From nobody Tue Dec 16 11:05:30 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D0B1270554; Tue, 27 May 2025 13:05:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748351156; cv=none; b=Iif7C/HvZ3K9MVa733Mub6fLazzcS8RoGLXALIxAKC+Vd9ia1m6I5GtOZSNwA2vcGjU2hqlboXvfKu/mdzkN5N4Aho2Am9J7rbmoWaQvnFms2HzcODnTICRtXI/ipKEEAVfOfu9y3RifaWVTg5I70WSxPxcJKWT6CCvjJ0IFdMw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748351156; c=relaxed/simple; bh=JFGvdaunIPSBqQz++xJiJxHCkckY0McbC4SfaFn0yuc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=OT6pWe4PdvpmWxs08fbuT0HFTJRXY2pI/P1Ytl92d4Br3iqJRDu+xyvsLayaBJHh0mTOhdBCzcOcWC0dIWDThW7y26Oz9nyeqkO3oDM0m+h7aKnVJDQEBF2abGkgD05Mz+C+4YcJO2GoYLRyc/wef0AJwDoJv/j2hrNE+JLUz/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=oZonfTbc; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="oZonfTbc" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54R9XLmJ031268; Tue, 27 May 2025 15:05:44 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= Xt2bCMTIvh87COE2sGKEmCIvYsCqTkRKv6pvRr+MTSc=; b=oZonfTbcryO3BEhb yy9lD0nt4kTjfJ6wItrXG1td105+XN+feeYvad32VZXP6IKqN6ZOP2r56mB81nFO Q+HVZxrq+iXaDky5D6pzPuApi+M/cWS0lIYRE88Pf0u3Bqw5mx2LFJiS18odi/yu TFP6fvfiWEB2Q9Uj8rfuWF8/A8GfCBVJMBZHnsfjAW0tJPl/FD9JS9KDvGL3F6e2 0ljDPZlsPGOwn8Voc4PApJ7DMTmnj2XdcOz/nnPm7qYWktwetftiQA1VF9m6ujWX m8wFnPP2UsVGjAiyW7qgqbunYro+QLPKMhar1NQqo+zp5hVGiC3Z9qm7SIcCWA3m +WH/rQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 46uqp4j1nt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 May 2025 15:05:43 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3EAE140055; Tue, 27 May 2025 15:04:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 970A6AE078E; Tue, 27 May 2025 15:03:47 +0200 (CEST) Received: from localhost (10.48.86.139) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 15:03:47 +0200 From: Amelie Delaunay Date: Tue, 27 May 2025 15:03:17 +0200 Subject: [PATCH 1/5] ARM: dts: stm32: fullfill diversity with OPP for STM32M15x SOCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250527-stm32mp157f-dk2-v1-1-8aef885a4928@foss.st.com> References: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> In-Reply-To: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 From: Alexandre Torgue This commit creates new files to manage security features and supported OPP on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information: -Y =3D A means no cryp IP and no secure boot + A7-CPU@650MHz. -Y =3D C means cryp IP + optee + secure boot + A7-CPU@650MHz. -Y =3D D means no cryp IP and no secure boot + A7-CPU@800MHz. -Y =3D F means cryp IP + optee + secure boot + A7-CPU@800MHz. It fullfills the initial STM32MP15x SoC diversity introduced by commit 0eda69b6c5f9 ("ARM: dts: stm32: Manage security diversity for STM32M15x SOCs"). Signed-off-by: Alexandre Torgue Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/st/stm32mp15xa.dtsi | 5 +++++ arch/arm/boot/dts/st/stm32mp15xc.dtsi | 4 +++- arch/arm/boot/dts/st/stm32mp15xd.dtsi | 5 +++++ arch/arm/boot/dts/st/stm32mp15xf.dtsi | 20 ++++++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xa.dtsi b/arch/arm/boot/dts/st/s= tm32mp15xa.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cb55f5966f74011d12d7a5c6ad0= 47569d25d4e98 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xa.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelec= tronics. + */ diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/s= tm32mp15xc.dtsi index 97465717f932fc223647af76e88a6182cf3c870f..4d30a2a537f15c1e145635b090d= e0f0222526579 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -1,9 +1,11 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2019 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectroni= cs. */ =20 +#include "stm32mp15xa.dtsi" + &etzpc { cryp1: cryp@54001000 { compatible =3D "st,stm32mp1-cryp"; diff --git a/arch/arm/boot/dts/st/stm32mp15xd.dtsi b/arch/arm/boot/dts/st/s= tm32mp15xd.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cb55f5966f74011d12d7a5c6ad0= 47569d25d4e98 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xd.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelec= tronics. + */ diff --git a/arch/arm/boot/dts/st/stm32mp15xf.dtsi b/arch/arm/boot/dts/st/s= tm32mp15xf.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..5f6a2952125d00d468e2e401202= 4f02380cfaa49 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xf.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelec= tronics. + */ + +#include "stm32mp15xd.dtsi" + +/ { + soc { + cryp1: cryp@54001000 { + compatible =3D "st,stm32mp1-cryp"; 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Tue, 27 May 2025 15:04:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 48C18AE0788; Tue, 27 May 2025 15:03:48 +0200 (CEST) Received: from localhost (10.48.86.139) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 15:03:48 +0200 From: Amelie Delaunay Date: Tue, 27 May 2025 15:03:18 +0200 Subject: [PATCH 2/5] ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250527-stm32mp157f-dk2-v1-2-8aef885a4928@foss.st.com> References: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> In-Reply-To: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 Adopt generic node name 'typec' for stusb1600, which is the USB Type-C controller on stm32mp157x Discovery Kits. Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/= st/stm32mp15xx-dkx.dtsi index a5511b1f0ce306feea5d8657721b078161d01a36..276ed2c9be71cc59891e9b06cb0= 57ce4ff8a143e 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -254,7 +254,7 @@ &i2c4 { /delete-property/dmas; /delete-property/dma-names; =20 - stusb1600@28 { + stusb1600: typec@28 { compatible =3D "st,stusb1600"; reg =3D <0x28>; interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; --=20 2.25.1 From nobody Tue Dec 16 11:05:30 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC1F226FDB3; Tue, 27 May 2025 13:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 27 May 2025 15:05:26 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3E75040050; Tue, 27 May 2025 15:04:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 055F4AE079F; Tue, 27 May 2025 15:03:49 +0200 (CEST) Received: from localhost (10.48.86.139) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 15:03:48 +0200 From: Amelie Delaunay Date: Tue, 27 May 2025 15:03:19 +0200 Subject: [PATCH 3/5] dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250527-stm32mp157f-dk2-v1-3-8aef885a4928@foss.st.com> References: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> In-Reply-To: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Etienne Carriere X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 From: Etienne Carriere These bindings will be used for the SCMI voltage domain. Signed-off-by: Etienne Carriere Signed-off-by: Amelie Delaunay --- .../dt-bindings/regulator/st,stm32mp15-regulator.h | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/inclu= de/dt-bindings/regulator/st,stm32mp15-regulator.h new file mode 100644 index 0000000000000000000000000000000000000000..8605b12b2aa7de6b14ec32bf877= 8ce94ecbe4bc2 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H + +/* SCMI voltage domain identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 3 +#define VOLTD_SCMI_STPMIC1_BUCK2 4 +#define VOLTD_SCMI_STPMIC1_BUCK3 5 +#define VOLTD_SCMI_STPMIC1_BUCK4 6 +#define VOLTD_SCMI_STPMIC1_LDO1 7 +#define VOLTD_SCMI_STPMIC1_LDO2 8 +#define VOLTD_SCMI_STPMIC1_LDO3 9 +#define VOLTD_SCMI_STPMIC1_LDO4 10 +#define VOLTD_SCMI_STPMIC1_LDO5 11 +#define VOLTD_SCMI_STPMIC1_LDO6 12 +#define VOLTD_SCMI_STPMIC1_VREFDDR 13 +#define VOLTD_SCMI_STPMIC1_BOOST 14 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 15 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 16 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */ --=20 2.25.1 From nobody Tue Dec 16 11:05:30 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 954E526FD9F; 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Tue, 27 May 2025 15:06:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5F97440049; Tue, 27 May 2025 15:04:39 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A806CAE07A5; Tue, 27 May 2025 15:03:49 +0200 (CEST) Received: from localhost (10.48.86.139) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 15:03:49 +0200 From: Amelie Delaunay Date: Tue, 27 May 2025 15:03:20 +0200 Subject: [PATCH 4/5] dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250527-stm32mp157f-dk2-v1-4-8aef885a4928@foss.st.com> References: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> In-Reply-To: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani , Conor Dooley X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 From: Himanshu Bhavani Add the "st,stm32mp157f-dk2" compatible string to the STM32 SoC bindings. The MP157F is functionally similar to the MP157C. Acked-by: Conor Dooley Signed-off-by: Himanshu Bhavani Signed-off-by: Amelie Delaunay --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index 408532504a24d5e570c738b16de30dcf8deead6a..ad144c02eb7edf4fc2191ab0af2= 44342dcaa59d5 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -121,6 +121,7 @@ properties: - st,stm32mp157a-dk1-scmi - st,stm32mp157c-dk2 - st,stm32mp157c-dk2-scmi + - st,stm32mp157f-dk2 - const: st,stm32mp157 =20 - items: --=20 2.25.1 From nobody Tue Dec 16 11:05:30 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77C18271458; 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Tue, 27 May 2025 15:05:38 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3E89040051; Tue, 27 May 2025 15:04:32 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 64843AE080F; Tue, 27 May 2025 15:03:50 +0200 (CEST) Received: from localhost (10.48.86.139) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 15:03:50 +0200 From: Amelie Delaunay Date: Tue, 27 May 2025 15:03:21 +0200 Subject: [PATCH 5/5] ARM: dts: stm32: add stm32mp157f-dk2 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250527-stm32mp157f-dk2-v1-5-8aef885a4928@foss.st.com> References: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> In-Reply-To: <20250527-stm32mp157f-dk2-v1-0-8aef885a4928@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same level of feature than a STM32MP157C SOC but A7 clock frequency can reach 800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi. As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE SCMI services for SoC clock and reset controllers resources, and for PMIC, now under OP-TEE control. That's why stm32mp157x-dk2-scmi.dtsi is introduced, to move all clocks, resets and regulators to SCMI-based ones. To "disable" SCMI, just need to comment stm32mp157x-dk2-scmi.dtsi inclusion and to replace &scmi_v3v3 with &v3v3, then to enable i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for dual role with type-C support if needed. Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 174 +++++++++++++++++ arch/arm/boot/dts/st/stm32mp157x-dk2-scmi.dtsi | 252 +++++++++++++++++++++= ++++ 3 files changed, 427 insertions(+) diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index cc9948b9870f7f73629573149bfd342af75b07da..8e17a4a847a385b677df6f3a34e= 943ae4368a068 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-dk2-scmi.dtb \ + stm32mp157f-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ed1-scmi.dtb \ stm32mp157c-emsbc-argon.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157f-dk2.dts new file mode 100644 index 0000000000000000000000000000000000000000..c40e22a6737df075563c93b0b46= 0a00d5ede376c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectr= onics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xf.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" +#include "stm32mp157x-dk2-scmi.dtsi" + +/ { + model =3D "STMicroelectronics STM32MP157F-DK2 Discovery Board"; + compatible =3D "st,stm32mp157f-dk2", "st,stm32mp157"; + + aliases { + ethernet0 =3D ðernet0; + serial3 =3D &usart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&gpioh 4 GPIO_ACTIVE_LOW>; + }; +}; + +&cryp1 { + status =3D "okay"; +}; + +&dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "orisetech,otm8009a"; + reg =3D <0>; + reset-gpios =3D <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + }; +}; + +&dsi_in { + remote-endpoint =3D <<dc_ep1_out>; +}; + +&dsi_out { + remote-endpoint =3D <&panel_in>; +}; + +&i2c1 { + touchscreen@38 { + compatible =3D "focaltech,ft6236"; + reg =3D <0x38>; + interrupts =3D <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpiof>; + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <800>; + status =3D "okay"; + }; +}; + +/* I2C4 is managed by OP-TEE */ +&i2c4 { + status =3D "disabled"; + + /* i2c4 subnodes, which won't be managed by Linux */ + typec@28 { + status =3D "disabled"; + connector { + status =3D "disabled"; + }; + }; + + stpmic@33 { + status =3D "disabled"; + }; +}; + +<dc { + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ltdc_ep1_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dsi_in>; + }; + }; +}; + +&rtc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_rsvd_pins_a>; + + rtc_lsco_pins_a: rtc-lsco-0 { + pins =3D "out2_rmp"; + function =3D "lsco"; + }; +}; + +/* Wifi */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a>; + non-removable; + cap-sdio-irq; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + mmc-pwrseq =3D <&wifi_pwrseq>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + brcmf: wifi@1 { + reg =3D <1>; + compatible =3D "brcm,bcm4329-fmac"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_lsco_pins_a>; + }; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&usart2_pins_c>; + pinctrl-1 =3D <&usart2_sleep_pins_c>; + pinctrl-2 =3D <&usart2_idle_pins_c>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + shutdown-gpios =3D <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible =3D "brcm,bcm43438-bt"; + max-speed =3D <3000000>; + vbat-supply =3D <&scmi_v3v3>; + vddio-supply =3D <&scmi_v3v3>; + }; +}; + +/* Since I2C4 is disabled, STUSB1600 is also disabled so there is no Type-= C support */ +&usbotg_hs { + dr_mode =3D "peripheral"; + role-switch-default-mode =3D "peripheral"; + /* + * Forcing dr_mode =3D "peripheral"/"role-switch-default-mode =3D "periph= eral"; + * will cause the pull-up on D+/D- to be raised as soon as the OTG is con= figured at runtime, + * regardless of the presence of VBUS. Notice that on self-powered device= s like + * stm32mp157f-dk2, this isn't compliant with the USB standard. That's wh= y usbotg_hs is kept + * disabled here. + */ + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157x-dk2-scmi.dtsi b/arch/arm/boot= /dts/st/stm32mp157x-dk2-scmi.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0c55203ae1520029abcda3bb475= 13815d0c4bfc1 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157x-dk2-scmi.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectr= onics. + */ + +#include +#include "stm32mp15-scmi.dtsi" + +/ { + reserved-memory { + optee@de000000 { + reg =3D <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&adc { + vdd-supply =3D <&scmi_vdd>; + vdda-supply =3D <&scmi_vdd>; +}; + +&cpu0 { + clocks =3D <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks =3D <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks =3D <&scmi_clk CK_SCMI_CRYP1>; + resets =3D <&scmi_reset RST_SCMI_CRYP1>; +}; + +&cs42l51 { + VL-supply =3D <&scmi_v3v3>; + VD-supply =3D <&scmi_v1v8_audio>; + VA-supply =3D <&scmi_v1v8_audio>; + VAHP-supply =3D <&scmi_v1v8_audio>; +}; + +&dsi { + phy-dsi-supply =3D <&scmi_reg18>; + clocks =3D <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks =3D <&scmi_clk CK_SCMI_HASH1>; + resets =3D <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + hdmi-transmitter@39 { + iovcc-supply =3D <&scmi_v3v3_hdmi>; + cvcc12-supply =3D <&scmi_v1v2_hdmi>; + }; +}; + +&iwdg2 { + clocks =3D <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets =3D <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names =3D "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets =3D <&scmi_reset RST_SCMI_MDMA>; +}; + +&optee { + interrupt-parent =3D <&intc>; + interrupts =3D ; +}; + +&pwr_regulators { + vdd-supply =3D <&scmi_vdd>; + vdd_3v3_usbfs-supply =3D <&scmi_vdd_usb>; + status =3D "disabled"; +}; + +&rcc { + compatible =3D "st,stm32mp1-rcc-secure", "syscon"; + clock-names =3D "hse", "hsi", "csi", "lse", "lsi"; + clocks =3D <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks =3D <&scmi_clk CK_SCMI_RNG1>; + resets =3D <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi_reguls { + scmi_vddcore: regulator@3 { + reg =3D ; + regulator-name =3D "vddcore"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * regulator-over-current-protection; + * regulator-initial-mode =3D <0>; + */ + }; + + scmi_vdd: regulator@5 { + reg =3D ; + regulator-name =3D "vdd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * regulator-over-current-protection; + * regulator-initial-mode =3D <0>; + * st,mask-reset; + */ + }; + + scmi_v3v3: regulator@6 { + reg =3D ; + regulator-name =3D "v3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * regulator-over-current-protection; + * regulator-initial-mode =3D <0>; + */ + }; + + scmi_v1v8_audio: regulator@7 { + reg =3D ; + regulator-name =3D "v1v8_audio"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_v3v3_hdmi: regulator@8 { + reg =3D ; + regulator-name =3D "v3v3_hdmi"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_vdd_usb: regulator@a { + reg =3D ; + regulator-name =3D "vdd_usb"; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_vdda: regulator@b { + reg =3D ; + regulator-name =3D "vdda"; + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <2900000>; + regulator-boot-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_v1v2_hdmi: regulator@c { + reg =3D ; + regulator-name =3D "v1v2_hdmi"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_vbus_otg: regulator@f { + reg =3D ; + regulator-name =3D "vbus_otg"; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + */ + }; + + scmi_vbus_sw: regulator@10 { + reg =3D ; + regulator-name =3D "vbus_sw"; + /* + * Not supported by SCMI regu, handled in SCMI server + * interrupts =3D ; + * regulator-active-discharge =3D <1>; + */ + }; +}; + +&sdmmc1 { + vmmc-supply =3D <&scmi_v3v3>; +}; + +&sdmmc3 { + vmmc-supply =3D <&scmi_v3v3>; +}; + +&usbh_ehci { + hub@1 { + vdd-supply =3D <&scmi_v3v3>; + }; +}; + +&usbphyc_port0 { + phy-supply =3D <&scmi_vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply =3D <&scmi_vdd_usb>; +}; + +&vrefbuf { + vdda-supply =3D <&scmi_vdd>; +}; --=20 2.25.1