From nobody Mon Feb 9 09:06:40 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 767EC74420 for ; Tue, 27 May 2025 21:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379899; cv=none; b=C3UyKxan/5MeaAO2p9b96DPBrP4vMZX8tYLYk2MgMXdzXo0xDrkdWiPXt8YxUjHm6E8rFAY3o6trLUj5ALin5HekIwt6tvSiH2SxtC2Xq9L2oIWL3hy4K49tIt9ggvy2h5Sz/CpfV9MqLa84EVUZtlNVsjyxfCZSK2kjT48aAkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379899; c=relaxed/simple; bh=5FExpQUZ/FHZEchRY6UIA2qfjFJXzxNKpcsVYOWNwso=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NP2gkpKtRMC8lTfukOEF8dz2PYdKDrdT5kDVHUZhuh7CRR1ZIm7kRClebrT2ceiLLhn5O8esXLV5xYUYPem08DNeeWgyhBJTMgwseIiddo9k/FHIzLZHIk29JjKLxP4+PDZVEtadGUnlaranH6aiOa7C/hKBjjpvl9smRzPO1FU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OyTIxGaN; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OyTIxGaN" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RJdYQL010449 for ; Tue, 27 May 2025 21:04:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 63TelnMaZLywwjt0ZE9rQRxentiOmbDDz3cY3YJGWYQ=; b=OyTIxGaN6HeRDMcx xggCgzI1x739zuaZPZkK/Z17fZFI0xZzNM/YZTFgTheQtJbDdNXhYKBxKf+W5MN2 DX8XrPOieMGaVw9TjzUVF4PkLqbtw5/UOSGvxncP4jZB4c+ONewBgvuoXu/L4LMS RsVbMLBofHwDTxffM9mQV2K24JGIDxD8dXqbpYoYLqfHpWrJmehsl1O5ZhwyHgI+ PAnUyDcepMBh4K5Xs0pqa6+UZZCPwpClbD1RYn9hv8bOjITC9PG6585FidoNAWSK aSzs98QMYwA0XAQESPVxSAqKW1RLbIFbSw7z7WslNtOr+t5ckkJkntlD807oyV0f Y6Qzjw== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46u3fq8e0r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:04:56 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-742c00c9044so2957850b3a.0 for ; Tue, 27 May 2025 14:04:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379895; x=1748984695; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=63TelnMaZLywwjt0ZE9rQRxentiOmbDDz3cY3YJGWYQ=; b=iRW34EJvor60JNaRNVcysfHvNjErk2wk0YZzHW9E/T3UVQIqkB+ZR/JY6Sr2+baANs gFMuIeFJlsKzki3hxvbnu3cC0auGZYk+2dPdlYUKdMfj56iij20qDhd/33LRmfulVqsD /P7xC7+tMEUchl8gnMmSzNX1vrVQ7P7iGw7bR83nLgdVwFLf6rC6O/8VYpEzzGlm1aFG tRwtCZhXqer+fnHshwMq4QcCiMNNwdvcJK4NgJenaM+KgOc/ahuQlXNjuWLZv/pQolE3 2HWIbKSL9POYgGJa1SgHZBOf5GqAFnX8aDtlb/+wgPz6e3sNK6HUb9fYU06or52aE1MT tsVg== X-Forwarded-Encrypted: i=1; AJvYcCXJQrJ3QAQJ11yshhqRLulCGZ3nbIHKpJqhTT4pMeCF7kcXVm4ZEpkqxeqDcJ/Bo08NZEzkrfjucQ8nHpo=@vger.kernel.org X-Gm-Message-State: AOJu0YwGj2nLBVICXUI9+42TeZ7Yfsg9Q5U0qkbShs6LbnEg6DpB+XOq BjixKKN9kf50FiMD76a1fz9Hiac3z9/3cZaHRaINuQN1wHXpmvefAWgKIzU1WYick0XDuVRS063 VfKDoARI4CXvQmhnZnhH5YEXgCD8rn+xIxsUbrGxhbazT1jKOQgBd2kczjJEYU4hwVU4= X-Gm-Gg: ASbGncun/ylO8fdEcCKf1lSSQC0LYkwHkbkapCFpGWHx49XV2LfQqj5hfWJcv9HenlX DmDNsN7j98MzRNls3aaluskfRl3Mvxq7Jn7IKpeqjNgvrD9Rugb9FrEqLDvqDTRT1vLZ4TCBKDS qOfIrm395nEhnbWvqFE40YptjgaNEZtqxDIqH0yzLfhkKwHC4pkVxyblCP6sSWpKt99vzSxBe3V Q95EhIGUX9PO6yO+yGK3/LPt+AHZ7oGvoRT4nk7g4tMcLzxaks3Vrk4mVmMBc0P79hMPtvC/6tE UofDxRRyGhEySRYAq7/gUF9qSKzPhuZzxtfmG/5M01wIy9aOcO1sFx2Aig+fl9Tv++o= X-Received: by 2002:a05:6a00:a22:b0:742:a82b:abeb with SMTP id d2e1a72fcca58-745fdf3f47amr20526679b3a.2.1748379894983; Tue, 27 May 2025 14:04:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVTU4ArnKS3XUx/KYBpdSClXfXaPefEciMMvAQUuS6TJ1WcP5QX4l+NUAEE9Sq/8WhMbuLTw== X-Received: by 2002:a05:6a00:a22:b0:742:a82b:abeb with SMTP id d2e1a72fcca58-745fdf3f47amr20526638b3a.2.1748379894549; Tue, 27 May 2025 14:04:54 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:04:54 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:37 -0700 Subject: [PATCH v6 01/10] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-1-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=1370; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=8DqyV8lJU3L/SgQ/5n/G4b54XOO0JVKsEdNPv+HKEao=; b=o1YRULItzlopd45+R1RF7yTgwH4zsRX84NLJyscueOAZIq8dR/2R1drH5MEiKT449uZdTpeo/ nk9NUMT8WM6A2HSBqhs2UW4zZJSmRT2pJUyfWqLzvb98NRmaK1BG1O9 X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-GUID: Hlaww-worrYES_FApOTns0qeKKF9nAWB X-Proofpoint-ORIG-GUID: Hlaww-worrYES_FApOTns0qeKKF9nAWB X-Authority-Analysis: v=2.4 cv=X8FSKHTe c=1 sm=1 tr=0 ts=683628f8 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=bbY3M6C_flAL0yJJl3cA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX+gu43Jtxesc3 +6N2UkLTw5MxRKO9P9dfllzjiN/fxvzyTt7gXguJQTwqKXZ83SUIE0NI2Ho00/MUdaz+DKFdvsM /+BxhXStYwJbKZGOx6k0GOXbxeIdCN4oRLZOnXNSWvgf6Td7ottOPJMdOVBFAzkIdNnpPKfvnKp QzJ3qF1lVi13B8Onm/8s0tMt2Kc514Hh2HmxNUfqpA8PndUnqfC4SrJPmG1s9KBv5sbSdxWJnuh 8VgOGUKDP+PSKKxA2L2LCwKj0Za+iRt8d+70mgoi8isaYGmXg78mngK9E3lEotMxBQSobZvdYUG VM4+rtzJkfXcnSaLnQu5RwcMGhlzvbi3XqopNuZhymg4n+AA/cGNosjybKaTT0wcAbM6qaAWjW4 JRDGTw28wipS/2WfyNAkc47a5iv6cerc3h1U7nqf4Dv6RMGb7r23Mkbh6fo0ZbXMy6885z0T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=901 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng Add an entry to the compatible field for SM8750 for the QMP combo PHY. This handles the USB3 path for SM8750. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 358a6736a951ca5db7cff7385b3657976a667358..38ce04c35d945d0d8d319191c24= 1920810ee9005 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -29,6 +29,7 @@ properties: - qcom,sm8450-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy - qcom,sm8650-qmp-usb3-dp-phy + - qcom,sm8750-qmp-usb3-dp-phy - qcom,x1e80100-qmp-usb3-dp-phy =20 reg: @@ -133,6 +134,7 @@ allOf: - qcom,sm6350-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy - qcom,sm8650-qmp-usb3-dp-phy + - qcom,sm8750-qmp-usb3-dp-phy - qcom,x1e80100-qmp-usb3-dp-phy then: required: --=20 2.48.1 From nobody Mon Feb 9 09:06:40 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC167211299 for ; Tue, 27 May 2025 21:04:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379900; cv=none; b=hCDnOvJMcsbrzovgVRfwaMP8DR7Xdatw2BWuDJBr0Bt8BOv19Qlq3b8hBAPSgqgACce7n2nxpUXAoJ5kn9o9w+Xoe7PkY91+BXdKWoKTBAZmwVunLKaez9T+qt2iTjDg+Puv3Zhl6F0BviYQANCb2PvDPN+gCL4MennlKaCaC7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379900; c=relaxed/simple; bh=Fz5Xv5kyUKBPX7FBV3s+Hc184GjMe84b+FHiXhLBQqQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fe5fl9xvHLwCcpfwyWwChKr7UhjppvaePuzRpCjrb6yxzP0dx7Pi/L8FYbvoBpG6uRrYoTgCMe0OlopqOU56vP7APwADD/snrHOpyJ4AfXZTuo2x0NeI5/Q0lqkkuSjc79eg/DHnN6iIO/k8Ctz+CBNbYpi9i1EW85/fxKq2KCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=BMjK2La9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="BMjK2La9" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RFW31a027799 for ; Tue, 27 May 2025 21:04:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yWhw1LvOhszFsVVXvJgT1USSc8+4N0aEBK16X6WxLSo=; b=BMjK2La916AdOnI6 lzQQ9SL18WKflK2peCZr8vrC450kRR5I8FDfuL5Pj+GkL8I7Rv9a4P9kDncVKXhM dWm826x6Vj4bcq8rJ2bV9duZRQgUoldLVYjQynNoMSbwgmNJJeH4q1yheR54s7b1 gzHijNHQ1PRSzblnFIb4/kwrupmvXYlEM/+24dkqiwpP2qNr6ImaW/4ktiQy++Nx mf6wwLjaOEgMW91/Q00xJNjTfVf0pF67dS3gM5LD+d6DSLYPhgVwM5aGqTE/Iq9v 7F+Sp+WNciE5LGqCLXJkGJLP2236iK7u0V5yI1+5qszTY8ckSDbZK2z7omAn4Kno w2EInQ== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46w992j8ku-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:04:57 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-7401179b06fso3047143b3a.1 for ; Tue, 27 May 2025 14:04:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379897; x=1748984697; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWhw1LvOhszFsVVXvJgT1USSc8+4N0aEBK16X6WxLSo=; b=u8Hnw+9yozvwP6nRcmcrgvLnxXHTmh2LwlB7HkELxMZv0ewN73K5t1Py3msGiEqIdD o80k+h6u6b3O81Y6uJuA8ThsXwYii9PosPUn4F7FaCq3SEHX5ha+d8OMy0DYoPQk0snV 8iehLSaAY9ZsQtZp0kWRb4DcGfAZWJzf5fbWYtqZ5C2cexDXzW6Qe2tlZ8iM3DnJn2f2 FCBN3f7YJURLXkkOgQWaMpbF+uYLKizzbYzFh3kXXUunxRn8ViclgGfw9q4lqCdD5Ug5 /ylQn+V3mXZu9rAfcM3jomJCK8xZfhu0o9fBnWDwkVetyns5QwPzrRDj0M+qzDQKFqno vAWw== X-Forwarded-Encrypted: i=1; AJvYcCXzMZmzaMAWcZIE2hgsuuzawV+ND4dWgr4jYhkxHOUFYkYfBOsMv/rFo6B2dHSrjfS7rmy3somgPiDaf3U=@vger.kernel.org X-Gm-Message-State: AOJu0YwWHLCdjZsXYd0//WXTWXy3JI39vaF7mngduWoTna4/WTfzT6vV qVDHLFmY2+RaLaTmKixb6mJwVF+hs5MkQG2xOvdddiexw94jOJGsLMpu+ypdiZ0v5A0DI21IAGj VhDGtSt5ZX8OzHxzj/yTa8apHGRK2YyTDSgq9QymThYKs69YuWV/S7VPfn0bX2xI6xW0= X-Gm-Gg: ASbGnct2wzbPKn+AVQ9j5d0aJOXk/ZOUNZkv1S64prdjvrvHkb1S/d/sEDHgaI0UQI3 ZEUfGO44gz/fhs6H5nv4059VCyQdNQYskFAOY4M0B5FAg7r/Cp8XwktAn5zXtFvh/VYAgFGBg92 PoNiBRqLn3mMTXACUbUZVjEql3HG/Q9p11SwL72c92I6JaCyPRwzmIthNFbH3O1BRpyfmHvLVuZ p476a8/G2AqrlH94Edtb6hPGkWI1cJM2jJyYSzuRPFvr0jnP31sirKFKhyUTSXnH1D/9C0k4OiW alaFC5th6LGbfSo880gAdyRpaLUQUIultEUhaI4wI70xwCJSm1Q4HAlvXWKJId5QeHw= X-Received: by 2002:a05:6a00:10d4:b0:736:6ecd:8e32 with SMTP id d2e1a72fcca58-745fe079d33mr22845431b3a.21.1748379896594; Tue, 27 May 2025 14:04:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGmO+062jTwbk+EfgkjkNmUp7R+SdrABrfM3fDJ/G+vfmwLBFmJuRS/yzv+9kvtX5aAipJvAw== X-Received: by 2002:a05:6a00:10d4:b0:736:6ecd:8e32 with SMTP id d2e1a72fcca58-745fe079d33mr22845375b3a.21.1748379896160; Tue, 27 May 2025 14:04:56 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:04:55 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:38 -0700 Subject: [PATCH v6 02/10] dt-bindings: phy: Add the M31 based eUSB2 PHY bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-2-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=2425; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=Wud7UEFHXJQ0decZnINKeSi+hAdh0llCKpYCfH/oedY=; b=FY9GlYlq2N3inwoifO8SkqjWHfzym3tmZX9bN0v1+GLtkQYvAnQtIlcyN/BdOACenHmj7V2hZ v5nudmTRmjBB3osJUy0giMKvuZiEGeBQCXn1Nmhej2+rqFaHmkZ3juW X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX8k3YYAhOry9Q hlt8sqzR0UNUJwR2wg4yl+ZMbg6GQ003GaEVwVGML0hI5esuqs73MVzMrSEesY/yjalxqveVtUN RtwkLNflRV58xGId93+iRWdEM4Apzrrj39JD24Iq9N5xzICQjKYWnVAPtqu0gtOqjwqrgETyzNm QoAr9ClL6bXdOab3CtKZ258cZWwl3179GWtDYHA1JWP6Xwp8Ua2fiKqKWjzMjN1DUUkKkjiS/r9 39G8m8bZw3wcOlUyrzhpm6mC1TVF8gU3gHO6LdCngZ1fRtqkYwf5WtijRrKr2AHNOpTHloFGrfp dWmPXqfIm1drOHTuMRTagZqy56maprnDYf9XPey3Te6Lhydb7OCrY4bbi4NqePYWRORCFqEPfLr gdQvOEUylPH5Z3mqGWY6X7b7JPCPt+NJDdwYjG8GzAlVzagcHpTZwkoWQg9U1YnEs5WOqNpB X-Authority-Analysis: v=2.4 cv=Fes3xI+6 c=1 sm=1 tr=0 ts=683628f9 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=_ZfBLJ5mcqDn8hZp9PAA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: QtBD-zYiKu5vL_YDhMzEx3rTvyB_iiAA X-Proofpoint-ORIG-GUID: QtBD-zYiKu5vL_YDhMzEx3rTvyB_iiAA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the binding definition for the PHY driver. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- .../bindings/phy/qcom,m31-eusb2-phy.yaml | 79 ++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml = b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c84c62d0e8cbd9fc1c0da6538f4= 9149e5bc7e066 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,m31-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm M31 eUSB2 phy + +maintainers: + - Wesley Cheng + +description: + M31 based eUSB2 controller, which supports LS/FS/HS usb connectivity + on Qualcomm chipsets. It is paired with a eUSB2 repeater. + +properties: + compatible: + items: + - enum: + - qcom,sm8750-m31-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: reference clock + + clock-names: + items: + - const: ref + + resets: + maxItems: 1 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - vdd-supply + - vdda12-supply + +additionalProperties: false + +examples: + - | + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0x88e3000 0x29c>; + + clocks =3D <&tcsrcc_usb2_clkref_en>; + clock-names =3D "ref"; + + resets =3D <&gcc_qusb2phy_prim_bcr>; + + #phy-cells =3D <0>; + + vdd-supply =3D <&vreg_l2d_0p88>; + vdda12-supply =3D <&vreg_l3g_1p2>; + }; --=20 2.48.1 From nobody Mon Feb 9 09:06:40 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E3F2139C8 for ; Tue, 27 May 2025 21:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379901; cv=none; b=jFM3dJ1iGBxqOfRrMyzAyiKodrvQVE2Nfx7R2aQsYovDwguQ78BO8HAox981J3Ac3Ae+iNKtAc0P9zvN2aKCRif138NqHZed8N3JnVISdZfGVdmnsGisLGQkr6FFh3Vf6pBDcf/qG7nu/bYPqw+QILDeBP2WnmwzOW2rxyAlmOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379901; c=relaxed/simple; bh=NhOsYBi6tADTMUAiHJ0Qk3HAGnZPId0WGmI4bIdXuV8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aZz6KWsl+Ywch0TgF0BLT47SZ6khfMb+e9n2QbkRQIVaw7Vv5uiITWmTv+e5ju5WTQH3dxU2l5kVnMlkK2hoxGcNZWxJDmcXO1bUnmmV47FBkOPU0GXyzw0Y2S1Q+2nJPKfc2vaTlINRmkf3WcyOJGfiXB1lAetd9aJs0jnbxkY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FEmTkq5A; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FEmTkq5A" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RIQxBQ001558 for ; Tue, 27 May 2025 21:04:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 8gIhfclnLH073VsLY1ttHA/tXRnGUkM9HdwYW3xYCyA=; b=FEmTkq5ApBPdiyy7 fYfR93tebQ/gtSyFOXu9QDIhyhgfbwvc6f4hTt2Wm6kIecV/JYbRXGycx+Eh6suM MHaef/GAhoUyd3z7Fy0l09g4yLPwaZeGfU3zp+JLI/vyh+pu27QRoN0ckzPPByNO mWw2yZieD6yxPQLqZ72AHmDkq8Si6nEfvWhZnsZSGu4IKJlx80icxvPhkdKJjMmf C+P0znTmdcovkywfsnT2Mplic/KYKztLXEcdV2PtITKXgAiZ6t90wZwfftUH1X3I 1IF0WFfn1k0J+B2ZMR1tBNc+drLGFYDwYLKETg+XwARFFsZnGWMoJ6Dns8LjlR1W ttVgmA== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46wavksyeh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:04:59 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-7391d68617cso184229b3a.0 for ; Tue, 27 May 2025 14:04:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379898; x=1748984698; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gIhfclnLH073VsLY1ttHA/tXRnGUkM9HdwYW3xYCyA=; b=ZILlijERA19ijxwfbbue9dN+8EVCVhNgnIx4AAfBmfJuqiicyEQGcnDS1XTQ075fvA vHUeAms872jDOuwnbWyA4OCSGywzoXUcrk6HHXQqcOBY52DLW5AK5vpAf8X4veyhgeNH +5DqEeAJdFGgAoEyGkD7EnPogDUdBRjJmvDm/3D8zDb/oDiXzYzjmukBUzdFdL3K2L5Y Q+f8W+B59ubrg21sHQ7ixdqcV73kwSs8krlxk0jVdJsH72k42xrl8mfFOpPhskIGb2+A EdDsoEHED/tr0jy0ohpkCsl/fX4aMb2mBRNOKmlxFjrQj/JVtvY9EgJh9WP2EFYlnv20 sVbg== X-Forwarded-Encrypted: i=1; AJvYcCXnw9BdtoVBq9QqYHrQ/iqsq0aMRbzKs0vV6RiUtFitpK3KzXNWu3vcvqcMz1hCsHXApMOJxZQmP5JlP7o=@vger.kernel.org X-Gm-Message-State: AOJu0YyGIIYIOfl8OWP6wDUHWiKUzr25bfFKuj6SFAOpdYRI3V1FTaAy thvg5O4BRGASDEG7Xpm7vL8+C5QdeWDlTyMyqzHuaP9CWXxVgqsEeLMfghiVbg9ilrDxunD1Jbu AxPmCePr27yvELTCSUkWtLKolmLT/ij34axHrdtkFU85jtOq4MB6EzmRtCDrVSnpVRyaDR4ZRY8 E= X-Gm-Gg: ASbGncvwKLXTHdhiI6JVGbBIJ2m+ptvDBqjAZKJEAZ5fnfmU9rH64pdWtHAmjddTg/h PAWAFAFJ+p7Umy1m1E8Qqm/EM2MNSzT+v0ZabYdqqyV9R13S/0hJlSozW2tUYnz9vDOTSQr8sWc 5ovCT9LMUU55PpjnTK3O8+/b/8p38uKfPOjuFKcaVnwoJjd5/nrTlZwMVGoFSN3CGpYGffOgcTL hjo3XW5q5fVlRXN1UVa1PzsgJqOKdd9U+PAaKbmExw4ZDbfwBv7wXEe6OPea0WaLiNipWOB5LLn C+oAyos148hmvI5F5J+YyL65RqcE+SOk45IvkDjt4upb6Tf+RSSsjU2qOyCja0WHPjI= X-Received: by 2002:a05:6a00:3ccd:b0:736:4d05:2e35 with SMTP id d2e1a72fcca58-7462eae8737mr2671730b3a.3.1748379898164; Tue, 27 May 2025 14:04:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IErVuSX8VnhDC5c80QonelHr5ry9GAhDcphlE+t5DRrIAcd4JLsqfnIcR34CNcLszXepePuHg== X-Received: by 2002:a05:6a00:3ccd:b0:736:4d05:2e35 with SMTP id d2e1a72fcca58-7462eae8737mr2671698b3a.3.1748379897734; Tue, 27 May 2025 14:04:57 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:04:57 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:39 -0700 Subject: [PATCH v6 03/10] dt-bindings: usb: qcom,dwc3: Correct the SM8750 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-3-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=1199; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=NhOsYBi6tADTMUAiHJ0Qk3HAGnZPId0WGmI4bIdXuV8=; b=lobSYcFGVwh8sfpUcLjkgbtPofAxzVDKJAfkDY2FUYjTHx3YXT1XBfydR+LmUIt7NbMLEs17M 4Jec41PnZl5CSCqn6HniNcEqQYvBtscZOhyooMC3wXeStWPigeWIgmT X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-GUID: JbSJxUn734ACN-s06aBr2xncRhHNfaQ8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX+6cGZax2it2N w28LFMp9acBK0Ym/ZXciymr94agL9qRWeBZPqrk/nOoLNslETGmJlrYMjKalBd5+J/Dl2yPaTJp Gt+sFG0Lobf6MuSTxBRVUNRIGdLI2IINYSEtBFsrLc+GYIjyI7g2pUaKg+8qD9FJzihg4ds8Ri4 xpCuDEmU66+xkijNIt7YSP6bCHFWPHKxwY194fqrZIGvPWFdediaxO522uahV1jr5zBYwwJwvvq id4QlcXJhgACAHcOkQCbxFvkKO1Z7pvObLRP81YH2utTCaBZLblOSqLqYEEZTWddaqDILenOsis efxXR1uZDEo3zpmontGITMtn2jOPAd+QZ9NS4vgSPYxwFif6v2vp9wkU+HuLU4SIPR9uFCJesFd 4P+rOBmtG/kPCn2BRNTk8pHG4eRZpLvHtWn+cULVlzdys46HVrfiO4pU8NkqWlxiJOkR9nWD X-Authority-Analysis: v=2.4 cv=fMk53Yae c=1 sm=1 tr=0 ts=683628fb cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=qiVRAF7mJj4RLuWAUSQA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: JbSJxUn734ACN-s06aBr2xncRhHNfaQ8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=498 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 SM8750 does not require an XO clock in the dt as it is the parent of the TCSR refclk_src, so move the compatible to a section where the XO clock is not required. Acked-by: Krzysztof Kozlowski Signed-off-by: Melody Olvera --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documen= tation/devicetree/bindings/usb/qcom,dwc3.yaml index a792434c59db2e6ba2b9b3b8498ca43f0f8d1ec4..298b1472ccbc4cfeb04927da29e= a40b9883d03eb 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -227,6 +227,7 @@ allOf: - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm6350-dwc3 + - qcom,sm8750-dwc3 then: properties: clocks: @@ -366,7 +367,6 @@ allOf: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 - - qcom,sm8750-dwc3 then: properties: clocks: --=20 2.48.1 From nobody Mon Feb 9 09:06:40 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A19B5215773 for ; Tue, 27 May 2025 21:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379905; cv=none; b=VMU84WM2383oC1yrmeoIWkxcOhqO2QA0RJ/GQ+f2LU2nGXeteFwuDRE/ZyHU8gTKI82oBOAYT2DKIw2mHsTonAHHo91s5ilBeH+nzkqC+BmwkpMk+jrE6Jam2HrTp7b9LA1QRp00iQ4zU1ZemrWefJySX/gWTEgSOx8fZOu96Uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379905; c=relaxed/simple; bh=J0tw8GGO4wL9xTL2953azTtC4i28XE8iFK6L9NmPDPk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MMlbduzMZjflw0Gs4JenmIeqtTeEelSb+1zG9h8mfBZu0MRnsVyYQ0qDcMYa65UqiT8CFrxmeF6+0Ca5Yjp2gBcBqJrV7r1poYs7Bl379ryPoKJ0+LE9pNwjYf1f/yIu4vfPf8BOtpCRz4bufeLCDXVlNU3afY+l3Nvqvj0uJE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NwgKDGsF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NwgKDGsF" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RJiQok010166 for ; Tue, 27 May 2025 21:05:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XwsiqMrHhXwWSHFVyW3ahl2aL/W4hpaHEh0uYCGybzA=; b=NwgKDGsFjaRMbiDS ENiHHkn1S3fTRz0U2vlVPkF4r4HiGczud07k4S9qtAObgXHdC7lELuzZb8stp+EP 6sSR01hzFT1aF5YV/LnDpbmrLK/yc0wD6PqVBt6jnq0MHgc3JUrUqEF8qX2m5rDs 9CC/fEpv1/3JXkSQaWFmZ/LTFyoyQ0uN0704pLNjLkxERtMAPjOd1acTVQh03mhS HkZbyKVy3GuQ7VN0uiyUvrXD6+v5tfWt4YeoicKE73RnwErznMasJ/l2TJJ6Rlxt 3MG5RDzA5U5eGo/bbkU/fCdTj9J+h3mGtutk90BXdChwN/PMqwYcQRIW49x2OIVr 7ZhC8A== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46u6vjr8tn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:01 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-742a091d290so2604438b3a.3 for ; Tue, 27 May 2025 14:05:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379900; x=1748984700; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XwsiqMrHhXwWSHFVyW3ahl2aL/W4hpaHEh0uYCGybzA=; b=Ckuld9+ctTf9e5l0n3Nw39FEFoQASlmHIc+Dgr+758O8xquWIRwywGuRKMUGw3bb5s 0LHhmbrrwEekesQKHIVD/U14/cxDACOppgQd1IrHmJtOYSDjmE6APLTZfUOSN6VspAxp AQnbxCbq8/tPrqJ1LrBll011xu0AV7jHDQ3iXVC6oRo6T2aRaugbhTTTASGIDX60eMri ZNmaaJX3FmEH7nFvvNXwewDpKaAp+isECZNx9y15V66vhbdl+NDNJ9xm4Gk9GQVxZmcs LtxhHDaaLweRO+9nH/JsOxFXBb3BehOG0d5WgMd1EUf68wFY8NLxHhX15Z0LSaNkgQ8T beXQ== X-Forwarded-Encrypted: i=1; AJvYcCXkxHFglnkKV0u8jxILnRHcA6Ee8076OL5OAxrzBk7yiECQZ2VdDOpPQ8DfPpm4IHnriMRrJBTdJULoXXE=@vger.kernel.org X-Gm-Message-State: AOJu0YzJaMD+cqfSMWxMZj90sM29e6Bya+HutLFTvND74VLwkrBf6UrZ bK7QRviypHqj/1IHtcF2HD5zzn4s45TwCDG+VJEdRifhaYPEJOmzASlk2NMDjlcqNlFf99iPQvm IxdIyGzwvtybiR6Xg5wdhfuncjf0KfUFDG9IUSpPHq4WTEVaqG3moZ2To8EqJTUrTTKk= X-Gm-Gg: ASbGncs3shu0OIpjIE8vMZa5bdtsEvSmoixm0eogjrtpaKdC3bo2VxMSM13rpMGx0rG FkudqtEsCbogwKeXw75x1ZvJQORvtmOUMbpgY7czbyE3HHPqBOUZDCqB4HDSW4ObN1x0BkFJsTP dUx0wBcM4rnt9TFZHgVCiwltPYBGHebqTgwfE/eRBwcvwxzYh5EPBEse6yzZKt6GiEfBH1FCrAb D7xLG5DkUE1EBTVyWASLoDHnEnw6OXKBnIbXtXYSAbd0jLm35c1WppoYh878Ekjbvpqj47eJ4RN TW6L4+wdFj87vR6VXgtt9OU3lHTWXL98mZNQI+1vQcfoL+I9LKh3j8PjuUkl+Huf78k= X-Received: by 2002:a05:6a00:2385:b0:742:3fe0:8289 with SMTP id d2e1a72fcca58-745fe079dabmr22415747b3a.20.1748379899875; Tue, 27 May 2025 14:04:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHNr6nLqUCy88efY8I90G9SAJJTj4IMIaxleVpD90RLAKlWPk+f90BoItsBGFbM4jwAXq7LKQ== X-Received: by 2002:a05:6a00:2385:b0:742:3fe0:8289 with SMTP id d2e1a72fcca58-745fe079dabmr22415701b3a.20.1748379899345; Tue, 27 May 2025 14:04:59 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:04:58 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:40 -0700 Subject: [PATCH v6 04/10] phy: qcom: qmp-combo: Add new PHY sequences for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-4-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=24445; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=YThqfioeYZBJUrXEKMsbkrkjox9bIVbgzIu25TaOG04=; b=obz5koI+8QB3wOjMxzRYXFV1qu6+ZY2VRJInjtbg1LGgQ2p/FDhdTEeKPh4LlmM/v4kMkUVXF 7FIlQzxoBXuATLB/v3U7K38meqMlfdXutb9EtqtmgiG1inpMAdz00Yi X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Authority-Analysis: v=2.4 cv=UOXdHDfy c=1 sm=1 tr=0 ts=683628fd cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=UZBd9ZQXIvJYZa1OSmIA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: gnIPStjehbS6i5xph4LW8_H4qV2pR-6Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX8kaZ+uYnaF3e 5x2WyWO1knNSgwq03euiQfw7eJyz0BQcYvxb1Q9UWxSSk/w+JdD5YKWmsUaJOl8UkZYRFJFQNN0 aJ9Hb9P0d7RNirJbx8UmrhHmnEThLnKlCaZcx+G+O+v+EKxbOqUsQ41JvqP04rl1u+Fuc6sFFmS Nc3d16jeUcu5wA7rBMfKa4KpSrRQMHe5VyUfDoUUxifKyUmEyRsAmw7bsyxo8YOmlZ25jP/Lko7 oPeapH64fWKHW6nDRJBCh/jx74Crxj5/+H1SA3s62iz/PlW8K/dFwZUjB9pDWf9pA+mB1hPUMpF 35Rggwsr/4CrVn8QssvLsSG4uQSX4JB2/1f76N61fbc6ghekP16GwFeb08L2gi+K91G9KbWyN59 hWXz21ArUfD9COZiHxUncLbH1sc/ZAWIuCMHwmvXMfbE6rsJAyItUil3mNAq75CGWWCWqo1d X-Proofpoint-GUID: gnIPStjehbS6i5xph4LW8_H4qV2pR-6Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng Add new register offsets and PHY values for SM8750. Some of the previous definitions can be leveraged from older PHY versions as offsets within registers have not changed. This also adds the required PHY sequence that is recommended after running hardware characterization. Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 221 +++++++++++++++++= ++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h | 38 ++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h | 32 +++ drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 64 ++++++ .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h | 68 +++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 5 + 6 files changed, 428 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index b09fa00e9fe7db8d97b7179ee15d3f07fe578b0c..8b9710a9654ab1acf8419e7f871= 88cbc98f8714a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -32,6 +32,7 @@ #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-usb-v5.h" #include "phy-qcom-qmp-pcs-usb-v6.h" +#include "phy-qcom-qmp-pcs-usb-v8.h" =20 #include "phy-qcom-qmp-dp-com-v3.h" =20 @@ -212,6 +213,28 @@ static const unsigned int qmp_v6_n4_usb3phy_regs_layou= t[QPHY_LAYOUT_SIZE] =3D { [QPHY_TX_TRANSCEIVER_BIAS_EN] =3D QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, }; =20 +static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =3D= { + [QPHY_SW_RESET] =3D QPHY_V8_PCS_SW_RESET, + [QPHY_START_CTRL] =3D QPHY_V8_PCS_START_CONTROL, + [QPHY_PCS_STATUS] =3D QPHY_V8_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V8_PCS_POWER_DOWN_CONTROL, + + /* In PCS_USB */ + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] =3D QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] =3D QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEA= R, + + [QPHY_COM_RESETSM_CNTRL] =3D QSERDES_V8_COM_RESETSM_CNTRL, + [QPHY_COM_C_READY_STATUS] =3D QSERDES_V8_COM_C_READY_STATUS, + [QPHY_COM_CMN_STATUS] =3D QSERDES_V8_COM_CMN_STATUS, + [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, + + [QPHY_TX_TX_POL_INV] =3D QSERDES_V8_TX_TX_POL_INV, + [QPHY_TX_TX_DRV_LVL] =3D QSERDES_V8_TX_TX_DRV_LVL, + [QPHY_TX_TX_EMP_POST1_LVL] =3D QSERDES_V8_TX_TX_EMP_POST1_LVL, + [QPHY_TX_HIGHZ_DRVR_EN] =3D QSERDES_V8_TX_HIGHZ_DRVR_EN, + [QPHY_TX_TRANSCEIVER_BIAS_EN] =3D QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, +}; + static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), @@ -1471,6 +1494,139 @@ static const struct qmp_phy_init_tbl x1e80100_usb43= dp_pcs_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), }; =20 +static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), + QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), +}; + +static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), + + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), +}; + static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), @@ -1781,6 +1937,22 @@ static const struct qmp_combo_offsets qmp_combo_offs= ets_v5 =3D { .dp_dp_phy =3D 0x2200, }; =20 +static const struct qmp_combo_offsets qmp_combo_offsets_v8 =3D { + .com =3D 0x0000, + .txa =3D 0x1400, + .rxa =3D 0x1600, + .txb =3D 0x1800, + .rxb =3D 0x1a00, + .usb3_serdes =3D 0x1000, + .usb3_pcs_misc =3D 0x1c00, + .usb3_pcs =3D 0x1e00, + .usb3_pcs_usb =3D 0x2100, + .dp_serdes =3D 0x3000, + .dp_txa =3D 0x3400, + .dp_txb =3D 0x3800, + .dp_dp_phy =3D 0x3c00, +}; + static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg =3D { .offsets =3D &qmp_combo_offsets_v3, =20 @@ -2280,6 +2452,51 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg= =3D { .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), }; =20 +static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v8, + + .serdes_tbl =3D sm8750_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8750_usb3_serdes_tbl), + .tx_tbl =3D sm8750_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8750_usb3_tx_tbl), + .rx_tbl =3D sm8750_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8750_usb3_rx_tbl), + .pcs_tbl =3D sm8750_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8750_usb3_pcs_tbl), + .pcs_usb_tbl =3D sm8750_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), + + .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v5_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v5_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v4_dp_aux_init, + .configure_dp_tx =3D qmp_v4_configure_dp_tx, + .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .calibrate_dp_phy =3D qmp_v4_calibrate_dp_phy, + + .regs =3D qmp_v8_usb3phy_regs_layout, + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), +}; + static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -3915,6 +4132,10 @@ static const struct of_device_id qmp_combo_of_match_= table[] =3D { .compatible =3D "qcom,sm8650-qmp-usb3-dp-phy", .data =3D &sm8650_usb3dpphy_cfg, }, + { + .compatible =3D "qcom,sm8750-qmp-usb3-dp-phy", + .data =3D &sm8750_usb3dpphy_cfg, + }, { .compatible =3D "qcom,x1e80100-qmp-usb3-dp-phy", .data =3D &x1e80100_usb3dpphy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-usb-v8.h new file mode 100644 index 0000000000000000000000000000000000000000..89ace8024bc0bde55b5a590f67d= 906b893c197a1 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V8_H_ +#define QCOM_PHY_QMP_PCS_USB_V8_H_ + +#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00 +#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04 +#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08 +#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c +#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10 +#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14 +#define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18 +#define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c +#define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20 +#define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24 +#define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28 +#define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c +#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30 +#define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34 +#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38 +#define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c +#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40 +#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44 +#define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48 +#define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c +#define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50 +#define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54 +#define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58 +#define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c +#define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60 +#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64 +#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68 +#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h b/drivers/phy/qualc= omm/phy-qcom-qmp-pcs-v8.h new file mode 100644 index 0000000000000000000000000000000000000000..169fd5de74747c8c9a833a629d8= 000875168a6ff --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V8_H_ +#define QCOM_PHY_QMP_PCS_V8_H_ + +/* Only for QMP V8 PHY - USB/PCIe PCS registers */ +#define QPHY_V8_PCS_SW_RESET 0x000 +#define QPHY_V8_PCS_PCS_STATUS1 0x014 +#define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V8_PCS_START_CONTROL 0x044 +#define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090 +#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V8_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V8_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V8_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V8_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h new file mode 100644 index 0000000000000000000000000000000000000000..d3b2292257bc521cb66562a5b6b= fae8dc8c92cc1 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V8_H_ + +/* Only for QMP V8 PHY - QSERDES COM registers */ +#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000 +#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004 +#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008 +#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010 +#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014 +#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018 +#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c +#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020 +#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024 +#define QSERDES_V8_COM_DEC_START_MODE1 0x028 +#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c +#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030 +#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034 +#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038 +#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c +#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048 +#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c +#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050 +#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054 +#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 +#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c +#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 +#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 +#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070 +#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 +#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 +#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 +#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 +#define QSERDES_V8_COM_DEC_START_MODE0 0x088 +#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c +#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 +#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 +#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 +#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 +#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac +#define QSERDES_V8_COM_BG_TIMER 0x0bc +#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 +#define QSERDES_V8_COM_SSC_PER1 0x0cc +#define QSERDES_V8_COM_SSC_PER2 0x0d0 +#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc +#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 +#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V8_COM_RESETSM_CNTRL 0x118 +#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V8_COM_CORE_CLK_EN 0x170 +#define QSERDES_V8_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 +#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 +#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac +#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 +#define QSERDES_V8_COM_CMN_STATUS 0x2c8 +#define QSERDES_V8_COM_C_READY_STATUS 0x2f0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h new file mode 100644 index 0000000000000000000000000000000000000000..4cb8b1708607ab35760fb15f3e5= 24872334d9b40 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_ + +#define QSERDES_V8_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V8_TX_TX_DRV_LVL 0x014 +#define QSERDES_V8_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V8_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V8_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V8_TX_TX_POL_INV 0x05c +#define QSERDES_V8_TX_LANE_MODE_1 0x084 +#define QSERDES_V8_TX_LANE_MODE_2 0x088 +#define QSERDES_V8_TX_LANE_MODE_3 0x08c +#define QSERDES_V8_TX_LANE_MODE_4 0x090 +#define QSERDES_V8_TX_LANE_MODE_5 0x094 +#define QSERDES_V8_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V8_TX_PI_QEC_CTRL 0x0e4 + +#define QSERDES_V8_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V8_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V8_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V8_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V8_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V8_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V8_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V8_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V8_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V8_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V8_RX_GM_CAL 0x0dc +#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V8_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V8_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V8_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V8_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V8_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V8_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V8_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V8_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V8_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V8_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V8_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V8_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V8_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V8_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V8_RX_VTH_CODE 0x1b0 +#define QSERDES_V8_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V8_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index d0f41e4aaa855fc3ee088afc833b214277b7e2b0..8148853ff275b0526cb47a158d3= 32af1d74e0abf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -30,6 +30,9 @@ #include "phy-qcom-qmp-qserdes-com-v7.h" #include "phy-qcom-qmp-qserdes-txrx-v7.h" =20 +#include "phy-qcom-qmp-qserdes-com-v8.h" +#include "phy-qcom-qmp-qserdes-txrx-v8.h" + #include "phy-qcom-qmp-qserdes-pll.h" =20 #include "phy-qcom-qmp-pcs-v2.h" @@ -52,6 +55,8 @@ =20 #include "phy-qcom-qmp-pcs-v7.h" =20 +#include "phy-qcom-qmp-pcs-v8.h" + /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17443215F42 for ; Tue, 27 May 2025 21:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379904; cv=none; b=IL5lEBYxzbkJOPT8QfOtIypEUFHlUcXHb6rZrwx0kypQuuAG2OIxcV0Os3CyFWHk/zrA/Z1k1sLh9jUUF5M8Fc1bVc7T1COS9FPZGmXi+LZOvKqG//COkWAeahlYsnTv0sZlyFhoz34p9iD8zDEFjsG63ZFOSC9lSiOts/YM+AI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379904; c=relaxed/simple; bh=KVQpBUxY898OgxHofMwBS3SQRdZueoxZf5ILA+twSEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oy+t20mpZj1LiqFYVpsxWOrz4osNGRh7aORk33a3bvVdOP6oFME8tdICaAw+r1MbXSfyv+pJxSswZuSpKa7LTiXu3vsagsOh2v3WvaHZ9yvCuHsZUnFbi9B9jSR5BmTRyRyQPVshNFG+rXWqGRqm6vARXzK+4qZmluum7vaGYbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ku8XGyGN; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ku8XGyGN" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RJ7YiL002142 for ; Tue, 27 May 2025 21:05:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vzRhl64Zv5yDqBHxQZ3cj4CWJj0+v77+Y3Pg3G7a3BU=; b=ku8XGyGNM0cD4O2p e/nfCt/gQVj1hNBbSv7MvO8P4az+FAp6b9N5ArvkdWR2iW8Hdv6/rvgkpecyuhFJ m3J0qfvmSsvPyRmJFA6Y9reIlgYRPoCkzRCT89oK491XFQBQPRJarRMRxVhBkQ0o zku//xs6drP+5+obIpRr+iMBYeXz5lT1M3RlbH2nkwX1xfpDGd/HoETNq9goUhXW KUxwj9tf+tHBWQdkFJUArrC3WoaaTu6w/0xHk1EOec29EgRILnNtPjRRaGRXkoOt T5n+Myo2nl4tVqLczaamkHpP9xlKMPZYUDc0bRVCwFfXcFkjjI13gsFzcjAsZAYa yNGXjw== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46wavksyeu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:02 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-740adfc7babso2885443b3a.0 for ; Tue, 27 May 2025 14:05:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379901; x=1748984701; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vzRhl64Zv5yDqBHxQZ3cj4CWJj0+v77+Y3Pg3G7a3BU=; b=MjgjamCPQmWURbNBUND3j1WPSrp3qgCBYFZURtOQrcmm9Hs59KN2LcuqgHr4hCKtP0 guRcx0VnLvg6rUqfyHLgCjegMWmnlhjH18o+WKoP8niU+1/koJXR6HwJv1QIevKMWTSa PX4HI7UEZhksVu3LZaFfGequ5c96xWCdiHbVqN71csGJGv+7Bd97r2M3L9C2KnID1zPZ C4e7TlXB0eQ9jbIz6/7yQMjpAAsZql0tOygTWYv+gdn8m2d25kEN40Sibwu/dqaHqBnT ntVMBIyNXpxIa7ZkEpET88CY/wsl33iW9TlwadtyiJ4cyAU+vTl9U3pp9qU050iZ6shD A3Xg== X-Forwarded-Encrypted: i=1; AJvYcCV+5r3afH6WRjhlBzleaFHGxd50K5gHp4J/IZUlwvhALaXlgKRM6WDoH1/z9XaV7AKjsSSexSmCimD0+Nw=@vger.kernel.org X-Gm-Message-State: AOJu0YxhjIHzOYhofjxdlWJMSGVBRkR2HMkgM7nUhunWbOXeGtDq+4Ky uZ6Tce1lIURuJQQdA0xevk98MYNCSo/vwKpK2MekGNLTUm8Swj2EfRmLoMRSTSyb89C3INrtCBd FP2rK3s9e+vrULHTT/JAfbN3dIlyn8ehJjA2trYnerb4sMXntbbCarEoOwfveCx72KTs= X-Gm-Gg: ASbGnctq5es9NN68zqQWaYhUChx0MihkjnnhN1wzbPAKCPmp9Q4uZEeeBdU8ACsnlXn 0gIVis7kTtodLj8iCT2QFf4+D6iJRS0dFpQoLqAXeElSLbZy97p9eYpcUrYuExsbGGpRPiwrO8+ 5Pqs9xZ7U4BrLjxi30YMmNOG87GZ19FzVCQy2HDORJ4xB2Ha1YFrMfyCjpQBXpwLW76sKB9BeNi JRTik+J5/Dr2Mg0esbVgCkjUAb2JVuldUNrWaaeVO4yhe9t92S6KAl+izo+0LChSaAuuL+Sh3k7 9YJAoV9o5/EzYcNjJZ0uw+Cvy+WVKZc2rm5D7QenUhTi9jUk76IS/qqBKY+tTMgynJ4= X-Received: by 2002:a05:6a21:3305:b0:1f5:87a0:60ed with SMTP id adf61e73a8af0-2188c289ab9mr22294728637.19.1748379901392; Tue, 27 May 2025 14:05:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFP42zUWXhEhoQN5IEHJjKv/vMbeqty1ztD8a25bRQwLQO3Db3gW3dczT8C8Tba1smWx7q+Lw== X-Received: by 2002:a05:6a21:3305:b0:1f5:87a0:60ed with SMTP id adf61e73a8af0-2188c289ab9mr22294694637.19.1748379900997; Tue, 27 May 2025 14:05:00 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:00 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:41 -0700 Subject: [PATCH v6 05/10] phy: qcom: Update description for QCOM based eUSB2 repeater Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-5-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio , Melody Olvera , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=1426; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=2C6aI5pd5BWhSTEhtHBak51NwjHm1CBTcKGDwCW84eg=; b=+RgrZ3qByHLV/U1fiMG21YBXz3FH3SWPCbcDLBDzvXvrqIQqU26M7grdrJWa2RNyA/AHze4N/ vb6chONnS/6B31yW7+693rVPVIUjPxlrSEsHR/5RkqyBCWY66Oqo6R6 X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-GUID: ZVBnQhx7suDcDPy9PfNAC78jc4sC4a_h X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfXzdVUHO42enoz 0nMuHOF/Kg3+ap/TKmAIwejIqo4vytERGOdcmza2pMgtLTqnG+ZNmdP6rZZjgQ8gIiAq2GFgV5B 3g6zDsDRzhK/ettVzEGoK58c0Q9c57a8Pc1AVfRoV6CNgjqG/V0gQ6RsLWRfoZ1rpU8YFe4jbpn d/v3Ra12tHlNX/cLR3YV6I/WpIsaevlNyqwawFNfXYsnm7yCpZ9roKFnhqssqCz7x3mTfzSrdEX 5ikjU3pV7AhVqs5kh5FsuEzWy7MezBRWnfORfdKEtJY1kODs8KUAoh6cwlXewVsTESyDPSztHp9 GcCweSfEbJc7YyBiAn9kmHWRtuBpgETSvRDMZd6wvtgkqVcflp4oz99bkCK+1CZoSgywqEn9x// a1w+QbVgn1Y/blDbUxB3SkZGJhAxVQkDU7Vu+mR10XUFT7tVt/5GYn9Xpx8JUeFsdehTB6K0 X-Authority-Analysis: v=2.4 cv=fMk53Yae c=1 sm=1 tr=0 ts=683628fe cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=2IHzoM5ujN45o2WKKn0A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: ZVBnQhx7suDcDPy9PfNAC78jc4sC4a_h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=942 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng The eUSB2 repeater that exists in the QCOM PMICs are utilized for several different eUSB2 PHY vendors, such as M31 or Synopsys. Hence, the wording needs to be updated to remove associations to a specific vendor. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- drivers/phy/qualcomm/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index ef14f4e33973cff4103d8ea3b07cfd62d344e450..85581b40e598814cb27d954e8c6= 3eba809702622 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -126,12 +126,12 @@ config PHY_QCOM_QUSB2 USB IPs on MSM SOCs. =20 config PHY_QCOM_EUSB2_REPEATER - tristate "Qualcomm SNPS eUSB2 Repeater Driver" + tristate "Qualcomm PMIC eUSB2 Repeater Driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) select GENERIC_PHY help - Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm - PMICs. The repeater is paired with a Synopsys eUSB2 Phy + Enable support for the USB high-speed eUSB2 repeater on Qualcomm + PMICs. The repeater is paired with a Synopsys or M31 eUSB2 Phy on Qualcomm SOCs. =20 config PHY_QCOM_M31_USB --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3713921767A for ; Tue, 27 May 2025 21:05:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379907; cv=none; b=KkY+JnKQ2hZ83+ywu4xi4atCbh1KXy8ZxlDIN7w3ko6fGcgnV+dJJSfSfNXncRQYihQEZENa5++cbB2+mXlbmToIVJRP8vyE7UmDrpmRC0jgTXYtbmYAVukZNfTxwRkfMhMR/yLke0Od8AlFGt5OdoUbsdpIpVqXlNgnqvu6Ii0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379907; c=relaxed/simple; bh=PevywGGapSAG4MFE6ngkqj2YuUx5aoI0ILq2Z2idU8w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mT+SG38RXbQ6KQlsUIiNkGUyvvF3OFPdvMDQH+MeLZHmJuMFqeOtnbhtpZS/zVB1p60bmaqnxlHg/NL3iEhDiBGecBWeILKc5h5pPp6lbRLo3q0kERbXIRRbqREsgZA718g15zhfTY4P2BrJkaj03Jwut9sv3bFKbXaJOQN5qKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kMCED8XF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kMCED8XF" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RIl3Mx001393 for ; Tue, 27 May 2025 21:05:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2/3HGUo2MtGRqntCaiBRNk9jwrbsOQcOGUX5HHY23Zo=; b=kMCED8XFAnVuLyPB tfN58tqCUjREwbjC9h3n4hveemLUyHrK4zxnlhGmdjxaR5Z8jAnVKT/Jq6niH4oI B5yn6SsEE8CU0mvStZq1ZZQAZxGU7DV8DXffV56uNXewTLscXh3yb2Owuv0FwrYw FciaK3an7I/tLiLq/bkaY+HaPlo/h2LrotyzqcxXVOc0iky0fhtDbhTEpfTkjF1R v4ZoMg9v5KO0/Po7xufxemlxqhVjJR7VUJzuVEpWIk6rP+CxUpTShX9FXPDyI2HJ dbfvwkGukAvt9zJwtobnYjXKVLSpqjTg7XVl6WalYxVXC0gaHdMo4Y6qrUtyI+Ju l5s/Jw== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46wavksyf4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:04 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-742c7227d7dso2696216b3a.2 for ; Tue, 27 May 2025 14:05:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379903; x=1748984703; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2/3HGUo2MtGRqntCaiBRNk9jwrbsOQcOGUX5HHY23Zo=; b=dZTDb6p7GU6WQDWR9h7D5eb5nBhNNGxzkUC4L7KysyEmYgptRTudaQgM/060o+Hzh6 DUWyby6wUC60g6T3pN1KGm4erMQ37btGRs8+U92WtZOuUSatOzkIlFkvk5BVGR4DdxZC deYlpUqfSY8bzynE5gYx+2Ci9B53WN1ZDM4yOw8a7HzglX0IbsPF8bwFi/gMwfpizXzO nuucB78yg2EWN0iUvwYmmCY8yp8Cy2oXeJ3K8Sp4e1vBH4tFS1sW++8eKCEMBpV4sZ5P bpyS1ztg663sC+c3bNtsO8k6zYMjEsNOJcG3EzQsAEET7lBdkBs71bLYJGYls/pGwguc 8Csw== X-Forwarded-Encrypted: i=1; AJvYcCXU5uR/hxcXK0FyNKpNQQvLocL4qIsun/Ir4ecij2mtPN3dDgUap+cm8MGXW6ZNE1suPrHjPOLFNi2LEcs=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6o7fq+O6j5OzB8/5MdEhtl9BZC0hUfvO5LIHZfQ13am0cCGMW H1r/cdGcDLO2S9nbCEttFskoyObGs7X+CBM+9j5ESoTZRbIdyxRAD3suVd4HCE+VSrg6Jcc3Sxl UiaKcrQPYAs+ILt4x4YmJOgK6+eeCrI3e25P5TUcUr+6gw/aOMJEhlYe8UDMxu5773ek= X-Gm-Gg: ASbGncuZjrPpTLQ6aW+gGn7FIaG0bLqy73O2v+urg9Lahd2UIpSIwe0yOeBLQ1w2keW Z+b4mTh6rPbXuOQ5X7+1PdD9pg0LTnq/CaQaVDt0q/llyGjurThGwdqT85jAdEito0nS3nCkw4j N+oCRfn0AsxdAHEtJ2E67XCWZkJDXl9pyIt1OKgTfZUctqKukHZ5yFRdsnqHO7SRoIT9GT0cAPP 9J4YCwNbzOrviF5B2CGFh822EhGQX2c5/qie0xG9apOshofNBMVelqMUvp/MaOE15+38ltGQObY xGa0yi2wAxg7zKHFcvcov7pNKjsqz9oGqTJAX966YSAzIjcahXKPdy28PqKTQrtaNyY= X-Received: by 2002:a05:6a21:3984:b0:215:e9aa:7fff with SMTP id adf61e73a8af0-2188c37406fmr24798608637.31.1748379903111; Tue, 27 May 2025 14:05:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGuurhrHN/MihCxAPYTt/pZCO41LXo0pEoLKI4JOXeYxLDBNhJJpMdGYa1LTYB3X3egWHfeDg== X-Received: by 2002:a05:6a21:3984:b0:215:e9aa:7fff with SMTP id adf61e73a8af0-2188c37406fmr24798572637.31.1748379902642; Tue, 27 May 2025 14:05:02 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:02 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:42 -0700 Subject: [PATCH v6 06/10] phy: qcom: Add M31 based eUSB2 PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-6-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=11792; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=B3fZATkj/ziFzRb18Hgq8kVogJTvn4JD0AIEU8tIdnM=; b=zFyHvhCZ7aXG2CwY/nglEMlUman9JRTGJ/BSwri+Fbn04n3KSWVnV/pKaZXUU4xKn3TSsP64W r6ntTRoeT5/DOrSt0IPODchwE9Kv1fBy1r/eUsUs6QXX/ZwJRgjJtvZ X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-GUID: 2WcFI4MuJwuKniRJ0_aC706gKYgBhz-n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX2DKXiEQ59dzK dVkSyRZ3+coN+WksxwmB0AOVuwAaEuGyyMxGIPnGdp31SeC3AHSiDFf57SWbcnOLtIjSLiEagfl hsasMft89BCpzzVJaqIKSKg0nMZfaDaj6qJZDxsajmm9JM3en64cXTZ2mg+RMD72OMv575k4dlu W3L9UsB5/1J+gC6UWS3Qf75V+/C3o40KRm+WZC9reQRQ0NkM3Fi8jR2QIyfer3PLgMDH3VfOIX1 2fpOVOeTI1mMs/FQ4cNxoJdxmJ30o0H5YrHvv3ZUrlASLcKeo/axMoQCluWezRyXsqivK/k397R wg5rzwoIEn7f/ik/WqYEz4s4++HqxCq73VE4Aym/a+9CGo0r9lLCLTvIen/Y3nEiT+uZ5MfymJ6 HRBasqNp6ZMCK/2+PE6rYb4Dc0VyabnXOQDe6TgRNUip1IapCGJSg9IAUO7W8cWyh21mBfMM X-Authority-Analysis: v=2.4 cv=fMk53Yae c=1 sm=1 tr=0 ts=68362900 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=SaPFg9MOAsmIOgfY5tUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2WcFI4MuJwuKniRJ0_aC706gKYgBhz-n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng SM8750 utilizes an eUSB2 PHY from M31. Add the initialization sequences to bring it out of reset and into an operational state. This differs to the M31 USB driver, in that the M31 eUSB2 driver will require a connection to an eUSB2 repeater. This PHY driver will handle the initialization of the associated eUSB2 repeater when required. Reviewed-by: Dmitry Baryshkov Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 325 ++++++++++++++++++++++++++= ++++ 3 files changed, 336 insertions(+) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 85581b40e598814cb27d954e8c63eba809702622..60a0ead127fa9f08749e1bc686e= 15cc5eb341c28 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -158,6 +158,16 @@ config PHY_QCOM_UNIPHY_PCIE_28LP handles PHY initialization, clock management required after resetting the hardware and power management. =20 +config PHY_QCOM_M31_EUSB + tristate "Qualcomm M31 eUSB2 PHY driver support" + depends on USB && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable this to support M31 EUSB2 PHY transceivers on Qualcomm + chips with DWC3 USB core. It supports initializing and cleaning + up of the associated USB repeater that is paired with the eUSB2 + PHY. + config PHY_QCOM_USB_HS tristate "Qualcomm USB HS PHY module" depends on USB_ULPI_BUS diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 3851e28a212d4a677a5b41805868f38b9ab49841..b71a6a0bed3f1489b1d07664ecd= 728f1db145986 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_QCOM_EDP) +=3D phy-qcom-edp.o obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) +=3D phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) +=3D phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_M31_USB) +=3D phy-qcom-m31.o +obj-$(CONFIG_PHY_QCOM_M31_EUSB) +=3D phy-qcom-m31-eusb2.o obj-$(CONFIG_PHY_QCOM_PCIE2) +=3D phy-qcom-pcie2.o =20 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) +=3D phy-qcom-qmp-combo.o phy-qcom-qmp-us= bc.o diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualco= mm/phy-qcom-m31-eusb2.c new file mode 100644 index 0000000000000000000000000000000000000000..9f02b8a78f6e2ffde9149bc5cf1= a454c8f0a2563 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define FSEL GENMASK(6, 4) +#define FSEL_38_4_MHZ_VAL (0x6) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define USB_PHY_CFG0 (0x94) +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define USB_PHY_CFG1 (0x154) +#define PLL_EN BIT(0) + +#define USB_PHY_FSEL_SEL (0xb8) +#define FSEL_SEL BIT(0) + +#define USB_PHY_XCFGI_39_32 (0x16c) +#define HSTX_PE GENMASK(3, 2) + +#define USB_PHY_XCFGI_71_64 (0x17c) +#define HSTX_SWING GENMASK(3, 0) + +#define USB_PHY_XCFGI_31_24 (0x168) +#define HSTX_SLEW GENMASK(2, 0) + +#define USB_PHY_XCFGI_7_0 (0x15c) +#define PLL_LOCK_TIME GENMASK(1, 0) + +#define M31_EUSB_PHY_INIT_CFG(o, b, v) \ +{ \ + .off =3D o, \ + .mask =3D b, \ + .val =3D v, \ +} + +struct m31_phy_tbl_entry { + u32 off; + u32 mask; + u32 val; +}; + +struct m31_eusb2_priv_data { + const struct m31_phy_tbl_entry *setup_seq; + unsigned int setup_seq_nregs; + const struct m31_phy_tbl_entry *override_seq; + unsigned int override_seq_nregs; + const struct m31_phy_tbl_entry *reset_seq; + unsigned int reset_seq_nregs; + unsigned int fsel; +}; + +static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] =3D { + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1), +}; + +static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] =3D { + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0), + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7), + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0), + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0), +}; + +static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] =3D { + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1), + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0), + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0), + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0), + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0), +}; + +static const struct regulator_bulk_data m31_eusb_phy_vregs[] =3D { + { .supply =3D "vdd" }, + { .supply =3D "vdda12" }, +}; + +#define M31_EUSB_NUM_VREGS ARRAY_SIZE(m31_eusb_phy_vregs) + +struct m31eusb2_phy { + struct phy *phy; + void __iomem *base; + const struct m31_eusb2_priv_data *data; + enum phy_mode mode; + + struct regulator_bulk_data *vregs; + struct clk *clk; + struct reset_control *reset; + + struct phy *repeater; +}; + +static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset, + const u32 mask, u32 val) +{ + u32 write_val; + u32 tmp; + + tmp =3D readl(base + offset); + tmp &=3D ~mask; + write_val =3D tmp | val; + + writel(write_val, base + offset); + + tmp =3D readl(base + offset); + tmp &=3D mask; + + if (tmp !=3D val) { + pr_err("write: %x to offset: %x FAILED\n", val, offset); + return -EINVAL; + } + + return 0; +} + +static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy, + const struct m31_phy_tbl_entry *tbl, + int num) +{ + int i; + int ret; + + for (i =3D 0 ; i < num; i++, tbl++) { + dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x", + tbl->off, tbl->mask, tbl->val); + + ret =3D m31eusb2_phy_write_readback(phy->base, + tbl->off, tbl->mask, + tbl->val << __ffs(tbl->mask)); + if (ret < 0) + return ret; + } + + return 0; +} + +static int m31eusb2_phy_set_mode(struct phy *uphy, enum phy_mode mode, int= submode) +{ + struct m31eusb2_phy *phy =3D phy_get_drvdata(uphy); + + phy->mode =3D mode; + + return phy_set_mode_ext(phy->repeater, mode, submode); +} + +static int m31eusb2_phy_init(struct phy *uphy) +{ + struct m31eusb2_phy *phy =3D phy_get_drvdata(uphy); + const struct m31_eusb2_priv_data *data =3D phy->data; + int ret; + + ret =3D regulator_bulk_enable(M31_EUSB_NUM_VREGS, phy->vregs); + if (ret) { + dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret); + return ret; + } + + ret =3D phy_init(phy->repeater); + if (ret) { + dev_err(&uphy->dev, "repeater init failed. %d\n", ret); + goto disable_vreg; + } + + ret =3D clk_prepare_enable(phy->clk); + if (ret) { + dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret); + goto disable_repeater; + } + + /* Perform phy reset */ + reset_control_assert(phy->reset); + udelay(5); + reset_control_deassert(phy->reset); + + m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs); + m31eusb2_phy_write_readback(phy->base, + USB_PHY_HS_PHY_CTRL_COMMON0, FSEL, + FIELD_PREP(FSEL, data->fsel)); + m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_n= regs); + m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs); + + return 0; + +disable_repeater: + phy_exit(phy->repeater); +disable_vreg: + regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs); + + return 0; +} + +static int m31eusb2_phy_exit(struct phy *uphy) +{ + struct m31eusb2_phy *phy =3D phy_get_drvdata(uphy); + + clk_disable_unprepare(phy->clk); + regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs); + phy_exit(phy->repeater); + + return 0; +} + +static const struct phy_ops m31eusb2_phy_gen_ops =3D { + .init =3D m31eusb2_phy_init, + .exit =3D m31eusb2_phy_exit, + .set_mode =3D m31eusb2_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int m31eusb2_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + const struct m31_eusb2_priv_data *data; + struct device *dev =3D &pdev->dev; + struct m31eusb2_phy *phy; + int ret; + + phy =3D devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + data =3D device_get_match_data(dev); + if (IS_ERR(data)) + return -EINVAL; + phy->data =3D data; + + phy->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + phy->reset =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(phy->reset)) + return PTR_ERR(phy->reset); + + phy->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(phy->clk)) + return dev_err_probe(dev, PTR_ERR(phy->clk), + "failed to get clk\n"); + + phy->phy =3D devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops); + if (IS_ERR(phy->phy)) + return dev_err_probe(dev, PTR_ERR(phy->phy), + "failed to create phy\n"); + + ret =3D devm_regulator_bulk_get_const(dev, M31_EUSB_NUM_VREGS, + m31_eusb_phy_vregs, &phy->vregs); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + + phy_set_drvdata(phy->phy, phy); + + phy->repeater =3D devm_of_phy_get_by_index(dev, dev->of_node, 0); + if (IS_ERR(phy->repeater)) + return dev_err_probe(dev, PTR_ERR(phy->repeater), + "failed to get repeater\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered M31 USB phy\n"); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct m31_eusb2_priv_data m31_eusb_v1_data =3D { + .setup_seq =3D m31_eusb2_setup_tbl, + .setup_seq_nregs =3D ARRAY_SIZE(m31_eusb2_setup_tbl), + .override_seq =3D m31_eusb_phy_override_tbl, + .override_seq_nregs =3D ARRAY_SIZE(m31_eusb_phy_override_tbl), + .reset_seq =3D m31_eusb_phy_reset_tbl, + .reset_seq_nregs =3D ARRAY_SIZE(m31_eusb_phy_reset_tbl), + .fsel =3D FSEL_38_4_MHZ_VAL, +}; + +static const struct of_device_id m31eusb2_phy_id_table[] =3D { + { .compatible =3D "qcom,sm8750-m31-eusb2-phy", .data =3D &m31_eusb_v1_dat= a }, + { }, +}; +MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table); + +static struct platform_driver m31eusb2_phy_driver =3D { + .probe =3D m31eusb2_phy_probe, + .driver =3D { + .name =3D "qcom-m31eusb2-phy", + .of_match_table =3D m31eusb2_phy_id_table, + }, +}; + +module_platform_driver(m31eusb2_phy_driver); + +MODULE_AUTHOR("Wesley Cheng "); +MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D2732185A8 for ; Tue, 27 May 2025 21:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379909; cv=none; b=ZfA3KEiIug4KqTFG/+XHAUvr5mdWIPzgNLH4TCorFxYJGfdSaTtu4KgiNAouRvFSahjNPjsrxs7lIeLC/4oOGvT7dAcmHYAOGr4Cd0fEGImRxGq+fwLi7FWHTthQayEQpTWj53fQmQjXYr3zfxqyWSmQLBRvFTFlKPhpQrGadpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379909; c=relaxed/simple; bh=ePo20IfBlWaDjd5XYF16s1b6NNlBz3KQ6V6aZLM8Uok=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S68cK9iNabX+tz4BkRA2Hp1MsNIaPMXOYyCT4QLuwP+AkPako4OCvsKP88S1P3PgT7okslMx9U+RDroUbxy2zhzRgoBRqglEn2f+rFNELs5dL9xkZI+WegJWUyFrZSlwYkjfFsYOtdhnVsndHLTyxyBGNRBceRkmPgakMGnyRLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nASkK0tz; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nASkK0tz" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RJoVvC004977 for ; Tue, 27 May 2025 21:05:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +R55bDvd2i6fMCr67D+fFGu07eFzF+YQ+BvBZJYOtis=; b=nASkK0tzI9M1YF1e ctEpsw+a2EFynb0E/6ceqpE8PeV4GAzsEDI9iYXQntOBVWTRIlHX9M7B9WM+fKLr 1hGJlfYIYMdLa+BsoguxUDJlsnJblXFi6ZxLuOdGoShuc9aBYgZ4fzmGMASjy4cI OPIddWCpeSHtzS13QEpCA8x3NjQIFAjKNIrOdS+6HDWVw4yTpWK2WgpmEAjU3HDJ uCGmSYGRA2YUSMQd25LtJ87QhOX4PzIcJSoSKW0HG2Rx82a0MP8VXNfW0c+GIF7U 7BK2OGf5L/bAy2gXt0ifS5GfYf3nTXCwyambSHbnp5tzje6QaBmnNDUG+8GuD6Rh 97d8tw== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46u6g907nv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:06 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-7394792f83cso2875304b3a.3 for ; Tue, 27 May 2025 14:05:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379905; x=1748984705; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+R55bDvd2i6fMCr67D+fFGu07eFzF+YQ+BvBZJYOtis=; b=INXwBEeoxIVE4uaVByV46rsWQj0NWSYUA91fAmCQXgUsnhxGQrc3wt5GEldmdx5Zyr +RtFTuPFs8W8wcIH3d/lRAZ/YsDe00Ieyb0XJzvLZpIkkeBOwC0Gfapdd3dPIuJHTMDq efjdhyahAcZLExXLpVUUCQjVRy3BSIHLkO/eE6u61Royz4MtuYIsXUk83ZD767+iuV0E lALWM/HZ7PY3LrTzC1Bd9gHNsTSScN4UqDxlXE6iEWUNdyk6xXKioV6S7wJeo8/PsmOb ebixgLB5XfiqD6e1ZVQ2vjDIC9OD+rtz8ySSFnBsWG4aPzl17lLkhJ4Uubln6j32H5PM Zxvw== X-Forwarded-Encrypted: i=1; AJvYcCWOiMq8gnHgg4UftwzpWk/VucGyA+NU7nqRICDa/ppY/aff8sMIzyDRw9kP54nd6Nf6EImGGP/cVLsQ0S4=@vger.kernel.org X-Gm-Message-State: AOJu0Yz8JXtpWVqU2fiqj3/Zv8EaHAB3JB0DtgkKbWgibpz/gx6glaDo pk8Q1tOVueLBNhmbokFdlRPMBNKk8o6M4/wyZHAU4q2erbgdbKu9WD37BXmSriGtL342yo8Q+OC 8DWNs56ZJMUjRT9OowzuRrCerfmtPJOKkLrqPKlJeVD2BjNmKPnqxo3DWykKfz/3RYgk= X-Gm-Gg: ASbGncvPupRVtwDRwwH8ZXO+BRySo7wAS4ZWljSr6zVk9Y2MbRobBbABoh7ZVpyMqxd 0uD9hNmjjSetA1SPKsaA/maRgQBEDGiJIm/5DJXHBLtzaXF28OyWel1d/baKjVXk/8YlSxDVYAv RRTDUmj1APZ70gacysvTsuw4hmFhchX7XDmPYC8VVEUozQnp3w+3LmGYUda10uc9VBwYUTIF5tv wrHfaAre6EfvueTSYE/wS0apVyP8RcUz2QHuqAbNrTkjkrIGeAxX0nA4SZmk85cJl5l9rojaM7J TAmXrHkBy49JQNxeeWopZWT9+9BjPgjroUn2E3K/uO2quRabx92cPuDCCmAlmStuT3s= X-Received: by 2002:a05:6a00:2d1b:b0:740:4095:4d07 with SMTP id d2e1a72fcca58-745fdf4aabcmr23423657b3a.12.1748379904934; Tue, 27 May 2025 14:05:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGF3F/0WuD1I/uFyifDLb+DPIbx6i8n8BnLXMFGs56DuGIiLm5xJPWIJar210TA0fKEm+zAug== X-Received: by 2002:a05:6a00:2d1b:b0:740:4095:4d07 with SMTP id d2e1a72fcca58-745fdf4aabcmr23423588b3a.12.1748379904421; Tue, 27 May 2025 14:05:04 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:03 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:43 -0700 Subject: [PATCH v6 07/10] arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-7-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio , Dmitry Baryshkov , Krzysztof Kozlowski , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=5686; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=+Rqpl60bvMJUwvbS+tvLZ+jZaj0RAwENmyzWKv4OcjE=; b=NQyoaBHmECAVGHIGRBOL8RKALjCiTvQacv/P61bnVDWHA0mO1TPh+XBlwznl8HgyNawFpp4lI ShPBlLR7OBsAggDbkxU57YRcprYao+1cAkvAwPmMuVq8iVsEfeefgHa X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Authority-Analysis: v=2.4 cv=d4b1yQjE c=1 sm=1 tr=0 ts=68362902 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=n1SQX4eW7R_9Zp26JX0A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: MyDXF3CHsGc2WwqN1Kiop8Hdby4ImmlI X-Proofpoint-GUID: MyDXF3CHsGc2WwqN1Kiop8Hdby4ImmlI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX+x0uSq6fO77L L2VjzWwxP1od+E+zeRuAURSot81FNuLWW5y59OIxNpaf5ULOjj640pNpiiDVaAwG8uBo70eMzmb gthpAJCRcL9hz6YNFmfA1J7msYkln+UkLpw3kMJV5M/o3xKIoS0FEzuhom1fmIRZ1ENR+lL46Ki Os38YYxPjn3IN4cBk5f4hVm+jWUn/66P3HZRjjP5qbbBe3JcK7dtqNPR++e4F/eraMYxbyjlW88 eQaNbmMyqnkpSwv0GP73uMHSOk3LjBMsZyKckfXgqI4PtEbHqIR7SxXQaw12FKtfm7kveH9LN1U DrWWocziSGF8k3WXKyi/6LgrFpnua0spyxCS83X7h3g/mJZwEtFOW18jF43QT/g8P12r6R9X+TR gbFOv/pzxM9ooD1HDwuinuTUexd8CKzrygJE+poVC+/GFuLnE0+YYO3n2stL2MKp71Zk97l8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng Add the base USB devicetree definitions for SM8750 platforms. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the transition to using the M31 eUSB2 PHY compared to previous SoCs. Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 164 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 980ba1ca23c487b9225b73872889f02c2611e68e..a1c54ced7fe5b83671ccab3bbf8= 70c9c10c27e05 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -2462,6 +2463,169 @@ data-pins { }; }; =20 + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0x0 0x88e3000 0x0 0x29c>; + + clocks =3D <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible =3D "qcom,sm8750-qmp-usb3-dp-phy"; + reg =3D <0x0 0x088e8000 0x0 0x4000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,sm8750-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a6f8800 0x0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xe000>; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x40 0x0>; + + phys =3D <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05F87218AD1 for ; Tue, 27 May 2025 21:05:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379910; cv=none; b=SFfPGy09NpYndt+gqx1IuyulM0FxLG0hTL4KLg7Ysf0GHGu8hZU+76z/huMpQvsMbCkg1Na9gQo0TBFbn7LYiD354/IwgkLCKu2kzyRbjCiCW32PWkajRFk2If4xGD1OYNkr/pIPjfiwFM2YUtr/RoC+5qiZZsIFXBoG8flI5O0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379910; c=relaxed/simple; bh=SzHbHz5W+oX3YfTw8d3BpgFZXwsUINC/XLP2fP7cIaQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fpfspYeykffruPuKjMwCHHshrpmN0AH3ewwFw73hC4CqnYs3CBZJGTi6vodCbMyN9mlurz6RXXFlvpIjThSgdFdgyxWSNybZuFOdhQsznVSOMQvgj1TTSHpdOgQSv2EdgM561MZ9jLijvif3cK76hMH26HR1oh8I9XLC2DcEJpk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XXLFu+zJ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XXLFu+zJ" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RKFpIB016904 for ; Tue, 27 May 2025 21:05:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= teg98KnCXRHpbibmB3t0iTGw5Sr71vWVJCSu3Gc6TZo=; b=XXLFu+zJIXzaJOnH 6MmY7OJEfvk+vqpjXwDNKNhnTFbtvufAnTxh0w43zpikEqqTLCYhUKVa5MY8XzVA XBJAD1aHs+NBai6fjOp52Bx1RzbDkUatBByTbzuPgJPwfMLFpVgb3Sg+OBnHvkA/ oidME/ep06EwgmBqQCMHpldraWVqtH46MEqXGm/cDll02vDhM9tqtRNubME16HPs eXvwB16TAaTZTGAow/4+PY82BOZt+CAxfoeQ3g4lgi0gGrlOs+YoQG+zookZh7Qs 0rEtKo694lDbsfnxz3eDjrRTZBJxvSeklAkL6fncQHDV5vP9IV+ZEF3QLKGRcvSq kKqKaA== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46vmgcvpxq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:07 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-742a091d290so2604476b3a.3 for ; Tue, 27 May 2025 14:05:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379906; x=1748984706; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=teg98KnCXRHpbibmB3t0iTGw5Sr71vWVJCSu3Gc6TZo=; b=Hl/TF7LyOtZMQNguMFOhLaTRw5M7CQrksZRiNUwDSZSnrFFFcQYubWjC2pUurXViD1 m/6YMYxlVwMJXwuuhU3tkpIY1OO2oC/05J1GgICXzAS4fVR50FmxNHxo72Lt9ghOJmj0 0o8Ugon/Tl0Ls+4DF+RntZKYMowSvVqykvkMItRQJGCDG1vyHNCMLFrfGG2muQOsU4bx 1DZwAQyu5UPbgd3uXq+ArNCKRO1viIP37DD+IdTTAy7+5WBCOvHhKrv9oIWXQPlt63TT kwCByss8AUu8A/ZEj31hZyz6op0LI2DwN8hbsRh/qyvC8LGGxsmjZ39K/ssTTQknuaKO E1ug== X-Forwarded-Encrypted: i=1; AJvYcCV1Au6QMffeN5IWuQWA1cugnKUPNaSsTnlM6XiBudChCWOgDi4P9D/HgI3YXFcc17oQaKHFoErpjo5xQ5A=@vger.kernel.org X-Gm-Message-State: AOJu0YzlynViE3FtVTTaw+KxPYcNphPVGx7frSriU/NXX8OwVocVHXUB ITstS5TqP9WQae4om+J/8or00+6cUq0dGoYomjq/eJwWMKKAccyzGvMKv/ijudV9jz7eLHpar7u TUCJ2L3NV4SmvdiEzmkXgOjeXo9hxXhZMUm+4+ls9AoE7EKtDuJAfsTrfYcMVvlWx78c= X-Gm-Gg: ASbGncvdcjSyACY6C5Rtd4WIO0sabnyG27J7y2tSUajr2uyGP+q9wTjmVCT3DFj/JFs RqZZFKbbJpL4Zqd98HxEPV6PvcLYWH6oJd/66D0Qf+6E263K2LFFXW4iorZPRr4VVaPQ4Y52mDW m2ZnaMuKxhkjPdn5c8DL9T5lasJCcq2Nj702VgFvVl6iYDKGSB3jLMJkdcZRuLAo8eJNwjXUp5g hodMUUehc7sAWdp8s335RWHhfnKXPtmmSbQl5VpVjYxG2wuMTVI2zVnhOhcH2SfDaiPIG5fhuGx h0vi2QBwGZr1NZpYAXx+jcqstZ3zbeH0B5Aq31ZvU6PnWq7uK1Gt/7oww4Bhk1gmAxk= X-Received: by 2002:a05:6300:210d:b0:203:c461:dd36 with SMTP id adf61e73a8af0-2188c20df49mr23718624637.6.1748379906514; Tue, 27 May 2025 14:05:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFurMh4Ktwpp0qvzyqJkXxlrwd4QWROOgS0twx82tbgVIupB84blzpNgeeLHqbI8CEKvbsTDA== X-Received: by 2002:a05:6300:210d:b0:203:c461:dd36 with SMTP id adf61e73a8af0-2188c20df49mr23718567637.6.1748379906065; Tue, 27 May 2025 14:05:06 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:05 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:44 -0700 Subject: [PATCH v6 08/10] arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-8-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio , Krzysztof Kozlowski , Melody Olvera , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=1355; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=Nx4I/ZG5m1Kxa6LCnqamndwPnsXvis3d+v65oICH37M=; b=Hp/G/DtacnwV0EhGyfZOVZRkpEebZE/+1C8caI/kuGc9Mek4iJ/VNGTuOQB6QRMqQZR9IOssZ 3IGYp9vp5sFCd3IY2cf3mgW1K0ADTPQeQ0gcHgh7c9fof70ePb4DYOm X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-ORIG-GUID: cwqKgxFgBzMiRTND4y121d42dldWOh_H X-Proofpoint-GUID: cwqKgxFgBzMiRTND4y121d42dldWOh_H X-Authority-Analysis: v=2.4 cv=Ws4rMcfv c=1 sm=1 tr=0 ts=68362903 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Tsvuh88POXG944tnl6EA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3NyBTYWx0ZWRfXwEOHi5BG5JoN wHWPdhQWzKohpsWcZzpg1AhgCYFwD/TIXvqlOaydpaldxcH6jsL0uiL9mG7lZdCr33+RH6I1q3U fU4x6dtg11a/Rwi6znJLoV4ocvH5SnHNM6TJEGIsdr9JPZn+Q2IkuWaRBUXWLVpAiRq3V6YyIf7 Te9hGPRtsYTOO5URgGGARrQr1yd1leSRvF80LKSzl6tc8wglFw4IzIGrD8aBxMAi/+5MUvcvH1w 9Fv9WZleIVWWlE4VUei22pMxOelVLcMORhGBVBKZ0KHCkykFuwQPbiBLNnqiNoPfKlVy9YYpg4L azHUj3RfWiytC7rLSAnqhtu/OTbctQK0A/nt+IiT9zBuo0T0o3ioEWDK47+bMjQG7cNK4t6/nSf aFa8TKsetKQHFbdRt34LG9ZUsCBziQ0zpP+n9jJbybU6+Pgy5eE4f1mn2+qq1+kbIaevhY/G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 mlxlogscore=823 priorityscore=1501 malwarescore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270177 From: Wesley Cheng Enable USB support on SM8750 MTP variants. The current definition will start the USB controller in peripheral mode by default until dependencies are added, such as USB role detection. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8750-mtp.dts index 72f081a890dfe49bfbee5e91b9e51da53b9d8baf..d28e45111b8d01c2753493a7a4e= e248bbb334aa8 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -814,3 +814,27 @@ &tlmm { &uart7 { status =3D "okay"; }; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l2d_0p88>; + vdda12-supply =3D <&vreg_l3g_1p2>; + + phys =3D <&pmih0108_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3g_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p88>; + + status =3D "okay"; +}; --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09DF7219A97 for ; Tue, 27 May 2025 21:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379912; cv=none; b=M049ej6b2QpmLjclzUyOPyOrHGESNaLTMwT+Kboo7RzrzxLvNYtmV7WlqDzE+Gw/amT8t+LTeM2kHJjy8LNNNKIUdNgEORh+K8X1OuP+aExoKTrVVsbJNQ+0EqTAwHYIkXgTbhNabWc4ooz31TXesZnQNAwwTGnHD9uJolvXXTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379912; c=relaxed/simple; bh=kcDd7XnM4Qs5GMBjJTFaJT0hgtOfG1Vu/9PUtKeuisU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TaISiVwvESpTpeoUmZnW6W/dEU24S4szrirGTfPpbhuesW6bx8HS41fzN5tTBJedCSuT3qEX/FNnWFV5miu4N4AO4Clr3A1xj8zmgb/qZd6ynkhTtCtK61o5yUMKvS2Ih+xKA5zAsv4/rIkRLg/R2mcNnfZXF+b/Q9lnvfKoGwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Hn+Q1/js; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Hn+Q1/js" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RIIa3G030608 for ; Tue, 27 May 2025 21:05:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ma8TsHB+F3p3QSMnqT7X+sjQQo7g7lCsD9xj8Lp3FGk=; b=Hn+Q1/js7qPqCwal QR0R6xiRErIo4DEK+STvZLfnrw+Qgh/ktGhQCxhH4XVsGkqdlpIEyZjdsB2XZTwr RAEvBd9mQ6/EyLGYMig0WJy4a9t5mHar9SKs6i97Maj6yZvtRFeesGOYF5gJ/OiK z0bzGKl9pXTURbmw5WV+xAj8bFE6stwakJ1Y/wHGKFDa36jtEV7LI0evjZ2hVTgO lNd7wjXcBmVYW8/cSgmFC7onsGW/LMVQ7Os/B6ccZlX7w1Rra7zu1RPs1G7VUY68 /MgQX1kUNqniV5Yffbua7o6dsLvxkwRTp3XwGYpYgAnhDeS4bD7w5QUZj8nAYO9n qNnYAA== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46u3fq8e1n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:09 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-742b6705a52so5180331b3a.1 for ; Tue, 27 May 2025 14:05:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379908; x=1748984708; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ma8TsHB+F3p3QSMnqT7X+sjQQo7g7lCsD9xj8Lp3FGk=; b=Km7mm7rp1OAEAkS7u223EsD1Ej3Mdwf+s+dy8sijSDkOSok9ymnaQrPKoMp06ocggG hwQN2rJcL85/fWttjTn7ihNAUzs/W832TdJeXuYm4frQBl44uDdJSt/p8whxl6TDwSZS 1V6A/5dNOoosWa9l8DvMsoLbX3xsJoeYpEMWomznvg5OzNAAHI6THnOeGY7bKwt3Kmz5 ykF0iiak7HCTilR5pwnKKrYGNGv4P8B0zQ0whkCy5ke7Pq0oSNjj5sPrdB8m9f4wEmBQ IPW3rn8YWV+pkLMEJXXuIXpG2Ej0HkVzvi3slY1CgL0KHzPapW+ynPuQ4hMuyA2y5Few yTuw== X-Forwarded-Encrypted: i=1; AJvYcCV3hYgmvzquOiC4codq5BSjKbWyPu21xxMdKd3wVGVEDEOTOjEf3zI0aRLe+r98Yj9bsyMptTiW3AApMeI=@vger.kernel.org X-Gm-Message-State: AOJu0YzOeUa/PoNqZNxBx1fhexlgYWpyMuWaVDUO4Qtvr7sBPzKqAUIc PVaVQNXqvCC81Uw0M/NzI82QwEhvB+K5yXzTxYuIrskGAtWwYj52Ax6QJeWtHmPRaa4ULVV0iru bbHO7ni00JvT7PneojEANrGSVlL/Em7ztPAl9w4P5bplsdbh6wHpnYwarmIOmQKJPPADk80sd5B s= X-Gm-Gg: ASbGncsiOTwruAEg5fkPCt8vvi7T/iMFgKaCCQPAmiENOxYa/d9M7YqyVgRs3iMzCN7 jkHlEjhjnEO3AYarEuf8OYk1+V15vGgOMiZElgqx09kqVayXS7CBdLIY/pLxBXmybDXEJxPDUkc dwFqCpOjENmLBLk4uZcwabbOCyNo36ng6yuqhixF9waRRum48ETotActlI/6mGbJn2sGV+XjeeY mXKGwmQTq6CRvjTG7w9i9uU+rl2L0b3qkUtptetDJMKbkKzqmy3SXja9zz5s0UIKI7SOQug32Gm tY479wcFzH3HbJQjm6tCwLr5yWpSVknu1ee/S9IcDcbd36ekkKdGxewEO2Nyugxj+s0= X-Received: by 2002:a05:6a00:2388:b0:740:91eb:c66 with SMTP id d2e1a72fcca58-745fde95d69mr22807099b3a.3.1748379908152; Tue, 27 May 2025 14:05:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2Bz45OE2w5HFnK31wbhlsPZnbFbrdn+wcobk3wqYztQHQDfpbs/apLivFlaZLBGsaPBctAg== X-Received: by 2002:a05:6a00:2388:b0:740:91eb:c66 with SMTP id d2e1a72fcca58-745fde95d69mr22807051b3a.3.1748379907716; Tue, 27 May 2025 14:05:07 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:07 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:45 -0700 Subject: [PATCH v6 09/10] arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-9-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio , Krzysztof Kozlowski , Melody Olvera , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=1413; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=gc+u2Wnbmer5INhP/AFAJkM8vbhhdjKxQE+MTNg1FPA=; b=4AgkM8l55iNY4RBu1/FwiBbrVzA4iniGJCA7yl35iytkMEU8TFElS/1xm1j9EFI9+yj5eR9fo gy0q4gu7itdDy4GfnuSGHdb+p/19GMumODCz/v+vYfN4+QHWeaYoKun X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-GUID: HD5wcuCTH_EewZNALQ-g86b6tXwLYD_7 X-Proofpoint-ORIG-GUID: HD5wcuCTH_EewZNALQ-g86b6tXwLYD_7 X-Authority-Analysis: v=2.4 cv=X8FSKHTe c=1 sm=1 tr=0 ts=68362905 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=EoOMd-xwxZjzz6zYUw0A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX8aNxg208bVvJ lzOtIT9js287+QZGRoYO9zIvpGLTMe9JqYGry5Tg8nNBXc71xaSia/mS/urq3yR+YD1o0wtT7pm KUfuKGvQSJdv3luGMiev5E02CM5MQjAQ+9RdleYaZd50erFtAwiF26WIWL4xrcNPaySx4eAloih arKbAKrpXixKaijTXe9cNIlRL2tzBy+f/4qid2QQMFE1lc8ZuJAGL6Z0CKiLETAieoJMja5nDkZ gh4vP7poG2Kb74DWMM0wQDgbcx4WCCB96x5KS+6K1HplOwuAeLLHDhDUzr9m+AbSr0nnn4jRxEp eCfmjoMVeIswgqSZtKcI2Z5YpnAsUVMF25XOS1YWJ5h+jsQELaiQEY4OVTvcgzcdgH23GbgMjph OuC+LGcH5Veu34XACprgPM2DsnrRQ9Cp6JbVPWWYmTneOyABV3U1OF2z1zlO/qo/7omxanrj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=787 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 From: Wesley Cheng Enable USB support on SM8750 QRD variant. The current definition will start the USB controller in peripheral mode by default until dependencies are added, such as USB role detection. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Tested-by: Konrad Dybcio Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8750-qrd.dts index 840a6d8f8a24670a01376f8fce511da222159016..5cb18ef1bdbece09a7626b57a85= 2379a62985995 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -811,3 +811,27 @@ &tlmm { &uart7 { status =3D "okay"; }; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l2d_0p88>; + vdda12-supply =3D <&vreg_l3g_1p2>; + + phys =3D <&pmih0108_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3g_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p88>; + + status =3D "okay"; +}; --=20 2.48.1 From nobody Mon Feb 9 09:06:41 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87807219EA5 for ; Tue, 27 May 2025 21:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379913; cv=none; b=BaUQsWI2vXhIdie5noNEypo+dyt3chHS/dqoaJsmvkz1ndTNEd6W2Ww4vRr+WGreSxuJzy2ccXoQXW78t3ztcHM7GqF/xdq2TMAjZt7Z62/inQiAFuuVp0j1pFHZ7VOaxzTsY6E/WUfAWhEK1JQi9Mvfc5fdIyYmjp0vBQse8Vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379913; c=relaxed/simple; bh=wCdzpXsKw8zqQyaRyA8EfWIj8Ra4i9wLlBGWl4/WARQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uIzXboFIZXvU0qqrT0Gd6zyrCMpXfSQ0ge4pXbpPfOGdW0YN6FHDp8QLpbw2DsjPyNT2uRtKtg1h5Kv2QHwX47Y5kLkNISCkDiOYoFq59TC0xfWjAFon9v7zgDDdb0uSPoaxKxnNsq7wY0rRu0cGROu4zVbEhgP5dkEVHtY0HVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eFOUBIeA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eFOUBIeA" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54RG1YQm029195 for ; Tue, 27 May 2025 21:05:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= LPkqIIVJzTbHReDF6liD2MG4ODSDIeHW603+18LbzM4=; b=eFOUBIeAvN/dWFCq xOi2G013rlZ7UNJ9SVpmPsTDwPGAB0oEuAjvAfGdvYksbrdY0symWV4SsdCUOsvr H5m77PaAXjMPVVVdCT9P3/+YHl8oK9cv1yc7qN690fZPZXzsLObszn5SD3YFxVpb nsJ6boRRZavZhS8IKbberwTGTRdwJqN0P9P2MJiWDKgdSIlh4kro4o67+Cydu+Cl YA4eIzQHP/iwFdzCEDtfnZHghqC0g1ri76po2htmvubU5wzX8UV4jdokohDGlsNs M4HGeox6sJpySVWdUqXm3ocOEI96B+VrtD5xDV0fycJ/NciETksjai7aCIAzwQIq v0TNbw== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46w992j8nd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 27 May 2025 21:05:10 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-73bfc657aefso2527870b3a.1 for ; Tue, 27 May 2025 14:05:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379910; x=1748984710; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LPkqIIVJzTbHReDF6liD2MG4ODSDIeHW603+18LbzM4=; b=NE+h7LYLBOFiyHigPHukMbiWw5qIpEegioKnFTMszXcro+VU0XlIgm6viwiLnyP0gR vFwZf9qWyiOzA6whRYLhQOjSxoHwqvwZ/ED+ZX1dKDDUF4sGyw4UlTd3DcQ3m2OErsTo i6YvncJUQngI6lgzitwzZgRyJkN/BpbpD35nbMW580d47mOMaGdfTDD2zcqiJP8Swalv dliNAtKBT5jh4vLXy5djZStgF05Qh8EGxfBOrAqRWt2vkq+/0OyWoF7VOzxgd8an5ehn nJ692zgT6qNOw63I6l86epUrixbWokt0TXUqj2Yd3FgF1Q277WUKBs/yDC6OE046uiSG hI8g== X-Forwarded-Encrypted: i=1; AJvYcCWPeqXSirIKrNcw2PIVPvXe9syVwc1LZTNvOV7jxlQp1O4lsINwiAPPY7DccLI8G2gwlUTnrlPN9cZjWqA=@vger.kernel.org X-Gm-Message-State: AOJu0YynI1OCHulyfPLCDelAaQWsmFZMXcuhs3ECjGDZmjpOGwsvbUlF z7Gxo+JjjtiY3lrN/KKi1xOoH21f6sESPnTH9T0QOrZzUub9PlXjVCJJsFry2i9L4VWq8J34h78 D2JKE0HqBXZD3NRV4GLWsaotn5jIDQ7a77HQVcL+qaG8FL2n8rcj7sPWtEXNOIvYqt8w= X-Gm-Gg: ASbGncvq5RwRI9n0/asrBhxZxpVAKgG69WE3SW8GFPziL5s0l0VJILhpp7D6627vmkQ KhzmGwn7FVG3m7WeIvfGTWgeVAlN8iM2XT/3euVzPaSdO0F2oHxcqM0BFqrmUVSCbYcXjnGAmEu 8yZIFuExBwF+v+taN16X5heYCQzDiFWx+sqZvesy4ZNxT4vwHLDB5T3/JfHMAYqjAxnjJfbmQOR oSVGuaVfaRe6SmP67oopWFIlXL7vTe9NM4ERvErw3pXTOwTBmcX/Sv78nFEGUAjDnyaWnMZvdZg VLpgD/7m9L2xKe2FScGEweUPSGgbjEe0aeQwBp4nqCtOHD0tDHY4ACN04d399ZHZ0ps= X-Received: by 2002:a05:6a00:a96:b0:740:6f69:f52a with SMTP id d2e1a72fcca58-745fdac80demr20724864b3a.0.1748379909730; Tue, 27 May 2025 14:05:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE89XO/JDVl6rd3hud7F4tMJEpNAb1237KFGDPWMLXu7CEJYly3v5ShxkxUVfmWpgn+xSWY/Q== X-Received: by 2002:a05:6a00:a96:b0:740:6f69:f52a with SMTP id d2e1a72fcca58-745fdac80demr20724807b3a.0.1748379909299; Tue, 27 May 2025 14:05:09 -0700 (PDT) Received: from hu-molvera-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7465e64836fsm29167b3a.26.2025.05.27.14.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:05:08 -0700 (PDT) From: Melody Olvera Date: Tue, 27 May 2025 14:04:46 -0700 Subject: [PATCH v6 10/10] arm64: defconfig: Add M31 eUSB2 PHY config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-sm8750_usb_master-v6-10-d58de3b41d34@oss.qualcomm.com> References: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> In-Reply-To: <20250527-sm8750_usb_master-v6-0-d58de3b41d34@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Greg Kroah-Hartman , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748379891; l=926; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=wCdzpXsKw8zqQyaRyA8EfWIj8Ra4i9wLlBGWl4/WARQ=; b=JUlbr6mF6I6cr5T9ZHdAGEijiVb5Mu+5V1BZNQUxXDHvq3yjKg+SamgDa52qed7t8bmWdrkdW 42TjvtABTDkAncpbXnX/wXXb06bSMRhHbxRyyU16AIFkDNCwCzClSUq X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI3MDE3OCBTYWx0ZWRfX5IJE4Lry96F9 T6hoUaP7PL9kQmLp+JTlfRP1nfc3XLTO3JN8/8ADzbRJnNVL+ObsrFVd0OI5VtyPfX2lKVu8fgE esPIt4UXIZH0WITVdKycddK9w4/G/wlS1n7QgO7QjdRrBEx3TfMSNt6CNqpFq9Ejb88s1B3yoNG vAIMvlT0KaF78pPr0P6sP7c2ztlZeKHND5YUZMKke5Wwbi84Eut7N4x12oDSXQKTRoPa29IKAb4 hMHMrlqhvwEKK5Jjmk0h3PpeNQsoaXWQeMK8VYm5zS5wQGtikbXsUyU+1URc2D8N6aiENzbHG9b dLPq8ZIzHZ1hYBfg3wkY/nKgwilfbBvK7AGW5XNIi98LSH2W6whrZp7DTQr9+MlCz7q33kMzBK9 mmjHSJp2nysT/ex7HOx6psA3l8aBaSbhreRHAaOLFBsiUceqGxd7VpQHyr4DM8zZb7+GAq2S X-Authority-Analysis: v=2.4 cv=Fes3xI+6 c=1 sm=1 tr=0 ts=68362906 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=yCBuECYR7Rf6QDnvud8A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: H4RhJEZIttOeWgsvllT2-xM84eG2RO-n X-Proofpoint-ORIG-GUID: H4RhJEZIttOeWgsvllT2-xM84eG2RO-n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_10,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=536 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505270178 The Qualcomm SM8750 SoCs use an eUSB2 PHY driver different from the already existing M31 USB driver because it requires a connection to an eUSB2 repeater. Thus, for USB to probe and work properly on the Qualcomm SM8750 SoCs, enable the additional driver. Signed-off-by: Melody Olvera --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a91b79770639d3eb15beb3ee48ef77..f4de2473b3078543b68b01387ac= 7e3ab6951e4a4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1600,6 +1600,7 @@ CONFIG_PHY_QCOM_QUSB2=3Dm CONFIG_PHY_QCOM_SNPS_EUSB2=3Dm CONFIG_PHY_QCOM_EUSB2_REPEATER=3Dm CONFIG_PHY_QCOM_M31_USB=3Dm +CONFIG_PHY_QCOM_M31_EUSB=3Dm CONFIG_PHY_QCOM_USB_HS=3Dm CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=3Dm CONFIG_PHY_QCOM_USB_HS_28NM=3Dm --=20 2.48.1