From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F252AF10; Tue, 27 May 2025 05:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; cv=none; b=kQVPq5MrNXSoJLj/+MHUowu/BFE1x1ZXPFSBi8cJuvZW21H7pqrFniMxEMePGi+vC9qY6Rh4Ujdw9fxxE8qXX4wOg1AO+lR/872x9DLTqe/jW28iMHqdhPPdlO95Y5JMjyfQvfYogXs1wt906hR4UTzuycUg1CXCFcSQ+DKy8Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; c=relaxed/simple; bh=EOFcyhTV/hOBYlu+9SROGy3FDiHIkp+vuQMdA1Ficts=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KBSmTu0JliHx5yMWgRBt1Il9YWRh83yCL3iLXoowtmcNMNChr8Zv0NzM4i2VgGDOjwDGCvy33xRjSRemC8Jc8Te3BP6s/B5CMmEjWgpiMo9GVOB+xlM8b1T7Hdi9qQ9NESLZlHJk1QxyswdRRULmM9dbngt+Xnzn916ylSYSB4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gPwvftPO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gPwvftPO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 653C5C4CEED; Tue, 27 May 2025 05:23:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748323410; bh=EOFcyhTV/hOBYlu+9SROGy3FDiHIkp+vuQMdA1Ficts=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gPwvftPO6lvCYD+4UwVVe8dox8JDhv79JpoN+BlmhVrGUXySwInK/ZJ2sDDOJcgYj kSZaKvgO4HAZWCJMptTVFkBPebSOAjx5Hl5hb/Ulmr5Cysin4dFXpD52FaF4VRKV+K xPlfvqVCs8kzFOv5vUgceMvjuN7dWkAAFrAoyt5dc3IbC/Fia9ziDQJK/7qZYv2Cew eswUQfXkE+QjY4XR1clL8JmoHgqwISBfPpQL+iPN9PF4ND4Xh10O9KkU2rCCzGsrih 5k248zaI5HXxVFFaEhLi2978FzkpXz5hJoh9HQUuKSwyCX7qf3DVFMtF284A53in80 XDHyAh/K5NHrg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56310C5AD49; Tue, 27 May 2025 05:23:30 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 27 May 2025 13:23:28 +0800 Subject: [PATCH v3 1/6] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7/S7D/S6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-1-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=1098; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=prX14EgQxx+RSrte6iKA/xDeT6QG01a/L3Prb2dIYk4=; b=MCVkadAxc+QJWR8KLI+ziAQqDUO8mWkG838u+iFmr/ATnjWWjKDFcHPXR4qxu9ANnEbYFecVo 6mSMypFlLH4CW+7lda4TvdDv01tO5gtZW0bMLIfy3NgfOvxUtDYvICt X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S7/S7D/S6. Signed-off-by: Xianwei Zhao Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 9 +++++= +++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.y= aml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index c36b6fe377ad..61a4685f9748 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -15,11 +15,18 @@ allOf: properties: compatible: oneOf: - - const: amlogic,pinctrl-a4 + - enum: + - amlogic,pinctrl-a4 + - amlogic,pinctrl-s6 + - amlogic,pinctrl-s7 - items: - enum: - amlogic,pinctrl-a5 - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-s7d + - const: amlogic,pinctrl-s7 =20 "#address-cells": const: 2 --=20 2.37.1 From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6FF01D5170; Tue, 27 May 2025 05:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; cv=none; b=GexRrats3FL2n40ed7dAIQzE5tZar78PR4Aa6orAgJD5lRBlOlsUVg4ukkvGbNzWcxHJfXQrilC8zOk2iKh9wJ+TdUrxxZKi0T63EYE5eLLB4x7XY4oKocYZleantl5nMO0ufDG+woUpIBJvSZrx6irh3ixD7MwjJLZJJRNscHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; c=relaxed/simple; bh=1L6yZi98OMXSwGuVg1fqDNJOAY9tKiGWyTN1OH6EbiI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j9ojHpk0PmJ6cgqWDHCLvJDsadv9nSkUkIqG8yIgLQP+zN5zPAD4Jym5SASLxIKRCyUF4MbCqTY+Z3ixclzwQMeKW3Zm8QVF8LP7AEu3DjbYwRFzKAM9vTxUZQZ2mVPDQgQl+6Ojq3YERU9PLKwLrgeMu/pLyP/P+A+KXwowjKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mbkJdXsD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mbkJdXsD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76803C4CEEF; Tue, 27 May 2025 05:23:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748323410; bh=1L6yZi98OMXSwGuVg1fqDNJOAY9tKiGWyTN1OH6EbiI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mbkJdXsDLBUaGBxZHauuX2jN7tcoNNQqY4H6OsyI6zTjnIR6p8Ing/dHjdqWikFF8 XmUK2A7hGXtzklVEW4S8W4SHRFNoOSfElO7FaM6Oq9/t8oZxEZfxa8ZThCkf4tidUR nG2NtZhorbAriHWLzIFGfRg/8ZvX4OZf2iAMaZZeeIFw/EcuxSKFda0i7pR5sbEZTM h+MCEd+9HSODB2JSrdXmdD1fsTxn3ZhR80V/F7Ud99xj6F5cye6F4TC+/FjNjH1fno TnoGRcfQyTcVvTowlGjG1rHu00abSfvAuZFdKR/qz4J50BliQsqUEZwHKhI9VuRg5k iOa6X1828qAVg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 655A4C54F30; Tue, 27 May 2025 05:23:30 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 27 May 2025 13:23:29 +0800 Subject: [PATCH v3 2/6] pinctrl: meson: a4: remove special data processing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-2-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=1982; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=g72piH28WZYJsuGTLrHAVcqtzDHjy35+PP/ZYnzW+rI=; b=rrK5/km3xKR3SJKuUH/4jDuMIKsv8qSz/aPkYq10bR2tZPJayF7mVdVQyuwBjHtR+yWBtREce LR2LUpEfu5tDH/vEu3hsoIA7N96Ws/T7KUNGgupXnZcd5CKOdSjxjNN X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao According to the data specifications of Amlogic's existing SoCs, the function register offset and the bit offset are the same value among various chips. Therefore, general processing can be carried out without the need for private data modification. Drop special data processing. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 33 +++-----------------------= ---- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/m= eson/pinctrl-amlogic-a4.c index 385cc619df13..11f68224342e 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,15 +50,8 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; =20 -struct aml_reg_bit { - u32 bank_id; - u32 reg_offs[AML_NUM_REG]; - u32 bit_offs[AML_NUM_REG]; -}; - struct aml_pctl_data { unsigned int number; - struct aml_reg_bit rb_offs[]; }; =20 struct aml_pmx_func { @@ -829,31 +822,11 @@ static const struct gpio_chip aml_gpio_template =3D { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { - const struct aml_pctl_data *data =3D info->data; - const struct aml_reg_bit *aml_rb; - bool def_offs =3D true; int i; =20 - if (data) { - for (i =3D 0; i < data->number; i++) { - aml_rb =3D &data->rb_offs[i]; - if (bank->bank_id =3D=3D aml_rb->bank_id) { - def_offs =3D false; - break; - } - } - } - - if (def_offs) { - for (i =3D 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; - bank->pc.bit_offset[i] =3D 0; - } - } else { - for (i =3D 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] =3D aml_rb->reg_offs[i]; - bank->pc.bit_offset[i] =3D aml_rb->bit_offs[i]; - } + for (i =3D 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; + bank->pc.bit_offset[i] =3D 0; } } =20 --=20 2.37.1 From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F8F1D416E; Tue, 27 May 2025 05:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-3-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=5341; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=qwVCVEAnoBSq9I7w3IY19mvHAyrHN1ELUryPfTi/kbc=; b=wbXtugHHTmGqqZwpfNa/C/9aeKyj4bIAOBY4DnAoW0oG+TN4aXTn7R3nqUieW0QUjmfJIT7wb vYnp2NKxsUUDxljc3ltoSPRo+FEyBJPIGunqQaOlgk/7K6TDw0HA5ss X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao In some Amlogic SoCs, to save register space or due to some abnormal arrangements, two sets of pins share one mux register. A group starting from pin0 is the main pin group, which acquires the register address through DTS and has management permissions, but the register bit offset is undetermined. Another GPIO group as a subordinate group. Some pins mux use share register and bit offset from bit0 . But this group do not have register management permissions. This submission implements this situation. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 101 +++++++++++++++++++++++++= +++- 1 file changed, 99 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/m= eson/pinctrl-amlogic-a4.c index 11f68224342e..2541c864086d 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,8 +50,23 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; =20 +/* + * partial bank(subordinate) pins mux config use other bank(main) mux regi= stgers + * m_bank_id: the main bank which pin_id from 0, but register bit not from= bit 0 + * m_bit_offs: bit offset the main bank mux register + * sid: start pin_id of subordinate bank + * eid: end pin_id of subordinate bank + */ +struct multi_mux { + unsigned int m_bank_id; + unsigned int m_bit_offs; + unsigned int sid; + unsigned int eid; +}; + struct aml_pctl_data { unsigned int number; + const struct multi_mux *p_mux; }; =20 struct aml_pmx_func { @@ -71,10 +86,12 @@ struct aml_gpio_bank { struct gpio_chip gpio_chip; struct aml_pio_control pc; u32 bank_id; + u32 mux_bit_offs; unsigned int pin_base; struct regmap *reg_mux; struct regmap *reg_gpio; struct regmap *reg_ds; + const struct multi_mux *p_mux; }; =20 struct aml_pinctrl { @@ -106,13 +123,46 @@ static const char *aml_bank_name[31] =3D { "GPIOCC", "TEST_N", "ANALOG" }; =20 +const struct multi_mux multi_mux_s7[] =3D { + { + .m_bank_id =3D AMLOGIC_GPIO_CC, + .m_bit_offs =3D 24, + .sid =3D (AMLOGIC_GPIO_X << 8) + 16, + .eid =3D (AMLOGIC_GPIO_X << 8) + 19, + }, +}; + +const struct aml_pctl_data s7_priv_data =3D { + .number =3D ARRAY_SIZE(multi_mux_s7), + .p_mux =3D multi_mux_s7, +}; + +const struct multi_mux multi_mux_s6[] =3D { + { + .m_bank_id =3D AMLOGIC_GPIO_CC, + .m_bit_offs =3D 24, + .sid =3D (AMLOGIC_GPIO_X << 8) + 16, + .eid =3D (AMLOGIC_GPIO_X << 8) + 19, + }, { + .m_bank_id =3D AMLOGIC_GPIO_F, + .m_bit_offs =3D 4, + .sid =3D (AMLOGIC_GPIO_D << 8) + 6, + .eid =3D (AMLOGIC_GPIO_D << 8) + 6, + }, +}; + +const struct aml_pctl_data s6_priv_data =3D { + .number =3D ARRAY_SIZE(multi_mux_s6), + .p_mux =3D multi_mux_s6, +}; + static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, unsigned int pin, unsigned int *reg, unsigned int *offset) { unsigned int shift; =20 - shift =3D (pin - range->pin_base) << 2; + shift =3D ((pin - range->pin_base) << 2) + *offset; *reg =3D (shift / 32) * 4; *offset =3D shift % 32; =20 @@ -124,9 +174,36 @@ static int aml_pctl_set_function(struct aml_pinctrl *i= nfo, int pin_id, int func) { struct aml_gpio_bank *bank =3D gpio_chip_to_bank(range->gc); + unsigned int shift; int reg; - int offset; + int i; + unsigned int offset =3D bank->mux_bit_offs; + const struct multi_mux *p_mux; + + /* peculiar mux reg set */ + if (bank->p_mux) { + p_mux =3D bank->p_mux; + if (pin_id >=3D p_mux->sid && pin_id <=3D p_mux->eid) { + bank =3D NULL; + for (i =3D 0; i < info->nbanks; i++) { + if (info->banks[i].bank_id =3D=3D p_mux->m_bank_id) { + bank =3D &info->banks[i]; + break; + } + } + + if (!bank || !bank->reg_mux) + return -EINVAL; + + shift =3D (pin_id - p_mux->sid) << 2; + reg =3D (shift / 32) * 4; + offset =3D shift % 32; + return regmap_update_bits(bank->reg_mux, reg, + 0xf << offset, (func & 0xf) << offset); + } + } =20 + /* normal mux reg set */ if (!bank->reg_mux) return 0; =20 @@ -822,12 +899,30 @@ static const struct gpio_chip aml_gpio_template =3D { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { + const struct aml_pctl_data *data =3D info->data; + const struct multi_mux *p_mux; int i; =20 for (i =3D 0; i < AML_NUM_REG; i++) { bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; bank->pc.bit_offset[i] =3D 0; } + + bank->mux_bit_offs =3D 0; + + if (data) { + for (i =3D 0; i < data->number; i++) { + p_mux =3D &data->p_mux[i]; + if (bank->bank_id =3D=3D p_mux->m_bank_id) { + bank->mux_bit_offs =3D p_mux->m_bit_offs; + break; + } + if (p_mux->sid >> 8 =3D=3D bank->bank_id) { + bank->p_mux =3D p_mux; + break; + } + } + } } =20 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, @@ -994,6 +1089,8 @@ static int aml_pctl_probe(struct platform_device *pdev) =20 static const struct of_device_id aml_pctl_of_match[] =3D { { .compatible =3D "amlogic,pinctrl-a4", }, + { .compatible =3D "amlogic,pinctrl-s7", .data =3D &s7_priv_data, }, + { .compatible =3D "amlogic,pinctrl-s6", .data =3D &s6_priv_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); --=20 2.37.1 From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08CEF1D9694; Tue, 27 May 2025 05:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; cv=none; b=fm4uFyWhza5JwWcZlqFAhpjOVK6Vma2PLKtK4MbVgOgcggc5ylkGv1+cfWTv6RIH3klquYYN8PzUTD0dseTL2CFQ/BQEUEyJEvtaBzXqY+vno3BlI0ZIdvnP5/MjRThmSnC8VD3Mymv+fKoOgJA6+adikl9W96ObUHOHvO7Ojrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; c=relaxed/simple; bh=Hj/dtiodyDNGd1NBE4jDypDZMQYKxKPm40P5Dg7K4HU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 27 May 2025 05:23:30 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 27 May 2025 13:23:31 +0800 Subject: [PATCH v3 4/6] dts: arm64: amlogic: add S7 pinctrl node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-4-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=3129; i=xianwei.zhao@amlogic.com; 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Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s7.dtsi index f0c172681bd1..260918b37b9a 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { cpus { @@ -94,6 +95,86 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s7"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x40 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + test_n: gpio@2c0 { + reg =3D <0 0x2c0 0 0x20>; + reg-names =3D "gpio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg =3D <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; --=20 2.37.1 From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7597C1E32B7; Tue, 27 May 2025 05:23:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-5-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=3401; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=TkCzL2tpFVGFSar0wGinjtXWgNKBSbV+l775+YV5x9c=; b=EWY4VF4AYkuDz79BNUMWvs8VorMEmzWK1voY1ImWT594mZ5+4WrXL0vTyPnCbiVDQzHS6NsLp YcPi61WnNPYDzfYiH6ovpFbSUnu2ixNIVvFcAtS8I5mu8Ykl8GZCWKb X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7D. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 ++++++++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot= /dts/amlogic/amlogic-s7d.dtsi index e1099bc1535d..c4d260d5bb58 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { cpus { @@ -94,6 +95,95 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s7d", + "amlogic,pinctrl-s7"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x40 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpiodv: gpio@280 { + reg =3D <0 0x280 0 0x20>, <0 0x8 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_DV<<8) 7>; + }; + + test_n: gpio@2c0 { + reg =3D <0 0x2c0 0 0x20>; + reg-names =3D "gpio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg =3D <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; --=20 2.37.1 From nobody Tue Dec 16 07:09:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21BEC1F8728; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MC+EMllW" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8C6E1C4CEEA; Tue, 27 May 2025 05:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748323412; bh=Hxa2EX+nSJ0LzGazJMi3CxQ9ZJHR9/MQI2pW4yU8x+c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MC+EMllWmRM04E3Wkn8A2+u265k3pgch+vQgcfuIWWqCuORSFmTKfea3w2kwS2n6q D/XJ+SoKfDy75Rqkk1PNrpuGDmQ7m+2QH05lR2LtNqepqFfnZOj0PxboVbJoww0PEB /jw37UuyDw4wvHVCqYn7WwYJDAv98L3JTZHUW8G1sbbsg1u6/pwi3okx9Z1ktHCy08 LUFHz3rqsClc0+aB579606KEx2t2n5FuEgQxJkxEx5s+BBcB0qzaiG3q3tRuCTm4FF cN4TlRF4D2mqrdsD+AeWotTojcnSpb8qkEGnRFwrEOeiHm9i4ixotbWOTA4z65KzUU khwjK2APWFWWw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82731C54ED1; Tue, 27 May 2025 05:23:32 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 27 May 2025 13:23:33 +0800 Subject: [PATCH v3 6/6] dts: arm64: amlogic: add S6 pinctrl node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-s6-s7-pinctrl-v3-6-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=3615; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=qrXyaWIhl6dY6RYbLmLL01WMo+S+QWiFeDMWvb8QD9A=; b=u3zN/dtoGY4LzAhcNGxLOH583hQ6CcnTOBWKrKQaglkUFetx+P5jMcrz+kEMsJijtZ8YiWYa7 KbK8TeGFliECxl5Q/oU5jSBVPxc/NbyslAf8+m6Ds/1HcbLG5bNwE4d X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S6. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 +++++++++++++++++++++++++= ++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s6.dtsi index a8c90245c42a..5f602f1170c0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { #address-cells =3D <2>; @@ -92,6 +93,102 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s6"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 9>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x8 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 7>; + }; + + gpiof: gpio@1a0 { + reg =3D <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_F<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 3>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioa: gpio@280 { + reg =3D <0 0x280 0 0x20>, <0 0x40 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 16>; + }; + + test_n: gpio@2c0 { + reg =3D <0 0x2c0 0 0x20>; + reg-names =3D "gpio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg =3D <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; --=20 2.37.1