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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Julien Panis , Nicolas Pitre , Colin Ian King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Chen-Yu Tsai , , , , , Frank Wunderlich , Daniel Golle , Steven Liu , Sam Shih CC: Mason Chang Subject: [PATCH 1/3] thermal/drivers/mediatek/lvts_thermal: change lvts commands array to static const Date: Mon, 26 May 2025 18:26:57 +0800 Message-ID: <20250526102659.30225-2-mason-cw.chang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com> References: <20250526102659.30225-1-mason-cw.chang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Change the LVTS commands array to static const in preparation for adding different commands. Signed-off-by: Mason Chang --- drivers/thermal/mediatek/lvts_thermal.c | 29 +++++++++++++------------ 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 985925147..7e4f56831 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -96,6 +96,17 @@ =20 #define LVTS_MINIMUM_THRESHOLD 20000 =20 +static const u32 default_conn_cmds[] =3D { 0xC103FFFF, 0xC502FF55 }; +/* + * Write device mask: 0xC1030000 + */ +static const u32 default_init_cmds[] =3D { + 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, + 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, + 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, + 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 +}; + static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 @@ -902,7 +913,7 @@ static void lvts_ctrl_monitor_enable(struct device *dev= , struct lvts_ctrl *lvts_ * each write in the configuration register must be separated by a * delay of 2 us. */ -static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int = nr_cmds) +static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds= , int nr_cmds) { int i; =20 @@ -985,9 +996,9 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_= ctrl, int enable) =20 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ct= rl) { - u32 id, cmds[] =3D { 0xC103FFFF, 0xC502FF55 }; + u32 id; =20 - lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); + lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_c= mds)); =20 /* * LVTS_ID : Get ID and status of the thermal controller @@ -1006,17 +1017,7 @@ static int lvts_ctrl_connect(struct device *dev, str= uct lvts_ctrl *lvts_ctrl) =20 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts= _ctrl) { - /* - * Write device mask: 0xC1030000 - */ - u32 cmds[] =3D { - 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, - 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, - 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, - 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 - }; - - lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 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Mon, 26 May 2025 18:30:02 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 26 May 2025 18:30:02 +0800 From: Mason Chang To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Julien Panis , Nicolas Pitre , Colin Ian King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Chen-Yu Tsai , , , , , Frank Wunderlich , Daniel Golle , Steven Liu , Sam Shih CC: Mason Chang Subject: [PATCH 2/3] thermal/drivers/mediatek/lvts_thermal: add lvts commands and their sizes to driver data Date: Mon, 26 May 2025 18:26:58 +0800 Message-ID: <20250526102659.30225-3-mason-cw.chang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com> References: <20250526102659.30225-1-mason-cw.chang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add LVTS commands and their sizes to driver data in preparation for adding different commands. Signed-off-by: Mason Chang --- drivers/thermal/mediatek/lvts_thermal.c | 65 ++++++++++++++++++++----- 1 file changed, 52 insertions(+), 13 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 7e4f56831..5b7bf29a7 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -96,17 +96,6 @@ =20 #define LVTS_MINIMUM_THRESHOLD 20000 =20 -static const u32 default_conn_cmds[] =3D { 0xC103FFFF, 0xC502FF55 }; -/* - * Write device mask: 0xC1030000 - */ -static const u32 default_init_cmds[] =3D { - 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, - 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, - 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, - 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 -}; - static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int golden_temp_offset; =20 @@ -136,7 +125,11 @@ struct lvts_ctrl_data { =20 struct lvts_data { const struct lvts_ctrl_data *lvts_ctrl; + const u32 *conn_cmd; + const u32 *init_cmd; int num_lvts_ctrl; + int num_conn_cmd; + int num_init_cmd; int temp_factor; int temp_offset; int gt_calib_bit_offset; @@ -996,9 +989,10 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts= _ctrl, int enable) =20 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ct= rl) { + const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; u32 id; =20 - lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_c= mds)); + lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd= ); =20 /* * LVTS_ID : Get ID and status of the thermal controller @@ -1017,7 +1011,9 @@ static int lvts_ctrl_connect(struct device *dev, stru= ct lvts_ctrl *lvts_ctrl) =20 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts= _ctrl) { - lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_c= mds)); + const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; + + lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd= ); =20 return 0; } @@ -1446,6 +1442,17 @@ static int lvts_resume(struct device *dev) return 0; } =20 +static const u32 default_conn_cmds[] =3D { 0xC103FFFF, 0xC502FF55 }; +/* + * Write device mask: 0xC1030000 + */ +static const u32 default_init_cmds[] =3D { + 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, + 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, + 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, + 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 +}; + /* * The MT8186 calibration data is stored as packed 3-byte little-endian * values using a weird layout that makes sense only when viewed as a 32-b= it @@ -1740,7 +1747,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { =20 static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, @@ -1748,7 +1759,11 @@ static const struct lvts_data mt7988_lvts_ap_data = =3D { =20 static const struct lvts_data mt8186_lvts_data =3D { .lvts_ctrl =3D mt8186_lvts_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8186_lvts_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, @@ -1757,7 +1772,11 @@ static const struct lvts_data mt8186_lvts_data =3D { =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { .lvts_ctrl =3D mt8188_lvts_mcu_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, @@ -1766,7 +1785,11 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { =20 static const struct lvts_data mt8188_lvts_ap_data =3D { .lvts_ctrl =3D mt8188_lvts_ap_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, @@ -1775,7 +1798,11 @@ static const struct lvts_data mt8188_lvts_ap_data = =3D { =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { .lvts_ctrl =3D mt8192_lvts_mcu_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, @@ -1784,7 +1811,11 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { =20 static const struct lvts_data mt8192_lvts_ap_data =3D { .lvts_ctrl =3D mt8192_lvts_ap_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, @@ -1793,7 +1824,11 @@ static const struct lvts_data mt8192_lvts_ap_data = =3D { =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { .lvts_ctrl =3D mt8195_lvts_mcu_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, @@ -1802,7 +1837,11 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { =20 static const struct lvts_data mt8195_lvts_ap_data =3D { .lvts_ctrl =3D mt8195_lvts_ap_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, --=20 2.45.2 From nobody Fri Dec 19 17:57:01 2025 Received: from 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mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1619150673; Mon, 26 May 2025 18:30:05 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 26 May 2025 18:30:02 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 26 May 2025 18:30:03 +0800 From: Mason Chang To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Julien Panis , Nicolas Pitre , Colin Ian King , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Chen-Yu Tsai" , , , , , Frank Wunderlich , Daniel Golle , Steven Liu , Sam Shih CC: Mason Chang Subject: [PATCH 3/3] thermal/drivers/mediatek/lvts_thermal: add mt7988 lvts commands Date: Mon, 26 May 2025 18:26:59 +0800 Message-ID: <20250526102659.30225-4-mason-cw.chang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250526102659.30225-1-mason-cw.chang@mediatek.com> References: <20250526102659.30225-1-mason-cw.chang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" These commands are necessary to avoid severely abnormal and inaccurate temperature readings that are caused by using the default commands. Signed-off-by: Mason Chang --- drivers/thermal/mediatek/lvts_thermal.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 5b7bf29a7..4d49482f0 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1443,6 +1443,8 @@ static int lvts_resume(struct device *dev) } =20 static const u32 default_conn_cmds[] =3D { 0xC103FFFF, 0xC502FF55 }; +static const u32 mt7988_conn_cmds[] =3D { 0xC103FFFF, 0xC502FC55 }; + /* * Write device mask: 0xC1030000 */ @@ -1453,6 +1455,12 @@ static const u32 default_init_cmds[] =3D { 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 }; =20 +static const u32 mt7988_init_cmds[] =3D { + 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, + 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, + 0xC10306B8 +}; + /* * The MT8186 calibration data is stored as packed 3-byte little-endian * values using a weird layout that makes sense only when viewed as a 32-b= it @@ -1747,11 +1755,11 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_d= ata_ctrl[] =3D { =20 static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, - .conn_cmd =3D default_conn_cmds, - .init_cmd =3D default_init_cmds, + .conn_cmd =3D mt7988_conn_cmds, + .init_cmd =3D mt7988_init_cmds, .num_lvts_ctrl =3D ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), - .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), - .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), + .num_conn_cmd =3D ARRAY_SIZE(mt7988_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(mt7988_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, --=20 2.45.2