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Mon, 26 May 2025 02:28:44 -0700 (PDT) From: Jun Nie Date: Mon, 26 May 2025 17:28:20 +0800 Subject: [PATCH v10 02/12] drm/msm/dpu: decide right side per last bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250526-v6-15-quad-pipe-upstream-v10-2-5fed4f8897c4@linaro.org> References: <20250526-v6-15-quad-pipe-upstream-v10-0-5fed4f8897c4@linaro.org> In-Reply-To: <20250526-v6-15-quad-pipe-upstream-v10-0-5fed4f8897c4@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748251705; l=1985; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=S7+JCdaVrPN/DIMlTCVGutgCbXcGk68o1VHEmTYxOSE=; b=DUdNxB0sCyTbGte5jKBqLS0uSxmc5nRMsJ9oKNzhyZSluKBN55Nfb6dKhKiY0NmrXktj394Os mj7wbw2RxNBCsqV0SEhfqN3JC/bKmjSSKSEeYgBXEQ7BNuasTvCvYJr X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, only one pair of mixers is supported, so a non-zero counter value is sufficient to identify the correct mixer within that pair. However, future implementations may involve multiple mixer pairs. With the current implementation, all mixers within the second pair would be incorrectly selected as right mixer. To correctly select the mixer within a pair, test the least significant bit of the counter. If the least significant bit is not set, select the mixer as left one; otherwise, select the mixer as right one for all pairs. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a4b0fe0d9899b32141928f0b6a16503a49b3c27a..90941ff4104f620d1f4f18ec260= 418ee59dc16b2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -369,11 +369,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state; - int lm_idx, lm_horiz_position; + int lm_idx; =20 crtc_state =3D to_dpu_crtc_state(crtc->state); =20 - lm_horiz_position =3D 0; for (lm_idx =3D 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi =3D &crtc_state->lm_bounds[lm_idx]; struct dpu_hw_mixer *hw_lm =3D crtc_state->mixers[lm_idx].hw_lm; @@ -384,7 +383,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_= crtc *crtc) =20 cfg.out_width =3D drm_rect_width(lm_roi); cfg.out_height =3D drm_rect_height(lm_roi); - cfg.right_mixer =3D lm_horiz_position++; + cfg.right_mixer =3D lm_idx & 0x1; cfg.flags =3D 0; hw_lm->ops.setup_mixer_out(hw_lm, &cfg); } --=20 2.34.1