From nobody Fri Dec 19 20:59:45 2025 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21BB7211A3D; Mon, 26 May 2025 14:31:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269891; cv=none; b=t5mYEST5/U5sKa9+qcVjPFkhSgDYaBoYANfYP0ogtcztnI/jAMf6V3wr87JdnaSHnFrbY2/CWzH+tmo+f9W3AdS/Pieq0cwDg2yBBEw1Qms1YZ++OjFRUE7oaBhRv38otigPqYA83lnl8lcHSK7pEYsVydpfjt1BrYUTwZBx97s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269891; c=relaxed/simple; bh=6axFiIRurV8uBHlsjxfe3KUp3NNI09locCbJCSS9qJQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y8WEvabW5y7/Fo7E3gV+67LFjngF3/MDALGaDBNfeVUuvn8vevz4OXaxCjOpJ9d4RgrLFdmvj547iZQWdoyV2vX9wHlqWcxXfldiV1SN0Sw+mdatf6mmS1Jp7CdlLchXTXZQkC5RZCyznMG38NREKS8A4Fq4B3cRO4B7ZqvLYms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 1670631dd; Mon, 26 May 2025 22:31:16 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:30:59 +0800 Subject: [PATCH v4 1/4] dt-bindings: phy: spacemit: add K1 USB2 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250526-b4-k1-usb3-phy-v2-v4-1-eca668fc16a2@whut.edu.cn> References: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> In-Reply-To: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748269870; l=1416; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=6axFiIRurV8uBHlsjxfe3KUp3NNI09locCbJCSS9qJQ=; b=wrLg/LNm7lSg/17Lhxi4LLOJhwCHlK/urcWawQFjdPfhkvf2gM9j154iBL+bPUEY/RtAbwvRy pGc0cUypID2B8PfdWRY9GkF6T4fqAGqqksdtTi7GTw26MiY0q4KoWLw X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDHk9DVhlPTEwfSB4fGUNOH1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJSEJLQ1VKS0tVSkJZBg ++ X-HM-Tid: 0a970d0144ce03a1kunm41fed85011999 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OBA6IRw*FTE8IgwXMCsiFS85 CzUKCQpVSlVKTE9DSU1CQ0NKSE1CVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFJTExNNwY+ Add support for USB2 PHY found on SpacemiT K1 SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ze Huang --- .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b= /Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8a91b730cb8733ddf29f1b94fc3= 1e6ba920dbc1b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC USB 2.0 PHY + +maintainers: + - Ze Huang + +properties: + compatible: + const: spacemit,k1-usb2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb-phy@c09c0000 { + compatible =3D "spacemit,k1-usb2-phy"; + reg =3D <0xc09c0000 0x200>; + clocks =3D <&syscon_apmu 15>; + #phy-cells =3D <0>; + }; --=20 2.49.0 From nobody Fri Dec 19 20:59:45 2025 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 435F4212B2B; Mon, 26 May 2025 14:31:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269891; cv=none; b=BMij5FoYq2vLUSjFQIt4JSjq4SlYkpUg7AyHsZRNCC3XfSO+pXpgPl6rM9ttIxu6/Og8JTn5kLAKUsCE36CEiOFdrPgmshbt4gpqSd21S8xaptNFS/siP82PKQUw6bgSucav9kCEpHyMrgPiqjtbiJAi3aCpyvEBJNtQ9lAzyEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269891; c=relaxed/simple; bh=7wRZijPTWkMIjtlbhD5lqHbIBKaLm3eG7ixPg9G+vh4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SsdSxXgFzNZuOYxrUjSbfVB2FSk+79HweD71O4PoPMjxUK8KeFzJoe3RmP+Z5f0xULgtSNVyBlin4qHDB5nCl+JbJW7MdUGshYRNFsmXbcVSDuOCX2cyJ0JKpvkMlefMIjNxu4yu5iDNbXpFX0j7ygBZApdvmvyrSffvFchg274= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 1670631e3; Mon, 26 May 2025 22:31:21 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:31:00 +0800 Subject: [PATCH v4 2/4] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250526-b4-k1-usb3-phy-v2-v4-2-eca668fc16a2@whut.edu.cn> References: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> In-Reply-To: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang , Junzhong Pan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748269870; l=2717; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=7wRZijPTWkMIjtlbhD5lqHbIBKaLm3eG7ixPg9G+vh4=; b=Zn5CP2nXRZDHZQO7ADSxxOmVSpAEdLXfbXKk7fNk2j9aDm5YbaFxOPG6zZaImbljExR/YgIwi CgDASEUaL4dAdbqnz1J9aHonVwMXny6GcpQJ/S8D2S58STJ7eh+XVal X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGUMZVk5CSx8ZGkgeGUxLTFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJQk1KSlVKS0tVS1kG X-HM-Tid: 0a970d0158bd03a1kunm41fed850119dc X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NRQ6NCo*STE8IgwOCjQ9FR85 Tg0aCxJVSlVKTE9DSU1CQ0NNQ09DVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFPSkhONwY+ Introduce support for SpacemiT K1 PCIe/USB3 combo PHY controller. PCIe portA and USB3 controller share this phy, only one of them can work at any given application scenario. Reviewed-by: Rob Herring (Arm) Co-developed-by: Junzhong Pan Signed-off-by: Junzhong Pan Signed-off-by: Ze Huang --- .../bindings/phy/spacemit,k1-combphy.yaml | 72 ++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml= b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..93f7a3bb06bba380def77f87f6d= b0184af26e9e6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k1-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PCIe/USB3 Combo PHY + +maintainers: + - Ze Huang + +description: + Combo PHY on SpacemiT K1 SoC. PCIe port A and USB3 controller share this + phy, only one of PCIe port A and USB3 port can work at any given applica= tion + scenario. + +properties: + compatible: + const: spacemit,k1-combphy + + reg: + items: + - description: PHY control registers + - description: PCIe/USB3 mode selection register + + reg-names: + items: + - const: ctrl + - const: sel + + resets: + maxItems: 1 + + "#phy-cells": + const: 1 + description: + Indicates the PHY mode to select. The value determines whether the P= HY + operates in PCIe or USB3 mode. + + spacemit,lfps-threshold: + description: + Controls the LFPS signal detection threshold, affects polling.LFPS + handshake. Lower the threshold when core voltage rises. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xff + + spacemit,rx-always-on: + description: + Affects RX.detect, enhance compatibility of some DFPs in device mode= but + increase power consumption. + type: boolean + +required: + - compatible + - reg + - reg-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@c0b10000 { + compatible =3D "spacemit,k1-combphy"; + reg =3D <0xc0b10000 0x800>, + <0xd4282910 0x400>; + reg-names =3D "ctrl", "sel"; + resets =3D <&syscon_apmu 19>; + #phy-cells =3D <1>; + }; --=20 2.49.0 From nobody Fri Dec 19 20:59:45 2025 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CB0520F079; Mon, 26 May 2025 14:31:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269898; cv=none; b=a0AWrRqNoltzgNhBRjXFYOPVRjL3qz7VN5fkVl2JDGVdwCes3TTzYFhXm9jZtw3g+dNaPoLxX3FsRyGKfkr2OUmvpiX/04UobHY/xfeFl0vL58LaDY3HI8M6dEzClKf7fZJfNoFeNanCezedF3uRDC2o8UoXxI2dSAyBLxarEQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269898; c=relaxed/simple; bh=JWWRteu3ZYpxOF1+wTeihAdDsNcIxAlZzqVubTTdtOI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LaTYdXOPWuey34NDTAzLrDMJxDAdRnLsxd0Y4QIj6gtC5cyWnX701hZhv8Oa6VcGiNEVl+ECqRDfvct/YKtMkJZ4qpuNpijMZxC3UKYomcNXuQCyV/0ZwZW40ns2ELMrr5e0J+bE73Ios1gRQhyRZ7t35V7aBsQ8XHQktKC0AUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 1670631f0; Mon, 26 May 2025 22:31:27 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:31:01 +0800 Subject: [PATCH v4 3/4] phy: spacemit: support K1 USB2.0 PHY controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250526-b4-k1-usb3-phy-v2-v4-3-eca668fc16a2@whut.edu.cn> References: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> In-Reply-To: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748269870; l=6770; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=JWWRteu3ZYpxOF1+wTeihAdDsNcIxAlZzqVubTTdtOI=; b=OcAYycwt39epUmlih4VioM/KyyXYRYhO+5+sU8t5htn8wTiGxl9Zslrz1ol0vpoBK/Pu8czvW EjkojzUqDeWBk4eFHn1A7ais7S8GcNfnHpfQMtnzss0Ly42kBeU03Qj X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSkgZVkMfShgdH0NDGU5DSFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktISk5MTlVKS0tVSkJLS1 kG X-HM-Tid: 0a970d016f1403a1kunm41fed85011a3d X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6P1E6SDo*NTE9CAwYTzQ4FR8w NR8wCjdVSlVKTE9DSU1CQ0JJTElCVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFDSkhPNwY+ The SpacemiT K1 SoC includes three USB ports: - One USB2.0 OTG port - One USB2.0 host-only port - One USB3.0 port with an integrated USB2.0 DRD interface Each of these ports is connected to a USB2.0 PHY responsible for USB2 transmission. This commit adds support for the SpacemiT K1 USB2.0 PHY, which is compliant with the USB 2.0 specification and supports both 8-bit 60MHz and 16-bit 30MHz parallel interfaces. Signed-off-by: Ze Huang --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/spacemit/Kconfig | 13 ++++ drivers/phy/spacemit/Makefile | 2 + drivers/phy/spacemit/phy-k1-usb2.c | 131 +++++++++++++++++++++++++++++++++= ++++ 5 files changed, 148 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe998ec5fd50054eed2c90d6ecce6bd5dd8..fca589aa7926eb5bce14e99785c= f32cf0395202e 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -114,6 +114,7 @@ source "drivers/phy/renesas/Kconfig" source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" +source "drivers/phy/spacemit/Kconfig" source "drivers/phy/st/Kconfig" source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442acc752820fe0bd638dfe38986a37c2a78..05993ff8a15daf7e2583b5f9b9b= 37ac584a30609 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -34,6 +34,7 @@ obj-y +=3D allwinner/ \ rockchip/ \ samsung/ \ socionext/ \ + spacemit/ \ st/ \ starfive/ \ sunplus/ \ diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..0136aee2e8a2f5f484da136b26f= 80130794b992c --- /dev/null +++ b/drivers/phy/spacemit/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for SpacemiT platforms +# +config PHY_SPACEMIT_K1_USB2 + tristate "SpacemiT K1 USB 2.0 PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF + depends on COMMON_CLK + depends on USB_COMMON + select GENERIC_PHY + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci drive= r. diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..fec0b425a948541b39b814caef0= b05e1e002d92f --- /dev/null +++ b/drivers/phy/spacemit/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) +=3D phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-= k1-usb2.c new file mode 100644 index 0000000000000000000000000000000000000000..3485064a77baac8bb857aff3da4= 5838c0da28f03 --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-usb2.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SpacemiT K1 USB 2.0 PHY driver + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include + +#define USB2_PHY_REG01 0x04 +#define USB2_PHY_REG01_VAL 0x60ef +#define USB2_PHY_REG01_PLL_IS_READY BIT(0) +#define USB2_PHY_REG04 0x10 +#define USB2_PHY_REG04_AUTO_CLEAR_DIS BIT(2) +#define USB2_PHY_REG0D 0x34 +#define USB2_PHY_REG0D_VAL 0x1c +#define USB2_PHY_REG26 0x98 +#define USB2_PHY_REG26_VAL 0xbec4 + +#define USB2D_CTRL_RESET_TIME_MS 50 + +struct spacemit_usb2phy { + struct phy *phy; + struct clk *clk; + void __iomem *base; +}; + +static int spacemit_usb2phy_init(struct phy *phy) +{ + struct spacemit_usb2phy *sphy =3D phy_get_drvdata(phy); + void __iomem *base =3D sphy->base; + u32 val; + int ret; + + ret =3D clk_prepare_enable(sphy->clk); + if (ret) { + dev_err(&phy->dev, "failed to enable clock\n"); + return ret; + } + + /* + * make sure the usb controller is not under reset process before + * any configuration + */ + usleep_range(150, 200); + writel(USB2_PHY_REG26_VAL, base + USB2_PHY_REG26); /* 24M ref clk */ + + ret =3D read_poll_timeout(readl, val, (val & USB2_PHY_REG01_PLL_IS_READY), + 500, USB2D_CTRL_RESET_TIME_MS * 1000, true, + base + USB2_PHY_REG01); + if (ret) { + dev_err(&phy->dev, "wait PHY_REG01[PLLREADY] timeout\n"); + return ret; + } + + /* release usb2 phy internal reset and enable clock gating */ + writel(USB2_PHY_REG01_VAL, base + USB2_PHY_REG01); + writel(USB2_PHY_REG0D_VAL, base + USB2_PHY_REG0D); + + /* auto clear host disc */ + val =3D readl(base + USB2_PHY_REG04); + val |=3D USB2_PHY_REG04_AUTO_CLEAR_DIS; + writel(val, base + USB2_PHY_REG04); + + return 0; +} + +static int spacemit_usb2phy_exit(struct phy *phy) +{ + struct spacemit_usb2phy *sphy =3D phy_get_drvdata(phy); + + clk_disable_unprepare(sphy->clk); + + return 0; +} + +static const struct phy_ops spacemit_usb2phy_ops =3D { + .init =3D spacemit_usb2phy_init, + .exit =3D spacemit_usb2phy_exit, + .owner =3D THIS_MODULE, +}; + +static int spacemit_usb2phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct spacemit_usb2phy *sphy; + + sphy =3D devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + + sphy->clk =3D devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); + + sphy->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sphy->base)) + return PTR_ERR(sphy->base); + + sphy->phy =3D devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + + phy_set_drvdata(sphy->phy, sphy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_usb2phy_dt_match[] =3D { + { .compatible =3D "spacemit,k1-usb2-phy", }, + { /* sentinal */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); + +static struct platform_driver spacemit_usb2_phy_driver =3D { + .probe =3D spacemit_usb2phy_probe, + .driver =3D { + .name =3D "spacemit-usb2-phy", + .of_match_table =3D spacemit_usb2phy_dt_match, + }, +}; +module_platform_driver(spacemit_usb2_phy_driver); + +MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0 From nobody Fri Dec 19 20:59:45 2025 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B25C215046; Mon, 26 May 2025 14:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269903; cv=none; b=cXNO84mKobaGFVyefpm0rAxMIFeuDIBRnvxEOruG0xArEwiOpsHe0rSut6E1xp3usUODrd/TBIyDX6MEgfR5hEhPuxKZiwG/AIgZVHKoCY9qqTHDPb2cNgP5mYM4yN0St0j2qtXm1H8IK7uytytUQmpxIWyqWqO2RsCGnBhzefo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748269903; c=relaxed/simple; bh=hO/A14lMsLJDpddYEzwZdSOtnCM4oAVIXnEqaKE4fpU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VdVTdXGeMH+q6z147VlRS6MdjZMIuhAHLrFp1+KtUtSfoW4rTpHz/wyVOlFu8XFNcVBJy2Wg5EA4DiBj4GNhyPC7SVgfq/uL81wIB9JN5IuMk1KdId1XYti5c+k/dGINkD+gQ9oGIe8QUz0ILrRn+HuiGwgHMfis/NLCNcK1eWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.99.37]) by smtp.qiye.163.com (Hmail) with ESMTP id 1670631ff; Mon, 26 May 2025 22:31:32 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 26 May 2025 22:31:02 +0800 Subject: [PATCH v4 4/4] phy: spacemit: add USB3 support for K1 PCIe/USB3 combo PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250526-b4-k1-usb3-phy-v2-v4-4-eca668fc16a2@whut.edu.cn> References: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> In-Reply-To: <20250526-b4-k1-usb3-phy-v2-v4-0-eca668fc16a2@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748269870; l=9624; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=hO/A14lMsLJDpddYEzwZdSOtnCM4oAVIXnEqaKE4fpU=; b=b8rkMeg97iPlL1x51tCGSbOIisf8RItTi9NizDkkvE9XlLRQX71NH7fq0bOkUC5Ehdh+UcIUC I8j3CGTAAJtCYP0wH/odZsoB27UWmr2485k9B9gadcszR6zzx6lyUtG X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCT00eVkxDQ0tOGk8eSkgdTVYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVITFlXWRYaDxIVHRRZQVlPS0hVSktJQk1KSlVKS0tVS1kG X-HM-Tid: 0a970d01856303a1kunm41fed85011aa0 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MxA6HTo6EzE*KgwrTzYVFSNP KTAKCixVSlVKTE9DSU1CQ0JDS0JLVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVITFlXWQgBWUFKSktLSjcG Add support for USB 3.0 mode on the K1 PCIe/USB3 combo PHY which implements PIPE3(125MHz) interface for USB3.0. Currently, only USB mode is supported; PCIe support is not included in this change. Signed-off-by: Ze Huang Reviewed-by: Neil Armstrong --- drivers/phy/spacemit/Kconfig | 8 + drivers/phy/spacemit/Makefile | 1 + drivers/phy/spacemit/phy-k1-combphy.c | 266 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 275 insertions(+) diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig index 0136aee2e8a2f5f484da136b26f80130794b992c..ccc6bf9ea49f4988a27f79a4dcd= 024b18cbd78b0 100644 --- a/drivers/phy/spacemit/Kconfig +++ b/drivers/phy/spacemit/Kconfig @@ -11,3 +11,11 @@ config PHY_SPACEMIT_K1_USB2 help Enable this to support K1 USB 2.0 PHY driver. This driver takes care of enabling and clock setup and will be used by K1 udc/ehci/otg/xhci drive= r. + +config PHY_SPACEMIT_K1_COMBPHY + tristate "SpacemiT K1 PCIe/USB3 combo PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF + depends on COMMON_CLK + select GENERIC_PHY + help + USB3/PCIe Combo PHY Support for SpacemiT K1 SoC diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile index fec0b425a948541b39b814caef0b05e1e002d92f..1fd0c65f2c5cd10ea2f70e43e62= c70588d1ffae9 100644 --- a/drivers/phy/spacemit/Makefile +++ b/drivers/phy/spacemit/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_COMBPHY) +=3D phy-k1-combphy.o obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) +=3D phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-combphy.c b/drivers/phy/spacemit/p= hy-k1-combphy.c new file mode 100644 index 0000000000000000000000000000000000000000..227b1c743f4d981b3d4555c871e= f397c1c8df0b5 --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-combphy.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SpacemiT K1 PCIE/USB3 PHY driver + * + * This driver supports the combo PHY found on Spacemit K1 SoC, which inte= grates + * a dual-mode USB3/PCIe PHY shared between the USB3.0 DRD controller and = PCIe + * PortA. But only one mode can work at any given application scenario. + * + * PCIe mode is not supported yet and any attempt to use the PHY in PCIe m= ode + * will result in an error. + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define COMBPHY_USB_REG1 0x68 +#define COMBPHY_USB_REG1_VAL 0x00 +#define COMBPHY_USB_REG2 0x48 +#define COMBPHY_USB_REG2_VAL 0x603a2276 +#define COMBPHY_USB_REG3 0x08 +#define COMBPHY_USB_REG3_VAL 0x97c +#define COMBPHY_USB_REG4 0x18 +#define COMBPHY_USB_REG4_VAL 0x00 +#define COMBPHY_USB_TERM_SHORT_MASK 0x3000 +#define COMBPHY_USB_TERM_SHORT_VAL 0x3000 +#define COMBPHY_USB_PLL_REG 0x08 +#define COMBPHY_USB_PLL_MASK 0x01 +#define COMBPHY_USB_PLL_VAL 0x01 +#define COMBPHY_USB_LFPS_REG 0x58 +#define COMBPHY_USB_LFPS_MASK 0x700 +#define COMBPHY_USB_LFPS_THRES_DEFAULT 0x03 + +#define COMBPHY_MODE_SEL_MASK BIT(3) +#define COMBPHY_MODE_USB BIT(3) +#define COMBPHY_WAIT_TIMEOUT 1000 + +struct spacemit_combphy_priv { + struct device *dev; + struct phy *phy; + struct reset_control *phy_rst; + struct regmap *regmap_ctrl; + struct regmap *regmap_sel; + bool rx_always_on; + u8 lfps_threshold; + u8 type; +}; + +static const struct regmap_config phy_ctrl_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x800, +}; + +static const struct regmap_config phy_sel_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x400, +}; + +static int spacemit_combphy_set_mode(struct spacemit_combphy_priv *priv) +{ + struct regmap *map =3D priv->regmap_sel; + int ret =3D 0; + + switch (priv->type) { + case PHY_TYPE_USB3: + regmap_update_bits(map, 0, COMBPHY_MODE_SEL_MASK, COMBPHY_MODE_USB); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret =3D -EINVAL; + break; + } + + return ret; +} + +static int spacemit_combphy_init_usb(struct spacemit_combphy_priv *priv) +{ + struct regmap *map =3D priv->regmap_ctrl; + u32 reg_val; + int ret; + + regmap_write(map, COMBPHY_USB_REG1, COMBPHY_USB_REG1_VAL); + regmap_write(map, COMBPHY_USB_REG2, COMBPHY_USB_REG2_VAL); + regmap_write(map, COMBPHY_USB_REG3, COMBPHY_USB_REG3_VAL); + regmap_write(map, COMBPHY_USB_REG4, COMBPHY_USB_REG4_VAL); + + ret =3D regmap_read_poll_timeout(map, COMBPHY_USB_PLL_REG, reg_val, + (reg_val & COMBPHY_USB_PLL_MASK) =3D=3D COMBPHY_USB_PLL_VAL, + 1000, COMBPHY_WAIT_TIMEOUT * 1000); + if (ret) { + dev_err(priv->dev, "USB3 PHY init timeout!\n"); + return ret; + } + + dev_dbg(priv->dev, "USB3 PHY init lfps threshold %d\n", priv->lfps_thresh= old); + regmap_update_bits(map, COMBPHY_USB_LFPS_REG, + COMBPHY_USB_LFPS_MASK, + priv->lfps_threshold << 8); + + if (priv->rx_always_on) + regmap_update_bits(map, COMBPHY_USB_REG4, + COMBPHY_USB_TERM_SHORT_MASK, + COMBPHY_USB_TERM_SHORT_VAL); + + return ret; +} + +static int spacemit_combphy_init(struct phy *phy) +{ + struct spacemit_combphy_priv *priv =3D phy_get_drvdata(phy); + int ret; + + ret =3D spacemit_combphy_set_mode(priv); + if (ret) { + dev_err(priv->dev, "failed to set mode for PHY type %x\n", + priv->type); + goto out; + } + + ret =3D reset_control_deassert(priv->phy_rst); + if (ret) { + dev_err(priv->dev, "failed to deassert rst\n"); + goto err_rst; + } + + switch (priv->type) { + case PHY_TYPE_USB3: + ret =3D spacemit_combphy_init_usb(priv); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret =3D -EINVAL; + break; + } + + if (ret) + goto err_rst; + + return 0; + +err_rst: + reset_control_assert(priv->phy_rst); +out: + return ret; +} + +static int spacemit_combphy_exit(struct phy *phy) +{ + struct spacemit_combphy_priv *priv =3D phy_get_drvdata(phy); + + reset_control_assert(priv->phy_rst); + + return 0; +} + +static struct phy *spacemit_combphy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct spacemit_combphy_priv *priv =3D dev_get_drvdata(dev); + + if (args->args_count !=3D 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->type !=3D PHY_NONE && priv->type !=3D args->args[0]) + dev_warn(dev, "PHY type %d is selected to override %d\n", + args->args[0], priv->type); + + priv->type =3D args->args[0]; + + if (args->args_count > 1) + dev_dbg(dev, "combo phy idx: %d selected", args->args[1]); + + return priv->phy; +} + +static const struct phy_ops spacemit_combphy_ops =3D { + .init =3D spacemit_combphy_init, + .exit =3D spacemit_combphy_exit, + .owner =3D THIS_MODULE, +}; + +static int spacemit_combphy_probe(struct platform_device *pdev) +{ + struct spacemit_combphy_priv *priv; + void __iomem *ctrl_base, *sel_base; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ctrl_base =3D devm_platform_ioremap_resource_byname(pdev, "ctrl"); + if (IS_ERR(ctrl_base)) + return PTR_ERR(ctrl_base); + + priv->regmap_ctrl =3D devm_regmap_init_mmio(dev, ctrl_base, &phy_ctrl_reg= map_config); + if (IS_ERR(priv->regmap_ctrl)) + return dev_err_probe(dev, PTR_ERR(priv->regmap_ctrl), + "Failed to init regmap for ctrl\n"); + + sel_base =3D devm_platform_ioremap_resource_byname(pdev, "sel"); + if (IS_ERR(sel_base)) + return PTR_ERR(sel_base); + + priv->regmap_sel =3D devm_regmap_init_mmio(dev, sel_base, &phy_sel_regmap= _config); + if (IS_ERR(priv->regmap_sel)) + return dev_err_probe(dev, PTR_ERR(priv->regmap_sel), + "Failed to init regmap for sel\n"); + + priv->lfps_threshold =3D COMBPHY_USB_LFPS_THRES_DEFAULT; + device_property_read_u8(&pdev->dev, "spacemit,lfps-threshold", &priv->lfp= s_threshold); + + priv->rx_always_on =3D device_property_read_bool(&pdev->dev, "spacemit,rx= -always-on"); + priv->type =3D PHY_NONE; + priv->dev =3D dev; + + priv->phy_rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), + "failed to get phy reset\n"); + + priv->phy =3D devm_phy_create(dev, NULL, &spacemit_combphy_ops); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create combphy\n"); + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider =3D devm_of_phy_provider_register(dev, spacemit_combphy_xlat= e); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_combphy_of_match[] =3D { + { .compatible =3D "spacemit,k1-combphy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_combphy_of_match); + +static struct platform_driver spacemit_combphy_driver =3D { + .probe =3D spacemit_combphy_probe, + .driver =3D { + .name =3D "spacemit-k1-combphy", + .of_match_table =3D spacemit_combphy_of_match, + }, +}; +module_platform_driver(spacemit_combphy_driver); + +MODULE_DESCRIPTION("Spacemit PCIE/USB3.0 COMBO PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0