From nobody Sun Feb 8 13:43:01 2026 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2056.outbound.protection.outlook.com [40.107.223.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D3161EFFB8; Sun, 25 May 2025 10:16:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748168197; cv=fail; b=RF6EKNqqrRODp7no7nwlHKRRAQMnMkRzJ47WpT9FBbnR+nSl1dtsWk+Krdga7s2k5bPltWwqBtsrnN/CLzANs/YQ0tPwN+JFUrywnhi8OpBCEPiZA5d4b+j2nv2dYWBYLFOu533+WpOK3xatlz1BiVFYEjv9uKv1paRhAszVE1g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748168197; c=relaxed/simple; bh=nb4vSaQ+L/QZEZBXLnDUog0TAYBMYLdX1LgGg8R/Ryg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oUD/49vgRhUPNZBJr/ZRe/tB68f81+DgMKcVHrZEINEB5Dp1bRUhAQ7XaMh4rM4bLFWNgg7wAhQUE0AfFekov3+PHa6IIwmWeoRJZBVoTQ63+CldrI2KZdF6Bnskn0qUk9FaQId0BbmEfukTW8p68gmIgBFJujfh78PnNE08Fa8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=5nrNw68p; arc=fail smtp.client-ip=40.107.223.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="5nrNw68p" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=USL9azgy80a5ywbUxRrYZnogU1W5BF0q9olMejnPmYsqipB3+Jd/A0KKJxCRhSvCMmtRgzYRJL1jxt1nvH+HrwU7z8UTPYQPfCvjSS7r+ZyaGzAEEpO4FwsWh4Dij7up4B4BmDdHuAAS8RKyr6JKXGPJ5OtoHaqYODq239jsY38URrN9hRHk8o/d229JFgTVdKlEBTDsJlXp4F5Jw/MmzP+ZhLTUzzQXMnVKt+P58YuvzN9Jtk7todrqsHBS0RVatEm8aS2pU64qqJIfwomxeUQ5Oak0m1HTyyMSrUcgK3L9WWxiz/3KmIxZHUAZPYkm45Ap8zwHvy0+pb1u2N3uYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=caB6il4exItnqlVYj9Fp/M/FQOJVmcd8pkpGOmiOTuU=; b=hfGxIfTUEd6cTRU8coiZrHnmsEk8uDudfp6xaxHUFRUzz/HCvPeKxja9as1y6OmKAmlQkXeZRFG1GXzVyP0PVWzZAVGY5yQKLCmIZhARkLEwHu5/dJvbxmPDer6tDNhfEdxE3rocmhN1mef6/lBCJv5VJPTODL6UAP3ayoB9mFcsyMOrzgeDFoBha1kFkTtTwM/9z4NMd8PLv9YlO1LJ+Xd49Pr15Rp/aHjKAKEPi7z6Q4AmKzCPSIA/FYTpjL/Pka09Bcv38opDxpyisIcf+IgoFe1u+BEg4A019GMsc6Q9bhOVTXlKYof8UD3lD3QUnXkfWfKUAuX2fG4vOikhjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=caB6il4exItnqlVYj9Fp/M/FQOJVmcd8pkpGOmiOTuU=; b=5nrNw68pOfyxCtwOyxT6ycFXS7HHG8GDV+IAtzT8BQRcRW4pgwbybfymBw46EaZXz4/qxz+anPB+Uh/ga5iCL9uKicXYhyOKu59rOF2eGHvXcjWPmf+UhvHB+VQWPPMav/e5O1mKUG8unrYRpAEX/NE8ypzX42gbzIWAoIOM6W0= Received: from SJ0PR13CA0029.namprd13.prod.outlook.com (2603:10b6:a03:2c0::34) by IA1PR12MB7494.namprd12.prod.outlook.com (2603:10b6:208:41a::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8769.25; Sun, 25 May 2025 10:16:30 +0000 Received: from SJ5PEPF00000203.namprd05.prod.outlook.com (2603:10b6:a03:2c0:cafe::12) by SJ0PR13CA0029.outlook.office365.com (2603:10b6:a03:2c0::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.16 via Frontend Transport; Sun, 25 May 2025 10:16:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF00000203.mail.protection.outlook.com (10.167.244.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8769.18 via Frontend Transport; Sun, 25 May 2025 10:16:30 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 25 May 2025 05:16:27 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Sun, 25 May 2025 05:16:25 -0500 From: Suraj Gupta To: , , , CC: , , , Subject: [PATCH 1/2] dmaengine: Add support to configure and read IRQ coalescing parameters Date: Sun, 25 May 2025 15:46:16 +0530 Message-ID: <20250525101617.1168991-2-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250525101617.1168991-1-suraj.gupta2@amd.com> References: <20250525101617.1168991-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: suraj.gupta2@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|IA1PR12MB7494:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e47a392-b841-4037-c246-08dd9b753793 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K2ca958qKNteiOFPBJEDRwzp+4/Uf6/YmGWuS/PrWB2OAa5yTrJX8wiLZi6V?= =?us-ascii?Q?2XYxY13V7D9EWX/P7iGv5RsLwfp9clmiYEDiau+Wdq7nuUaVFnPng4RdJdd8?= =?us-ascii?Q?00Cs+e3OjtXP6wSw2fJYEWahsxz7lg5laoIBOwongN8sYoETx0Z98HnXk0su?= =?us-ascii?Q?hta5DMY49PPpg3z6KE45w0r/hRtDiVd6A4JDg979b5zKIUt/skEYxXm8jhi8?= =?us-ascii?Q?gZ7bu8eFxaGmtl1Um7EBAQjTo1P++zXd20id338ZAbtdqt9c2iKEJ6uBcJi9?= =?us-ascii?Q?4aqrLE39GSqwKOExosJXaNx0O50+QtArm0dhsgcJ8IPoHlK2sr3m6iR09NCW?= =?us-ascii?Q?qtG3hfVr69x2Vvlqi8RetwD5ddzlnPxC1OJ3rjuq2inqZ3FHio7pIRhP3jQZ?= =?us-ascii?Q?dk31vnU0CdixLwK+H0B+LEGYjidsH0RQ20YBC4kQsIzw0mgJdl0nLmvnKwRA?= =?us-ascii?Q?oJ819b5Leq00pvKbxaDQXf2DosYIOC73lmIIKKZsKvvD5OpLk21Kn2mkJZQy?= =?us-ascii?Q?4Zi3OGWuyd0stmJxaDApCpkJBIaKTK/+ogAnxD03MIW9heAAMkAthVWvM6hm?= =?us-ascii?Q?tFtoHGDD6Gr7gdA2fNnw8bcUu+u0EKPUhgmkylzxMZ66N2L+s+jLxtDsemIn?= =?us-ascii?Q?6ITGBXPSKRR8bpgbnM4r+FmsLh8SSLWXzOFmV3EG/KEyx6EGG6mqUg45yNli?= =?us-ascii?Q?kezfXylkLpKOdUVky0kEE/lam5GCk8m99CcI+C3gR7u+DVtiwRgD1q7qSlZb?= =?us-ascii?Q?oEWWY6PkJpK+b70AsgVyWccgDHqvPpD2jqwdf71V1kGgNm8RywjQBCXbaj4r?= =?us-ascii?Q?XpmZymtN696VqeOawiE8UkdCgt4FV75u8t7AczH1ylUyWUYTRMIVVmq6gRUC?= =?us-ascii?Q?pdJD3Re5bilzkYTnDTTFgx8vDw6MIDuXGbOa9LZd5bLxOxnn86dq5xIBnpc0?= =?us-ascii?Q?SPBKicFHH9jKi7wkRPErX/6blLBzfx7cODpqJtDt8ZcQHn92hZNcurWesZYM?= =?us-ascii?Q?9XSJMK1L2l69aGORRSpvv3Osvo0jItSFCaXfnZzxf4HxpaRnCUF8pzV7rn5W?= =?us-ascii?Q?KfzRgYQk28q3yDifDU2kS1wrZF3I67qnq+nxrNzsoUnkFVhsGQJpTtHl6713?= =?us-ascii?Q?95ddzNKxi2YiUtmtTmnYNTaYb3ToNz0dzcsRzpfPjGGsJ01wd2qduoV1dzCl?= =?us-ascii?Q?5hR5xzm6L00i4p7BbwTvv9ZRGNzyC6MCVgTtQBrmsSHZBSkg19NFu25GtrVM?= =?us-ascii?Q?UZ4xNd8+9zLzJs0p8MZVA4mCasYqb619iU1z4IV5RiFE1bD6nUGybAz8H3EF?= =?us-ascii?Q?5CwoP7NWRLV6F0ZDmAP+5JaMhFZwomPQrmEEhqplwamD7BbzvY4xtEtAGd0j?= =?us-ascii?Q?vO9OJgFkeOZcBXLaB82P8oOaQg+pK91JuYAJU6TqUtfhoZ+11X3eJvZLH8lz?= =?us-ascii?Q?J5fGu34GGoiecZ/wv+yePec3OJAdr0myIOZUfhRXXAqGREOuB0x64faFL2X0?= =?us-ascii?Q?bRtFr13s+urps2QpLTYmHbgGM4KQ01yHmK/b?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2025 10:16:30.1120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e47a392-b841-4037-c246-08dd9b753793 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7494 Content-Type: text/plain; charset="utf-8" Interrupt coalescing is a mechanism to reduce the number of hardware interrupts triggered ether until a certain amount of work is pending, or a timeout timer triggers. Tuning the interrupt coalesce settings involves adjusting the amount of work and timeout delay. Many DMA controllers support to configure coalesce count and delay. Add support to configure them via dma_slave_config and read using dma_slave_caps. Signed-off-by: Suraj Gupta --- include/linux/dmaengine.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index bb146c5ac3e4..c7c1adb8e571 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -431,6 +431,9 @@ enum dma_slave_buswidth { * @peripheral_config: peripheral configuration for programming peripheral * for dmaengine transfer * @peripheral_size: peripheral configuration buffer size + * @coalesce_cnt: Maximum number of transfers before receiving an interrup= t. + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer + * is completed. * * This struct is passed in as configuration data to a DMA engine * in order to set up a certain channel for DMA transport at runtime. @@ -457,6 +460,8 @@ struct dma_slave_config { bool device_fc; void *peripheral_config; size_t peripheral_size; + u32 coalesce_cnt; + u32 coalesce_usecs; }; =20 /** @@ -507,6 +512,9 @@ enum dma_residue_granularity { * @residue_granularity: granularity of the reported transfer residue * @descriptor_reuse: if a descriptor can be reused by client and * resubmitted multiple times + * @coalesce_cnt: Maximum number of transfers before receiving an interrup= t. + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer + * is completed. */ struct dma_slave_caps { u32 src_addr_widths; @@ -520,6 +528,8 @@ struct dma_slave_caps { bool cmd_terminate; enum dma_residue_granularity residue_granularity; bool descriptor_reuse; + u32 coalesce_cnt; + u32 coalesce_usecs; }; =20 static inline const char *dma_chan_name(struct dma_chan *chan) --=20 2.25.1 From nobody Sun Feb 8 13:43:01 2026 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2084.outbound.protection.outlook.com [40.107.237.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC5C8BA42; Sun, 25 May 2025 10:16:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.84 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748168198; cv=fail; b=TPp/SwZWh5fquNKGaPNkXYOp3m7nNSZeNiACXu+VpCdkDjRUW/6/EQ8d7yh+SvY85drY6oPrQ2qbrJx7UaN4qfrGonIertZhY2wmHsDj6wx4HC7NMXj1hbyJo5ALTsZ5wgRBaAawIFjzMzyHC0V3yYcfVxoDjcH8qUh4NVz99fQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748168198; c=relaxed/simple; bh=ti++qP2SxbCr94b+06dVpNQ9tNLbZ2ONqCbu72CQOmE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FhQrODlm8iT12PoG0WAPT9zYuRRV6N5dZbPPpDj4zseKX5gWsuBkgw3cCHddncwZwW6IGJVRxiZFbaY42VJPK2Rm8gnG6DbuxiWb/MEDI1YwQxaZBESZUBTynIeh4zt4tJNKE0+sO3sRi/80P1gsjEP6EGHqLXYmslUwVPKHBQ4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=Nf7OwBBK; arc=fail smtp.client-ip=40.107.237.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Nf7OwBBK" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VFSxjE0aVdCf5qOf4bYAqqXrkOV/DLEqef6P9uFVguRVm94YthYzXa/pYFVZLS56M7oDZJBdoBnq+U6yfiV+2U8PhdpZPscYpdK+RZzVxgNT+RCBDNm2ZMpLjnadDkRzs3NTncRou5EJ5B2/H5qV6buBBUW0TW6AgzL+jzg/I/qQYovNu9unvpi19oGChDdMffmfpw+sxc1XXJcoReponbo4/v6v6gHPEHmBfYfMvTi4tFdcGGzd/9yfPJoaEXjOTY4fXf75Yrh6VO3gLmAs8GdSWxY3rBXnUMrW9dTjqKeVwGLXkGHUOOzAhlbyj7YkTSCQQYYn2Rfou907fr25mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=izlEIQwUeKrajRtPKUwber5TbtMd+1HlD92TZXy7rh8=; b=FKIy2laTVzrYdnFMWYYDJisWxO9IlsYZiIoGJ5bspS9Hc39lE8dtR1D4jcASOpfAGspdKzJWO6V8WUbLj7NcXhdyQeHRlWooPpAn2Y1DHTMLxt+RyUXSA0fpOqv/QUkd8j75WzMr2CEc42Ym+nG2n3TzDa9sHFNMB4q1L00z3fd05JHBQDeFXWmiv4HQPvCH/6rQpl8xq4JqlEeqhRMqIAYpRFWxj036HyRXv5F2tEwPCLH+DlwgOEn+aY/2zYR253EqQVbSfPVTxucgqC2lVnkfVrvEU8EI96a7yIXT2ElbGNrFTfYsA+FbSQOg8PO860OkJFNFWvcb7rGgC9MaLA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=izlEIQwUeKrajRtPKUwber5TbtMd+1HlD92TZXy7rh8=; b=Nf7OwBBKpznfj4JQdzlCrO+5LZIPuHHPsE3Bip5RlnBaHWywDt4+6uozLC6Z3jO+6WaCtF6XoELcH7QuhtgJisvoS8InH/a0ksaaIP3+R3YwfZftWchIysGbhjONWMuZoNFVswhbB4JCn0BOwMHWZmfNPB6VOm9kW6mzW5TTmN8= Received: from SJ0PR13CA0014.namprd13.prod.outlook.com (2603:10b6:a03:2c0::19) by MW4PR12MB5601.namprd12.prod.outlook.com (2603:10b6:303:168::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8722.30; Sun, 25 May 2025 10:16:31 +0000 Received: from SJ5PEPF00000203.namprd05.prod.outlook.com (2603:10b6:a03:2c0:cafe::84) by SJ0PR13CA0014.outlook.office365.com (2603:10b6:a03:2c0::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.18 via Frontend Transport; Sun, 25 May 2025 10:16:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF00000203.mail.protection.outlook.com (10.167.244.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8769.18 via Frontend Transport; Sun, 25 May 2025 10:16:31 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 25 May 2025 05:16:30 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Sun, 25 May 2025 05:16:28 -0500 From: Suraj Gupta To: , , , CC: , , , Subject: [PATCH 2/2] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA Date: Sun, 25 May 2025 15:46:17 +0530 Message-ID: <20250525101617.1168991-3-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250525101617.1168991-1-suraj.gupta2@amd.com> References: <20250525101617.1168991-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: suraj.gupta2@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|MW4PR12MB5601:EE_ X-MS-Office365-Filtering-Correlation-Id: b3f0fa65-ed8a-42dd-6a83-08dd9b75385f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WA8g2uxEXoi3gYYQt75FOx8xOtgQxPyx1652anJp7dowfZXEvsPKwLFIry2/?= =?us-ascii?Q?ybSaRkuHHg5No6KDbcXmjaWds9OyFd0F98T+YlUxOp4sioBufcHcKCS1s/CR?= =?us-ascii?Q?8jv5T7hdWwGeUf4ZDVCU4yRLKRwSI+AqzpvzwcDZGke/rPVahQeex3lA+NFM?= =?us-ascii?Q?Ol0SdBpVff6p+983Q5vpFAYMa3d190Nvo0X8UZvjnbLPTLkARv0chfZ6zjKL?= =?us-ascii?Q?7QE4zcJBdU4VFTDES3wQJr0ly7PoxwpCcaS6qcZDT5WX+bPZSCMKXO2rpYp0?= =?us-ascii?Q?k/d2hVqiMrEU+vioRvtHjSFSs5qSzpuq10koE20+ToD6VxbpeyTgeWcd6ndp?= =?us-ascii?Q?+ff6woDa36Qmnp1Yzor5oZJnKvOREMbZj/sniWofz6eEFt7ktJ8NWISwN0BN?= =?us-ascii?Q?mVPwJ791j1D5rfj9BreA2/tXEqnWI8U1yvQ0ORTzVlAAQQ3l6SkQ43deI260?= =?us-ascii?Q?d4NSgh3zzQVeXx2bizBlMCPMaLmez29ijXQzcnOsO1Y0ZP4hqcnT/6UkLm6s?= =?us-ascii?Q?4kpei9kZE81XyjGTwiB7BdsYrMYXNbo0DV0YJdTLukIitcumi1N9rMnrODtZ?= =?us-ascii?Q?NCh7p3qsf774nGmJ9ZP40+cQcrnzrPTyP2uEGADVwWtbAVVdBdC/yBJ5Ut/4?= =?us-ascii?Q?K+lkdSmuT6U6aGXYLiVb5OBxCnMg4oC2fu/lx038u3raaS/GDSAVcSSKh8XV?= =?us-ascii?Q?1lNzfjzhuRmqC0I6VNke1LhkMg318gvA0MFiW9P/0oB94bs+HLVEaF/DyCwh?= =?us-ascii?Q?k4/yJgQq6CXekkGgOZQqMDDDrKT1ldbpsdbJcrRhFe1HRDynz55zfU4vYzkF?= =?us-ascii?Q?f1OLTJiw9F7RcfEUw4XxXk7b5pxcYe9AYPrQzQOItAuUOyunFTbaJ7biPlYG?= =?us-ascii?Q?XbGiyoumVRlt5wBCmVYdYksWJypecQPIm8dvkuUHO9yFxMAKrl2/BE7SAqc1?= =?us-ascii?Q?sMAwJinlSDLcnFQ9zCXveyiKY0JmTQS48RwmGmEr0tHiOd97f8X5hJ87LwKY?= =?us-ascii?Q?N7RSRNpKu7Pk5P5cOTACmHzyioWR3kKoohtS4t7CC8yUr8dv20afKQhFYn/H?= =?us-ascii?Q?BNtwnEGu+I1XMG9eeiEJRwlgqcq6BNKccVkcZzLGFsrl00vfBYuwbO2JOY+3?= =?us-ascii?Q?SXgNC3jilF+LnYN1N1lYYyJVM7xnGuAl718UK6ut6Bg8TgyAKVoKXSDG3g7G?= =?us-ascii?Q?uEo5XBtQzLXcZROLGe0llrTeJt4EYMDFpOYSn9PiI2zWDoy42MT5LqKbIkcc?= =?us-ascii?Q?je/lIzZh/YF4XAG+3xWi6iFQKRUB1eqUFvZ4rr5yeXLiOrhda83QZw62av6e?= =?us-ascii?Q?i+A+T9R69MPKNgm5GMsTpmmT2AK8a1+XlY6PcU297MMX1gCIvIGytIK6wdX+?= =?us-ascii?Q?ZcF+/CgezLCiQU7PW3h+ng01egHVZKi6UeE+ysZmcEINz+zFAOwpImwUjDBV?= =?us-ascii?Q?8jQJDL1aXX10SjtfzUD1ic4U7RtQwu9t39/Wlu9oDSaVVBE20jQSBLgMqJ9a?= =?us-ascii?Q?7THluC4SMO3sd+CNjh2PiRyHVOEtf/D4p6xQ?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2025 10:16:31.4478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3f0fa65-ed8a-42dd-6a83-08dd9b75385f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5601 Content-Type: text/plain; charset="utf-8" AXI DMA supports interrupt coalescing. Client can fine-tune coalesce parameters based on transaction load. Add support to configure/ report coalesce parameters. Change delay setting to scale with SG clock rate rather than being a fixed number of clock cycles (Referred from AXI ethernet driver). Signed-off-by: Suraj Gupta --- drivers/dma/xilinx/xilinx_dma.c | 62 ++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index a34d8f0ceed8..b03975b6f00f 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -159,6 +159,9 @@ XILINX_DMA_DMASR_SOF_EARLY_ERR | \ XILINX_DMA_DMASR_DMA_INT_ERR) =20 +/* Constant to convert delay counts to microseconds */ +#define XILINX_DMA_DELAY_SCALE (125ULL * USEC_PER_SEC) + /* Axi VDMA Flush on Fsync bits */ #define XILINX_DMA_FLUSH_S2MM 3 #define XILINX_DMA_FLUSH_MM2S 2 @@ -403,6 +406,7 @@ struct xilinx_dma_tx_descriptor { * @terminating: Check for channel being synchronized by user * @tasklet: Cleanup work after irq * @config: Device configuration info + * @slave_cfg: Device configuration info from Dmaengine * @flush_on_fsync: Flush on Frame sync * @desc_pendingcount: Descriptor pending count * @ext_addr: Indicates 64 bit addressing is supported by dma channel @@ -442,6 +446,7 @@ struct xilinx_dma_chan { bool terminating; struct tasklet_struct tasklet; struct xilinx_vdma_config config; + struct dma_slave_config slave_cfg; bool flush_on_fsync; u32 desc_pendingcount; bool ext_addr; @@ -1540,7 +1545,9 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) { struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; struct xilinx_axidma_tx_segment *tail_segment; - u32 reg; + struct dma_slave_config *slave_cfg =3D &chan->slave_cfg; + u64 clk_rate; + u32 reg, usec, timer; =20 if (chan->err) return; @@ -1560,19 +1567,38 @@ static void xilinx_dma_start_transfer(struct xilinx= _dma_chan *chan) =20 reg =3D dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); =20 - if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) { - reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; + reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; + reg &=3D ~XILINX_DMA_CR_DELAY_MAX; + + /* Use dma_slave_config if it has valid values */ + if (slave_cfg->coalesce_cnt && + slave_cfg->coalesce_cnt <=3D XILINX_DMA_COALESCE_MAX) + reg |=3D slave_cfg->coalesce_cnt << + XILINX_DMA_CR_COALESCE_SHIFT; + else if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); - } + + if (slave_cfg->coalesce_usecs <=3D XILINX_DMA_DMACR_DELAY_MAX) + usec =3D slave_cfg->coalesce_usecs; + else + usec =3D chan->irq_delay; + + /* Scale with SG clock rate rather than being a fixed number of + * clock cycles. + * 1 Timeout Interval =3D 125 * (clock period of SG clock) + */ + clk_rate =3D clk_get_rate(chan->xdev->rx_clk); + timer =3D DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate, + XILINX_DMA_DELAY_SCALE); + timer =3D min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK)); + reg |=3D timer << XILINX_DMA_CR_DELAY_SHIFT; + + dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 if (chan->has_sg) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); - reg &=3D ~XILINX_DMA_CR_DELAY_MAX; - reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 xilinx_dma_start(chan); =20 @@ -1703,9 +1729,28 @@ static void xilinx_dma_issue_pending(struct dma_chan= *dchan) static int xilinx_dma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { + struct xilinx_dma_chan *chan =3D to_xilinx_chan(dchan); + + if (!config->coalesce_cnt || + config->coalesce_cnt > XILINX_DMA_DMACR_FRAME_COUNT_MAX || + config->coalesce_usecs > XILINX_DMA_DMACR_DELAY_MAX) + return -EINVAL; + + chan->slave_cfg.coalesce_cnt =3D config->coalesce_cnt; + chan->slave_cfg.coalesce_usecs =3D config->coalesce_usecs; + return 0; } =20 +static void xilinx_dma_device_caps(struct dma_chan *dchan, + struct dma_slave_caps *caps) +{ + struct xilinx_dma_chan *chan =3D to_xilinx_chan(dchan); + + caps->coalesce_cnt =3D chan->slave_cfg.coalesce_cnt; + caps->coalesce_usecs =3D chan->slave_cfg.coalesce_usecs; +} + /** * xilinx_dma_complete_descriptor - Mark the active descriptor as complete * @chan : xilinx DMA channel @@ -3178,6 +3223,7 @@ static int xilinx_dma_probe(struct platform_device *p= dev) xdev->common.device_tx_status =3D xilinx_dma_tx_status; xdev->common.device_issue_pending =3D xilinx_dma_issue_pending; xdev->common.device_config =3D xilinx_dma_device_config; + xdev->common.device_caps =3D xilinx_dma_device_caps; if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIDMA) { dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); xdev->common.device_prep_slave_sg =3D xilinx_dma_prep_slave_sg; --=20 2.25.1