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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 01/23] riscv: Add new error codes defined by SBI v3.0 Date: Sun, 25 May 2025 14:16:48 +0530 Message-ID: <20250525084710.1665648-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI v3.0 defines new error codes so add these new error codes to the asm/sbi.h for use by newer SBI extensions. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3d250824178b..4dd6aafb8468 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -419,6 +419,11 @@ enum sbi_ext_nacl_feature { #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 #define SBI_ERR_NO_SHMEM -9 +#define SBI_ERR_INVALID_STATE -10 +#define SBI_ERR_BAD_RANGE -11 +#define SBI_ERR_TIMEOUT -12 +#define SBI_ERR_IO -13 +#define SBI_ERR_DENIED_LOCKED -14 =20 extern unsigned long sbi_spec_version; struct sbiret { @@ -503,11 +508,18 @@ static inline int sbi_err_map_linux_errno(int err) case SBI_SUCCESS: return 0; case SBI_ERR_DENIED: + case SBI_ERR_DENIED_LOCKED: return -EPERM; case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_STATE: + case SBI_ERR_BAD_RANGE: return -EINVAL; case SBI_ERR_INVALID_ADDRESS: return -EFAULT; + case SBI_ERR_TIMEOUT: + return -ETIMEDOUT; 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Sun, 25 May 2025 01:47:43 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Date: Sun, 25 May 2025 14:16:49 +0530 Message-ID: <20250525084710.1665648-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Signed-off-by: Anup Patel --- .../mailbox/riscv,rpmi-shmem-mbox.yaml | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-sh= mem-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbo= x.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.ya= ml new file mode 100644 index 000000000000..a5bcf1fba464 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a common sha= red + memory based RPMI transport. This RPMI shared memory transport integrate= s as + mailbox controller in the SBI implementation or supervisor software wher= eas + each RPMI service group is mailbox client in the SBI implementation and + supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,rpmi-shmem-mbox + + reg: + minItems: 2 + items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - description: A2P doorbell address + + reg-names: + minItems: 2 + items: + - const: a2p-req + - const: p2a-ack + - enum: [ p2a-req, a2p-doorbell ] + - const: a2p-ack + - const: a2p-doorbell + + interrupts: + maxItems: 1 + description: + The RPMI shared memory transport supports P2A doorbell as a wired + interrupt and this property specifies the interrupt source. + + msi-parent: + description: + The RPMI shared memory transport supports P2A doorbell as a system M= SI + and this property specifies the target MSI controller. + + riscv,slot-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + description: + Power-of-2 RPMI slot size of the RPMI shared memory transport. + + riscv,a2p-doorbell-value: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1 + description: + Value written to the 32-bit A2P doorbell register. + + riscv,p2a-doorbell-sysmsi-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The RPMI shared memory transport supports P2A doorbell as a system M= SI + and this property specifies system MSI index to be used for configur= ing + the P2A doorbell MSI. + + "#mbox-cells": + const: 1 + description: + The first cell specifies RPMI service group ID. + +required: + - compatible + - reg + - reg-names + - riscv,slot-size + - "#mbox-cells" + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + // Example 1 (RPMI shared memory with only 2 queues): + mailbox@10080000 { + compatible =3D "riscv,rpmi-shmem-mbox"; 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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Date: Sun, 25 May 2025 14:16:50 +0530 Message-ID: <20250525084710.1665648-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RISC-V SBI Message Proxy (MPXY) extension as a mailbox controller. Signed-off-by: Anup Patel --- .../bindings/mailbox/riscv,sbi-mpxy-mbox.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,sbi-mpx= y-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.= yaml b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml new file mode 100644 index 000000000000..ad4c135e0510 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,sbi-mpxy-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI Message Proxy (MPXY) extension based mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V SBI Message Proxy (MPXY) extension [1] allows supervisor + software to send messages through the SBI implementation (M-mode + firmware or HS-mode hypervisor). The underlying message protocol + and message format used by the supervisor software could be some + other standard protocol compatible with the SBI MPXY extension + (such as RISC-V Platform Management Interface (RPMI) [2]). + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Supervisor Binary Interface (SBI) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + + [2] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,sbi-mpxy-mbox + + "#mbox-cells": + const: 2 + description: + The first cell specifies channel_id of the SBI MPXY channel, + the second cell specifies MSG_PROT_ID of the SBI MPXY channel + +required: + - compatible + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + mailbox { + compatible =3D "riscv,sbi-mpxy-mbox"; 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Sun, 25 May 2025 01:47:58 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 04/23] RISC-V: Add defines for the SBI message proxy extension Date: Sun, 25 May 2025 14:16:51 +0530 Message-ID: <20250525084710.1665648-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add defines for the new SBI message proxy extension which is part of the SBI v3.0 specification. Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4dd6aafb8468..d295c26a7c26 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, + SBI_EXT_MPXY =3D 0x4D505859, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -402,6 +403,65 @@ enum sbi_ext_nacl_feature { #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 =20 +enum sbi_ext_mpxy_fid { + SBI_EXT_MPXY_GET_SHMEM_SIZE, + SBI_EXT_MPXY_SET_SHMEM, + SBI_EXT_MPXY_GET_CHANNEL_IDS, + SBI_EXT_MPXY_READ_ATTRS, + SBI_EXT_MPXY_WRITE_ATTRS, + SBI_EXT_MPXY_SEND_MSG_WITH_RESP, + SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP, + SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS, +}; + +enum sbi_mpxy_attribute_id { + /* Standard channel attributes managed by MPXY framework */ + SBI_MPXY_ATTR_MSG_PROT_ID =3D 0x00000000, + SBI_MPXY_ATTR_MSG_PROT_VER =3D 0x00000001, + SBI_MPXY_ATTR_MSG_MAX_LEN =3D 0x00000002, + SBI_MPXY_ATTR_MSG_SEND_TIMEOUT =3D 0x00000003, + SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT =3D 0x00000004, + SBI_MPXY_ATTR_CHANNEL_CAPABILITY =3D 0x00000005, + SBI_MPXY_ATTR_SSE_EVENT_ID =3D 0x00000006, + SBI_MPXY_ATTR_MSI_CONTROL =3D 0x00000007, + SBI_MPXY_ATTR_MSI_ADDR_LO =3D 0x00000008, + SBI_MPXY_ATTR_MSI_ADDR_HI =3D 0x00000009, + SBI_MPXY_ATTR_MSI_DATA =3D 0x0000000A, + SBI_MPXY_ATTR_EVENTS_STATE_CONTROL =3D 0x0000000B, + SBI_MPXY_ATTR_STD_ATTR_MAX_IDX, + /* + * Message protocol specific attributes, managed by + * the message protocol specification. + */ + SBI_MPXY_ATTR_MSGPROTO_ATTR_START =3D 0x80000000, + SBI_MPXY_ATTR_MSGPROTO_ATTR_END =3D 0xffffffff +}; + +/* Possible values of MSG_PROT_ID attribute */ +enum sbi_mpxy_msgproto_id { + SBI_MPXY_MSGPROTO_RPMI_ID =3D 0x0, +}; + +/** RPMI message protocol specific MPXY attributes */ +enum sbi_mpxy_rpmi_attribute_id { + SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID =3D SBI_MPXY_ATTR_MSGPROTO_ATTR_START, + SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION, + SBI_MPXY_RPMI_ATTR_MAX_ID, +}; + +/* Encoding of MSG_PROT_VER attribute */ +#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) (((__ver) >> 16) & 0xffff) +#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver) ((__ver) & 0xffff) +#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min) (((__maj) << 16) | (__min)) + +/* Capabilities available through CHANNEL_CAPABILITY attribute */ +#define SBI_MPXY_CHAN_CAP_MSI BIT(0) +#define SBI_MPXY_CHAN_CAP_SSE BIT(1) +#define SBI_MPXY_CHAN_CAP_EVENTS_STATE BIT(2) +#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP BIT(3) +#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4) +#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5) + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4F371E5B8A for ; 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Sun, 25 May 2025 01:48:06 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:48:06 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 05/23] mailbox: Add common header for RPMI messages sent via mailbox Date: Sun, 25 May 2025 14:16:52 +0530 Message-ID: <20250525084710.1665648-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RPMI based mailbox controller drivers and mailbox clients need to share defines related to RPMI messages over mailbox interface so add a common header for this purpose. Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel --- include/linux/mailbox/riscv-rpmi-message.h | 204 +++++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 include/linux/mailbox/riscv-rpmi-message.h diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h new file mode 100644 index 000000000000..6201d4dd6047 --- /dev/null +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2025 Ventana Micro Systems Inc. */ + +#ifndef _LINUX_RISCV_RPMI_MESSAGE_H_ +#define _LINUX_RISCV_RPMI_MESSAGE_H_ + +#include + +/* RPMI version encode/decode macros */ +#define RPMI_VER_MAJOR(__ver) (((__ver) >> 16) & 0xffff) +#define RPMI_VER_MINOR(__ver) ((__ver) & 0xffff) +#define RPMI_MKVER(__maj, __min) (((__maj) << 16) | (__min)) + +/* RPMI message header */ +struct rpmi_message_header { + __le16 servicegroup_id; + u8 service_id; + u8 flags; + __le16 datalen; + __le16 token; +}; + +/* RPMI message */ +struct rpmi_message { + struct rpmi_message_header header; + u8 data[]; +}; + +/* RPMI notification event */ +struct rpmi_notification_event { + __le16 event_datalen; + u8 event_id; + u8 reserved; + u8 event_data[]; +}; + +/* RPMI error codes */ +enum rpmi_error_codes { + RPMI_SUCCESS =3D 0, + RPMI_ERR_FAILED =3D -1, + RPMI_ERR_NOTSUPP =3D -2, + RPMI_ERR_INVALID_PARAM =3D -3, + RPMI_ERR_DENIED =3D -4, + RPMI_ERR_INVALID_ADDR =3D -5, + RPMI_ERR_ALREADY =3D -6, + RPMI_ERR_EXTENSION =3D -7, + RPMI_ERR_HW_FAULT =3D -8, + RPMI_ERR_BUSY =3D -9, + RPMI_ERR_INVALID_STATE =3D -10, + RPMI_ERR_BAD_RANGE =3D -11, + RPMI_ERR_TIMEOUT =3D -12, + RPMI_ERR_IO =3D -13, + RPMI_ERR_NO_DATA =3D -14, + RPMI_ERR_RESERVED_START =3D -15, + RPMI_ERR_RESERVED_END =3D -127, + RPMI_ERR_VENDOR_START =3D -128 +}; + +static inline int rpmi_to_linux_error(int rpmi_error) +{ + switch (rpmi_error) { + case RPMI_SUCCESS: + return 0; + case RPMI_ERR_INVALID_PARAM: + case RPMI_ERR_BAD_RANGE: + case RPMI_ERR_INVALID_STATE: + return -EINVAL; + case RPMI_ERR_DENIED: + return -EPERM; + case RPMI_ERR_INVALID_ADDR: + case RPMI_ERR_HW_FAULT: + return -EFAULT; + case RPMI_ERR_ALREADY: + return -EALREADY; + case RPMI_ERR_BUSY: + return -EBUSY; + case RPMI_ERR_TIMEOUT: + return -ETIMEDOUT; + case RPMI_ERR_IO: + return -ECOMM; + case RPMI_ERR_FAILED: + case RPMI_ERR_NOTSUPP: + case RPMI_ERR_NO_DATA: + case RPMI_ERR_EXTENSION: + default: + return -EOPNOTSUPP; + } +} + +/* RPMI linux mailbox attribute IDs */ +enum rpmi_mbox_attribute_id { + RPMI_MBOX_ATTR_SPEC_VERSION =3D 0, + RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE, + RPMI_MBOX_ATTR_SERVICEGROUP_ID, + RPMI_MBOX_ATTR_SERVICEGROUP_VERSION, + RPMI_MBOX_ATTR_MAX_ID +}; + +/* RPMI linux mailbox message types */ +enum rpmi_mbox_message_type { + RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE =3D 0, + RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE, + RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE, + RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE, + RPMI_MBOX_MSG_TYPE_NOTIFICATION_EVENT, + RPMI_MBOX_MSG_MAX_TYPE +}; + +/* RPMI linux mailbox message instance */ +struct rpmi_mbox_message { + enum rpmi_mbox_message_type type; + union { + struct { + enum rpmi_mbox_attribute_id id; + u32 value; + } attr; + + struct { + u32 service_id; + void *request; + unsigned long request_len; + void *response; + unsigned long max_response_len; + unsigned long out_response_len; + } data; + + struct { + u16 event_datalen; + u8 event_id; + u8 *event_data; + } notif; + }; + int error; +}; + +/* RPMI linux mailbox message helper routines */ +static inline void rpmi_mbox_init_get_attribute(struct rpmi_mbox_message *= msg, + enum rpmi_mbox_attribute_id id) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE; + msg->attr.id =3D id; + msg->attr.value =3D 0; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_set_attribute(struct rpmi_mbox_message *= msg, + enum rpmi_mbox_attribute_id id, + u32 value) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE; + msg->attr.id =3D id; + msg->attr.value =3D value; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_send_with_response(struct rpmi_mbox_mess= age *msg, + u32 service_id, + void *request, + unsigned long request_len, + void *response, + unsigned long max_response_len) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE; + msg->data.service_id =3D service_id; + msg->data.request =3D request; + msg->data.request_len =3D request_len; + msg->data.response =3D response; + msg->data.max_response_len =3D max_response_len; + msg->data.out_response_len =3D 0; + msg->error =3D 0; +} + +static inline void rpmi_mbox_init_send_without_response(struct rpmi_mbox_m= essage *msg, + u32 service_id, + void *request, + unsigned long request_len) +{ + msg->type =3D RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE; + msg->data.service_id =3D service_id; + msg->data.request =3D request; + msg->data.request_len =3D request_len; + msg->data.response =3D NULL; + msg->data.max_response_len =3D 0; + msg->data.out_response_len =3D 0; + msg->error =3D 0; +} + +static inline int rpmi_mbox_send_message(struct mbox_chan *chan, + struct rpmi_mbox_message *msg) +{ + int ret; + + /* Send message for the underlying mailbox channel */ + ret =3D mbox_send_message(chan, msg); + if (ret < 0) + return ret; + + /* Explicitly signal txdone for mailbox channel */ + ret =3D msg->error; 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Sun, 25 May 2025 01:48:14 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 06/23] mailbox: Allow controller specific mapping using fwnode Date: Sun, 25 May 2025 14:16:53 +0530 Message-ID: <20250525084710.1665648-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce optional fw_node() callback which allows a mailbox controller driver to provide controller specific mapping using fwnode. The Linux OF framework already implements fwnode operations for the Linux DD framework so the fw_xlate() callback works fine with device tree as well. Signed-off-by: Anup Patel --- drivers/mailbox/mailbox.c | 47 +++++++++++++++++------------- include/linux/mailbox_controller.h | 3 ++ 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 0593b4d03685..0100163c0390 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -399,35 +399,49 @@ EXPORT_SYMBOL_GPL(mbox_bind_client); */ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) { + struct fwnode_reference_args fwspec; struct device *dev =3D cl->dev; struct mbox_controller *mbox; struct of_phandle_args spec; struct mbox_chan *chan; - int ret; + int i, ret; =20 - if (!dev || !dev->of_node) { - pr_debug("%s: No owner device node\n", __func__); + if (!dev || !dev->fwnode) { + pr_debug("%s: No owner %s\n", __func__, !dev ? "device" : "fwnode"); return ERR_PTR(-ENODEV); } =20 - ret =3D of_parse_phandle_with_args(dev->of_node, "mboxes", "#mbox-cells", - index, &spec); + ret =3D fwnode_property_get_reference_args(dev->fwnode, "mboxes", + "#mbox-cells", 0, index, &fwspec); if (ret) { dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); return ERR_PTR(ret); } =20 + memset(&spec, 0, sizeof(spec)); + if (dev->of_node) { + spec.np =3D to_of_node(fwspec.fwnode); + spec.args_count =3D fwspec.nargs; + for (i =3D 0; i < spec.args_count; i++) + spec.args[i] =3D fwspec.args[i]; + } + mutex_lock(&con_mutex); =20 chan =3D ERR_PTR(-EPROBE_DEFER); - list_for_each_entry(mbox, &mbox_cons, node) - if (mbox->dev->of_node =3D=3D spec.np) { + list_for_each_entry(mbox, &mbox_cons, node) { + if (mbox->fw_xlate && mbox->dev->fwnode =3D=3D fwspec.fwnode) { + chan =3D mbox->fw_xlate(mbox, &fwspec); + if (!IS_ERR(chan)) + break; + } else if (mbox->of_xlate && mbox->dev->of_node =3D=3D spec.np) { chan =3D mbox->of_xlate(mbox, &spec); if (!IS_ERR(chan)) break; } + } =20 - of_node_put(spec.np); + fwnode_handle_put(fwspec.fwnode); =20 if (IS_ERR(chan)) { mutex_unlock(&con_mutex); @@ -446,15 +460,8 @@ EXPORT_SYMBOL_GPL(mbox_request_channel); struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl, const char *name) { - struct device_node *np =3D cl->dev->of_node; - int index; - - if (!np) { - dev_err(cl->dev, "%s() currently only supports DT\n", __func__); - return ERR_PTR(-EINVAL); - } + int index =3D device_property_match_string(cl->dev, "mbox-names", name); =20 - index =3D of_property_match_string(np, "mbox-names", name); if (index < 0) { dev_err(cl->dev, "%s() could not locate channel named \"%s\"\n", __func__, name); @@ -492,8 +499,8 @@ void mbox_free_channel(struct mbox_chan *chan) EXPORT_SYMBOL_GPL(mbox_free_channel); =20 static struct mbox_chan * -of_mbox_index_xlate(struct mbox_controller *mbox, - const struct of_phandle_args *sp) +fw_mbox_index_xlate(struct mbox_controller *mbox, + const struct fwnode_reference_args *sp) { int ind =3D sp->args[0]; =20 @@ -544,8 +551,8 @@ int mbox_controller_register(struct mbox_controller *mb= ox) spin_lock_init(&chan->lock); } =20 - if (!mbox->of_xlate) - mbox->of_xlate =3D of_mbox_index_xlate; + if (!mbox->fw_xlate && !mbox->of_xlate) + mbox->fw_xlate =3D fw_mbox_index_xlate; =20 mutex_lock(&con_mutex); list_add_tail(&mbox->node, &mbox_cons); diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_con= troller.h index 5fb0b65f45a2..b91379922cb3 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -66,6 +66,7 @@ struct mbox_chan_ops { * no interrupt rises. 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Sun, 25 May 2025 01:48:23 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:48:22 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Date: Sun, 25 May 2025 14:16:54 +0530 Message-ID: <20250525084710.1665648-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a mailbox controller driver for the new SBI message proxy extension which is part of the SBI v3.0 specification. Co-developed-by: Rahul Pathak Signed-off-by: Rahul Pathak Signed-off-by: Anup Patel --- drivers/mailbox/Kconfig | 11 + drivers/mailbox/Makefile | 2 + drivers/mailbox/riscv-sbi-mpxy-mbox.c | 979 ++++++++++++++++++++++++++ 3 files changed, 992 insertions(+) create mode 100644 drivers/mailbox/riscv-sbi-mpxy-mbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ed52db272f4d..cc29a1a1974a 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -330,4 +330,15 @@ config THEAD_TH1520_MBOX kernel is running, and E902 core used for power management among other things. =20 +config RISCV_SBI_MPXY_MBOX + tristate "RISC-V SBI Message Proxy (MPXY) Mailbox" + depends on RISCV_SBI + default RISCV + help + Mailbox driver implementation for RISC-V SBI Message Proxy (MPXY) + extension. This mailbox driver is used to send messages to the + remote processor through the SBI implementation (M-mode firmware + or HS-mode hypervisor). Say Y here if you want to have this support. + If unsure say N. + endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 9a1542b55539..833d72649790 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -70,3 +70,5 @@ obj-$(CONFIG_QCOM_CPUCP_MBOX) +=3D qcom-cpucp-mbox.o obj-$(CONFIG_QCOM_IPCC) +=3D qcom-ipcc.o =20 obj-$(CONFIG_THEAD_TH1520_MBOX) +=3D mailbox-th1520.o + +obj-$(CONFIG_RISCV_SBI_MPXY_MBOX) +=3D riscv-sbi-mpxy-mbox.o diff --git a/drivers/mailbox/riscv-sbi-mpxy-mbox.c b/drivers/mailbox/riscv-= sbi-mpxy-mbox.c new file mode 100644 index 000000000000..121ee5fd3d0d --- /dev/null +++ b/drivers/mailbox/riscv-sbi-mpxy-mbox.c @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RISC-V SBI Message Proxy (MPXY) mailbox controller driver + * + * Copyright (C) 2025 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* =3D=3D=3D=3D=3D=3D SBI MPXY extension data structures =3D=3D=3D=3D=3D= =3D */ + +/* SBI MPXY MSI related channel attributes */ +struct sbi_mpxy_msi_info { + /* Lower 32-bits of the MSI target address */ + u32 msi_addr_lo; + /* Upper 32-bits of the MSI target address */ + u32 msi_addr_hi; + /* MSI data value */ + u32 msi_data; +}; + +/* + * SBI MPXY standard channel attributes. + * + * NOTE: The sequence of attribute fields are as-per the + * defined sequence in the attribute table in spec (or + * as-per the enum sbi_mpxy_attribute_id). + */ +struct sbi_mpxy_channel_attrs { + /* Message protocol ID */ + u32 msg_proto_id; + /* Message protocol version */ + u32 msg_proto_version; + /* Message protocol maximum message length */ + u32 msg_max_len; + /* Message protocol message send timeout in microseconds */ + u32 msg_send_timeout; + /* Message protocol message completion timeout in microseconds */ + u32 msg_completion_timeout; + /* Bit array for channel capabilities */ + u32 capability; + /* SSE event ID */ + u32 sse_event_id; + /* MSI enable/disable control knob */ + u32 msi_control; + /* Channel MSI info */ + struct sbi_mpxy_msi_info msi_info; + /* Events state control */ + u32 events_state_ctrl; +}; + +/* + * RPMI specific SBI MPXY channel attributes. + * + * NOTE: The sequence of attribute fields are as-per the + * defined sequence in the attribute table in spec (or + * as-per the enum sbi_mpxy_rpmi_attribute_id). + */ +struct sbi_mpxy_rpmi_channel_attrs { + /* RPMI service group ID */ + u32 servicegroup_id; + /* RPMI service group version */ + u32 servicegroup_version; +}; + +/* SBI MPXY channel IDs data in shared memory */ +struct sbi_mpxy_channel_ids_data { + /* Remaining number of channel ids */ + __le32 remaining; + /* Returned channel ids in current function call */ + __le32 returned; + /* Returned channel id array */ + __le32 channel_array[]; +}; + +/* SBI MPXY notification data in shared memory */ +struct sbi_mpxy_notification_data { + /* Remaining number of notification events */ + __le32 remaining; + /* Number of notification events returned */ + __le32 returned; + /* Number of notification events lost */ + __le32 lost; + /* Reserved for future use */ + __le32 reserved; + /* Returned channel id array */ + u8 events_data[]; +}; + +/* =3D=3D=3D=3D=3D=3D MPXY data structures & helper routines =3D=3D=3D=3D= =3D=3D */ + +/* MPXY Per-CPU or local context */ +struct mpxy_local { + /* Shared memory base address */ + void *shmem; + /* Shared memory physical address */ + phys_addr_t shmem_phys_addr; + /* Flag representing whether shared memory is active or not */ + bool shmem_active; +}; + +static DEFINE_PER_CPU(struct mpxy_local, mpxy_local); +static unsigned long mpxy_shmem_size; +static bool mpxy_shmem_init_done; + +static int mpxy_get_channel_count(u32 *channel_count) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbi_mpxy_channel_ids_data *sdata =3D mpxy->shmem; + u32 remaining, returned; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!channel_count) + return -EINVAL; + + get_cpu(); + + /* Get the remaining and returned fields to calculate total */ + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_CHANNEL_IDS, + 0, 0, 0, 0, 0, 0); + if (!sret.error) { + remaining =3D le32_to_cpu(sdata->remaining); + returned =3D le32_to_cpu(sdata->returned); + *channel_count =3D remaining + returned; + } + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_get_channel_ids(u32 channel_count, u32 *channel_ids) +{ + u32 remaining, returned, sidx, start_index =3D 0, cidx =3D 0; + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbi_mpxy_channel_ids_data *sdata =3D mpxy->shmem; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!channel_count || !channel_ids) + return -EINVAL; + + get_cpu(); + + do { + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_CHANNEL_IDS, + start_index, 0, 0, 0, 0, 0); + if (sret.error) + goto done; + + remaining =3D le32_to_cpu(sdata->remaining); + returned =3D le32_to_cpu(sdata->returned); + + for (sidx =3D 0; sidx < returned && cidx < channel_count; sidx++) { + channel_ids[cidx] =3D le32_to_cpu(sdata->channel_array[sidx]); + cidx +=3D 1; + } + + start_index =3D cidx; + + } while (remaining); + +done: + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_read_attrs(u32 channel_id, u32 base_attrid, u32 attr_count, + u32 *attrs_buf) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + u32 i; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!attr_count || !attrs_buf) + return -EINVAL; + + get_cpu(); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_READ_ATTRS, + channel_id, base_attrid, attr_count, 0, 0, 0); + if (!sret.error) { + for (i =3D 0; i < attr_count; i++) + attrs_buf[i] =3D le32_to_cpu(((__le32 *)mpxy->shmem)[i]); + } + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_write_attrs(u32 channel_id, u32 base_attrid, u32 attr_coun= t, + u32 *attrs_buf) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + u32 i; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!attr_count || !attrs_buf) + return -EINVAL; + + get_cpu(); + + for (i =3D 0; i < attr_count; i++) + ((__le32 *)mpxy->shmem)[i] =3D cpu_to_le32(attrs_buf[i]); + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_WRITE_ATTRS, + channel_id, base_attrid, attr_count, 0, 0, 0); + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_send_message_with_resp(u32 channel_id, u32 msg_id, + void *tx, unsigned long tx_len, + void *rx, unsigned long max_rx_len, + unsigned long *rx_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + unsigned long rx_bytes; + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!tx && tx_len) + return -EINVAL; + + get_cpu(); + + /* Message protocols allowed to have no data in messages */ + if (tx_len) + memcpy(mpxy->shmem, tx, tx_len); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SEND_MSG_WITH_RESP, + channel_id, msg_id, tx_len, 0, 0, 0); + if (rx && !sret.error) { + rx_bytes =3D sret.value; + if (rx_bytes > max_rx_len) { + put_cpu(); + return -ENOSPC; + } + + memcpy(rx, mpxy->shmem, rx_bytes); + if (rx_len) + *rx_len =3D rx_bytes; + } + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_send_message_without_resp(u32 channel_id, u32 msg_id, + void *tx, unsigned long tx_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!tx && tx_len) + return -EINVAL; + + get_cpu(); + + /* Message protocols allowed to have no data in messages */ + if (tx_len) + memcpy(mpxy->shmem, tx, tx_len); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP, + channel_id, msg_id, tx_len, 0, 0, 0); + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static int mpxy_get_notifications(u32 channel_id, + struct sbi_mpxy_notification_data *notif_data, + unsigned long *events_data_len) +{ + struct mpxy_local *mpxy =3D this_cpu_ptr(&mpxy_local); + struct sbiret sret; + + if (!mpxy->shmem_active) + return -ENODEV; + if (!notif_data || !events_data_len) + return -EINVAL; + + get_cpu(); + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS, + channel_id, 0, 0, 0, 0, 0); + if (!sret.error) { + memcpy(notif_data, mpxy->shmem, sret.value + 16); + *events_data_len =3D sret.value; + } + + put_cpu(); + return sbi_err_map_linux_errno(sret.error); +} + +static unsigned long mpxy_get_shmem_size(void) +{ + struct sbiret sret; + + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_GET_SHMEM_SIZE, + 0, 0, 0, 0, 0, 0); + if (sret.error) + return sbi_err_map_linux_errno(sret.error); + + return sret.value; +} + +static int mpxy_setup_shmem(unsigned int cpu) +{ + struct page *shmem_page; + struct mpxy_local *mpxy; + struct sbiret sret; + + mpxy =3D per_cpu_ptr(&mpxy_local, cpu); + if (mpxy->shmem_active) + return 0; + + shmem_page =3D alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(mpxy_shmem_= size)); + if (!shmem_page) + return -ENOMEM; + + /* + * Linux setup of shmem is done in mpxy OVERWRITE mode. + * flags[1:0] =3D 00b + */ + sret =3D sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_SET_SHMEM, + page_to_phys(shmem_page), 0, 0, 0, 0, 0); + if (sret.error) { + free_pages((unsigned long)page_to_virt(shmem_page), + get_order(mpxy_shmem_size)); + return sbi_err_map_linux_errno(sret.error); + } + + mpxy->shmem =3D page_to_virt(shmem_page); + mpxy->shmem_phys_addr =3D page_to_phys(shmem_page); + mpxy->shmem_active =3D true; + + return 0; +} + +/* =3D=3D=3D=3D=3D=3D MPXY mailbox data structures =3D=3D=3D=3D=3D=3D */ + +/* MPXY mailbox channel */ +struct mpxy_mbox_channel { + struct mpxy_mbox *mbox; + u32 channel_id; + struct sbi_mpxy_channel_attrs attrs; + struct sbi_mpxy_rpmi_channel_attrs rpmi_attrs; + struct sbi_mpxy_notification_data *notif; + u32 max_xfer_len; + bool have_events_state; + u32 msi_index; + u32 msi_irq; + bool started; +}; + +/* MPXY mailbox */ +struct mpxy_mbox { + struct device *dev; + u32 channel_count; + struct mpxy_mbox_channel *channels; + u32 msi_count; + struct mpxy_mbox_channel **msi_index_to_channel; + struct mbox_controller controller; +}; + +/* =3D=3D=3D=3D=3D=3D MPXY RPMI processing =3D=3D=3D=3D=3D=3D */ + +static int mpxy_mbox_send_rpmi_data(struct mpxy_mbox_channel *mchan, + struct rpmi_mbox_message *msg) +{ + int rc =3D 0; + + switch (msg->type) { + case RPMI_MBOX_MSG_TYPE_GET_ATTRIBUTE: + switch (msg->attr.id) { + case RPMI_MBOX_ATTR_SPEC_VERSION: + msg->attr.value =3D mchan->attrs.msg_proto_version; + break; + case RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE: + msg->attr.value =3D mchan->max_xfer_len; + break; + case RPMI_MBOX_ATTR_SERVICEGROUP_ID: + msg->attr.value =3D mchan->rpmi_attrs.servicegroup_id; + break; + case RPMI_MBOX_ATTR_SERVICEGROUP_VERSION: + msg->attr.value =3D mchan->rpmi_attrs.servicegroup_version; + break; + default: + rc =3D -EOPNOTSUPP; + break; + } + break; + case RPMI_MBOX_MSG_TYPE_SET_ATTRIBUTE: + /* None of the RPMI linux mailbox attributes are writeable */ + rc =3D -EOPNOTSUPP; + break; + case RPMI_MBOX_MSG_TYPE_SEND_WITH_RESPONSE: + if ((!msg->data.request && msg->data.request_len) || + (msg->data.request && + msg->data.request_len > mchan->max_xfer_len) || + (!msg->data.response && msg->data.max_response_len)) { + rc =3D -EINVAL; + break; + } + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_SEND_WITH_RESP)) { + rc =3D -EIO; + break; + } + rc =3D mpxy_send_message_with_resp(mchan->channel_id, + msg->data.service_id, + msg->data.request, + msg->data.request_len, + msg->data.response, + msg->data.max_response_len, + &msg->data.out_response_len); + break; + case RPMI_MBOX_MSG_TYPE_SEND_WITHOUT_RESPONSE: + if ((!msg->data.request && msg->data.request_len) || + (msg->data.request && + msg->data.request_len > mchan->max_xfer_len)) { + rc =3D -EINVAL; + break; + } + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP)) { + rc =3D -EIO; + break; + } + rc =3D mpxy_send_message_without_resp(mchan->channel_id, + msg->data.service_id, + msg->data.request, + msg->data.request_len); + break; + default: + rc =3D -EOPNOTSUPP; + break; + } + + msg->error =3D rc; + return 0; +} + +static void mpxy_mbox_peek_rpmi_data(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan, + struct sbi_mpxy_notification_data *notif, + unsigned long events_data_len) +{ + struct rpmi_notification_event *event; + unsigned long pos =3D 0, event_size; + struct rpmi_mbox_message msg; + + while ((pos < events_data_len) && !(pos & 0x3) && + ((events_data_len - pos) <=3D sizeof(*event))) { + event =3D (struct rpmi_notification_event *)(notif->events_data + pos); + + msg.type =3D RPMI_MBOX_MSG_TYPE_NOTIFICATION_EVENT; + msg.notif.event_datalen =3D le16_to_cpu(event->event_datalen); + msg.notif.event_id =3D event->event_id; + msg.notif.event_data =3D event->event_data; + msg.error =3D 0; + + event_size =3D sizeof(*event) + msg.notif.event_datalen; + if (event_size > (events_data_len - pos)) { + event_size =3D events_data_len - pos; + goto skip_event; + } + if (event_size & 0x3) + goto skip_event; + + mbox_chan_received_data(chan, &msg); + +skip_event: + pos +=3D event_size; + } +} + +static int mpxy_mbox_read_rpmi_attrs(struct mpxy_mbox_channel *mchan) +{ + return mpxy_read_attrs(mchan->channel_id, + SBI_MPXY_ATTR_MSGPROTO_ATTR_START, + sizeof(mchan->rpmi_attrs) / sizeof(u32), + (u32 *)&mchan->rpmi_attrs); +} + +/* =3D=3D=3D=3D=3D=3D MPXY mailbox callbacks =3D=3D=3D=3D=3D=3D */ + +static int mpxy_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) + return mpxy_mbox_send_rpmi_data(mchan, data); + + return -EOPNOTSUPP; +} + +static bool mpxy_mbox_peek_data(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + struct sbi_mpxy_notification_data *notif =3D mchan->notif; + bool have_notifications =3D false; + unsigned long data_len; + int rc; + + if (!(mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS)) + return false; + + while (1) { + rc =3D mpxy_get_notifications(mchan->channel_id, notif, &data_len); + if (rc || !data_len) + break; + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) + mpxy_mbox_peek_rpmi_data(chan, mchan, notif, data_len); + + have_notifications =3D true; + } + + return have_notifications; +} + +static irqreturn_t mpxy_mbox_irq_thread(int irq, void *dev_id) +{ + mpxy_mbox_peek_data(dev_id); + return IRQ_HANDLED; +} + +static int mpxy_mbox_setup_msi(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if MSI not supported */ + if (mchan->msi_irq =3D=3D U32_MAX) + return 0; + + /* Fail if MSI already enabled */ + if (mchan->attrs.msi_control) + return -EALREADY; + + /* Request channel MSI handler */ + rc =3D request_threaded_irq(mchan->msi_irq, NULL, mpxy_mbox_irq_thread, + 0, dev_name(dev), chan); + if (rc) { + dev_err(dev, "failed to request MPXY channel 0x%x IRQ\n", + mchan->channel_id); + return rc; + } + + /* Enable channel MSI control */ + mchan->attrs.msi_control =3D 1; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_CONTROL, + 1, &mchan->attrs.msi_control); + if (rc) { + dev_err(dev, "enable MSI control failed for MPXY channel 0x%x\n", + mchan->channel_id); + mchan->attrs.msi_control =3D 0; + free_irq(mchan->msi_irq, chan); + return rc; + } + + return 0; +} + +static void mpxy_mbox_cleanup_msi(struct mbox_chan *chan, + struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if MSI not supported */ + if (mchan->msi_irq =3D=3D U32_MAX) + return; + + /* Do nothing if MSI already disabled */ + if (!mchan->attrs.msi_control) + return; + + /* Disable channel MSI control */ + mchan->attrs.msi_control =3D 0; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_CONTROL, + 1, &mchan->attrs.msi_control); + if (rc) { + dev_err(dev, "disable MSI control failed for MPXY channel 0x%x\n", + mchan->channel_id); + } + + /* Free channel MSI handler */ + free_irq(mchan->msi_irq, chan); +} + +static int mpxy_mbox_setup_events(struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if events state not supported */ + if (!mchan->have_events_state) + return 0; + + /* Fail if events state already enabled */ + if (mchan->attrs.events_state_ctrl) + return -EALREADY; + + /* Enable channel events state */ + mchan->attrs.events_state_ctrl =3D 1; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_EVENTS_STATE_CON= TROL, + 1, &mchan->attrs.events_state_ctrl); + if (rc) { + dev_err(dev, "enable events state failed for MPXY channel 0x%x\n", + mchan->channel_id); + mchan->attrs.events_state_ctrl =3D 0; + return rc; + } + + return 0; +} + +static void mpxy_mbox_cleanup_events(struct mpxy_mbox_channel *mchan) +{ + struct device *dev =3D mchan->mbox->dev; + int rc; + + /* Do nothing if events state not supported */ + if (!mchan->have_events_state) + return; + + /* Do nothing if events state already disabled */ + if (!mchan->attrs.events_state_ctrl) + return; + + /* Disable channel events state */ + mchan->attrs.events_state_ctrl =3D 0; + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_EVENTS_STATE_CON= TROL, + 1, &mchan->attrs.events_state_ctrl); + if (rc) { + dev_err(dev, "disable events state failed for MPXY channel 0x%x\n", + mchan->channel_id); + } +} + +static int mpxy_mbox_startup(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + int rc; + + if (mchan->started) + return -EALREADY; + + /* Setup channel MSI */ + rc =3D mpxy_mbox_setup_msi(chan, mchan); + if (rc) + return rc; + + /* Setup channel notification events */ + rc =3D mpxy_mbox_setup_events(mchan); + if (rc) { + mpxy_mbox_cleanup_msi(chan, mchan); + return rc; + } + + /* Mark the channel as started */ + mchan->started =3D true; + + return 0; +} + +static void mpxy_mbox_shutdown(struct mbox_chan *chan) +{ + struct mpxy_mbox_channel *mchan =3D chan->con_priv; + + if (!mchan->started) + return; + + /* Mark the channel as stopped */ + mchan->started =3D false; + + /* Cleanup channel notification events */ + mpxy_mbox_cleanup_events(mchan); + + /* Cleanup channel MSI */ + mpxy_mbox_cleanup_msi(chan, mchan); +} + +static const struct mbox_chan_ops mpxy_mbox_ops =3D { + .send_data =3D mpxy_mbox_send_data, + .peek_data =3D mpxy_mbox_peek_data, + .startup =3D mpxy_mbox_startup, + .shutdown =3D mpxy_mbox_shutdown, +}; + +/* =3D=3D=3D=3D=3D=3D MPXY platform driver =3D=3D=3D=3D=3D */ + +static void mpxy_mbox_msi_write(struct msi_desc *desc, struct msi_msg *msg) +{ + struct device *dev =3D msi_desc_to_dev(desc); + struct mpxy_mbox *mbox =3D dev_get_drvdata(dev); + struct mpxy_mbox_channel *mchan; + struct sbi_mpxy_msi_info *minfo; + int rc; + + mchan =3D mbox->msi_index_to_channel[desc->msi_index]; + if (!mchan) { + dev_warn(dev, "MPXY channel not available for MSI index %d\n", + desc->msi_index); + return; + } + + minfo =3D &mchan->attrs.msi_info; + minfo->msi_addr_lo =3D msg->address_lo; + minfo->msi_addr_hi =3D msg->address_hi; + minfo->msi_data =3D msg->data; + + rc =3D mpxy_write_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSI_ADDR_LO, + sizeof(*minfo) / sizeof(u32), (u32 *)minfo); + if (rc) { + dev_warn(dev, "failed to write MSI info for MPXY channel 0x%x\n", + mchan->channel_id); + } +} + +static struct mbox_chan *mpxy_mbox_fw_xlate(struct mbox_controller *ctlr, + const struct fwnode_reference_args *pa) +{ + struct mpxy_mbox *mbox =3D container_of(ctlr, struct mpxy_mbox, controlle= r); + struct mpxy_mbox_channel *mchan; + u32 i; + + if (pa->nargs !=3D 2) + return ERR_PTR(-EINVAL); + + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->channel_id =3D=3D pa->args[0] && + mchan->attrs.msg_proto_id =3D=3D pa->args[1]) + return &mbox->controller.chans[i]; + } + + return ERR_PTR(-ENOENT); +} + +static int mpxy_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mpxy_mbox_channel *mchan; + struct mpxy_mbox *mbox; + int i, msi_idx, rc; + u32 *channel_ids; + + /* + * Initialize MPXY shared memory only once. This also ensures + * that SBI MPXY mailbox is probed only once. + */ + if (mpxy_shmem_init_done) { + dev_err(dev, "SBI MPXY mailbox already initialized\n"); + return -EALREADY; + } + + /* Probe for SBI MPXY extension */ + if (sbi_spec_version < sbi_mk_version(1, 0) || + sbi_probe_extension(SBI_EXT_MPXY) <=3D 0) { + dev_info(dev, "SBI MPXY extension not available\n"); + return -ENODEV; + } + + /* Find-out shared memory size */ + mpxy_shmem_size =3D mpxy_get_shmem_size(); + + /* + * Setup MPXY shared memory on each CPU + * + * Note: Don't cleanup MPXY shared memory upon CPU power-down + * because the RPMI System MSI irqchip driver needs it to be + * available when migrating IRQs in CPU power-down path. + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/sbi-mpxy-shmem", + mpxy_setup_shmem, NULL); + + /* Mark as MPXY shared memory initialization done */ + mpxy_shmem_init_done =3D true; + + /* Allocate mailbox instance */ + mbox =3D devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + mbox->dev =3D dev; + platform_set_drvdata(pdev, mbox); + + /* Find-out of number of channels */ + rc =3D mpxy_get_channel_count(&mbox->channel_count); + if (rc) + return dev_err_probe(dev, rc, "failed to get number of MPXY channels\n"); + if (!mbox->channel_count) + dev_err_probe(dev, -ENODEV, "no MPXY channels available\n"); + + /* Allocate and fetch all channel IDs */ + channel_ids =3D devm_kcalloc(dev, mbox->channel_count, + sizeof(*channel_ids), GFP_KERNEL); + if (!channel_ids) + return -ENOMEM; + rc =3D mpxy_get_channel_ids(mbox->channel_count, channel_ids); + if (rc) + return dev_err_probe(dev, rc, "failed to MPXY channel IDs\n"); + + /* Populate all channels */ + mbox->channels =3D devm_kcalloc(dev, mbox->channel_count, + sizeof(*mbox->channels), GFP_KERNEL); + if (!mbox->channels) + return -ENOMEM; + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + mchan->mbox =3D mbox; + mchan->channel_id =3D channel_ids[i]; + + rc =3D mpxy_read_attrs(mchan->channel_id, SBI_MPXY_ATTR_MSG_PROT_ID, + sizeof(mchan->attrs) / sizeof(u32), + (u32 *)&mchan->attrs); + if (rc) { + return dev_err_probe(dev, rc, + "MPXY channel 0x%x read attrs failed\n", + mchan->channel_id); + } + + if (mchan->attrs.msg_proto_id =3D=3D SBI_MPXY_MSGPROTO_RPMI_ID) { + rc =3D mpxy_mbox_read_rpmi_attrs(mchan); + if (rc) { + return dev_err_probe(dev, rc, + "MPXY channel 0x%x read RPMI attrs failed\n", + mchan->channel_id); + } + } + + mchan->notif =3D devm_kzalloc(dev, mpxy_shmem_size, GFP_KERNEL); + if (!mchan->notif) + return -ENOMEM; + + mchan->max_xfer_len =3D min(mpxy_shmem_size, mchan->attrs.msg_max_len); + + if ((mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS) && + (mchan->attrs.capability & SBI_MPXY_CHAN_CAP_EVENTS_STATE)) + mchan->have_events_state =3D true; + + if ((mchan->attrs.capability & SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS) && + (mchan->attrs.capability & SBI_MPXY_CHAN_CAP_MSI)) + mchan->msi_index =3D mbox->msi_count++; + else + mchan->msi_index =3D U32_MAX; + mchan->msi_irq =3D U32_MAX; + } + + /* Free-up channel IDs */ + devm_kfree(dev, channel_ids); + + /* Initialize mailbox controller */ + mbox->controller.txdone_irq =3D false; + mbox->controller.txdone_poll =3D false; + mbox->controller.ops =3D &mpxy_mbox_ops; + mbox->controller.dev =3D dev; + mbox->controller.num_chans =3D mbox->channel_count; + mbox->controller.fw_xlate =3D mpxy_mbox_fw_xlate; + mbox->controller.chans =3D devm_kcalloc(dev, mbox->channel_count, + sizeof(*mbox->controller.chans), + GFP_KERNEL); + if (!mbox->controller.chans) + return -ENOMEM; + for (i =3D 0; i < mbox->channel_count; i++) + mbox->controller.chans[i].con_priv =3D &mbox->channels[i]; + + /* Set the MSI domain if not available */ + if (!dev_get_msi_domain(dev)) { + /* + * The device MSI domain for OF devices is only set at the + * time of populating/creating OF device. If the device MSI + * domain is discovered later after the OF device is created + * then we need to set it explicitly before using any platform + * MSI functions. + */ + if (is_of_node(dev_fwnode(dev))) + of_msi_configure(dev, to_of_node(dev_fwnode(dev))); + } + + /* Setup MSIs for mailbox (if required) */ + if (mbox->msi_count) { + mbox->msi_index_to_channel =3D devm_kcalloc(dev, mbox->msi_count, + sizeof(*mbox->msi_index_to_channel), + GFP_KERNEL); + if (!mbox->msi_index_to_channel) + return -ENOMEM; + + for (msi_idx =3D 0; msi_idx < mbox->msi_count; msi_idx++) { + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->msi_index =3D=3D msi_idx) { + mbox->msi_index_to_channel[msi_idx] =3D mchan; + break; + } + } + } + + rc =3D platform_device_msi_init_and_alloc_irqs(dev, mbox->msi_count, + mpxy_mbox_msi_write); + if (rc) { + return dev_err_probe(dev, rc, "Failed to allocate %d MSIs\n", + mbox->msi_count); + } + + for (i =3D 0; i < mbox->channel_count; i++) { + mchan =3D &mbox->channels[i]; + if (mchan->msi_index =3D=3D U32_MAX) + continue; + mchan->msi_irq =3D msi_get_virq(dev, mchan->msi_index); + } + } + + /* Register mailbox controller */ + rc =3D devm_mbox_controller_register(dev, &mbox->controller); + if (rc) { + dev_err_probe(dev, rc, "Registering SBI MPXY mailbox failed\n"); + if (mbox->msi_count) + platform_device_msi_free_irqs_all(dev); + return rc; + } + + dev_info(dev, "mailbox registered with %d channels\n", + mbox->channel_count); + return 0; +} + +static void mpxy_mbox_remove(struct platform_device *pdev) +{ + struct mpxy_mbox *mbox =3D platform_get_drvdata(pdev); + + if (mbox->msi_count) + platform_device_msi_free_irqs_all(mbox->dev); +} + +static const struct of_device_id mpxy_mbox_of_match[] =3D { + {.compatible =3D "riscv,sbi-mpxy-mbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpxy_mbox_of_match); + +static struct platform_driver mpxy_mbox_driver =3D { + .driver =3D { + .name =3D "riscv-sbi-mpxy-mbox", + .of_match_table =3D mpxy_mbox_of_match, + }, + .probe =3D mpxy_mbox_probe, + .remove =3D mpxy_mbox_remove, +}; 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Sun, 25 May 2025 01:48:30 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Date: Sun, 25 May 2025 14:16:55 +0530 Message-ID: <20250525084710.1665648-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Signed-off-by: Anup Patel --- .../bindings/clock/riscv,rpmi-mpxy-clock.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy= -clock.yaml diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.= yaml b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml new file mode 100644 index 000000000000..39db52de86b3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The SBI implementat= ion + (machine mode firmware or hypervisor) can implement an SBI MPXY channel + to allow RPMI clock service group access to the supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "riscv,rpmi-mpxy-clock"; + mboxes =3D <&rpmi_shmem_mbox 0x8>; + riscv,sbi-mpxy-channel-id =3D <0x1000>; + }; +... --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A39D19FA93 for ; Sun, 25 May 2025 08:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162922; cv=none; b=i13UsY/ybvZwqkl7Gbh06rQOS05VPa+/3dTNgx7aKcXBpO9DEZiUygikiHdCHAsZPtbHwHeqNI6Q8BW2ZgJl/pp7Z0UgRxm6YwPcgAlpTFTewKnrzvTeJn52lx0HUIltop0TRLorxMTiBUbwmTyvektU/QfFoYAcM58RYTTNupg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162922; c=relaxed/simple; bh=Q274OnfG3podIQmVKmeGWN09V8KF3qj8jlwfrCOnBJY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Sun, 25 May 2025 01:48:39 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Date: Sun, 25 May 2025 14:16:56 +0530 Message-ID: <20250525084710.1665648-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../bindings/clock/riscv,rpmi-clock.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-cloc= k.yaml diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml = b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml new file mode 100644 index 000000000000..9c672a38595a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based clock controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The supervisor + software can access RPMI clock service group via SBI MPXY channel or + some dedicated supervisor-mode RPMI transport. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message prox= y channel. + + "#clock-cells": + const: 1 + +required: + - compatible + - mboxes + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "riscv,rpmi-clock"; + mboxes =3D <&mpxy_mbox 0x1000 0x0>; + #clock-cells =3D <1>; + }; +... --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BB6F1E5B8A for ; Sun, 25 May 2025 08:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162931; cv=none; b=W2dzNkFYSYgE2SQrFEL04kxqsZJZDbPQQfli531x+OAecRYNk6uLOE8VmE6g+SCAtupj7mkHTjsObyqonTQnJTeDDOusSN8FmD4Tn3rH6CTeEcmk8yzObXo/fwArSYwic/ElvE5TYQlwTonG++ETGJ1rvNAPQFLbZ4+oWLUJYL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162931; c=relaxed/simple; bh=55GSbeFsp/jpg0gJGDF6k2OfJY/IIDpX0is2Z+kR9UI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Sun, 25 May 2025 01:48:47 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Date: Sun, 25 May 2025 14:16:57 +0530 Message-ID: <20250525084710.1665648-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rahul Pathak The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak --- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-rpmi.c | 589 +++++++++++++++++++++ include/linux/mailbox/riscv-rpmi-message.h | 16 + include/linux/wordpart.h | 8 + 5 files changed, 622 insertions(+) create mode 100644 drivers/clk/clk-rpmi.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 713573b6c86c..d89308c7f75c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -493,6 +493,14 @@ config COMMON_CLK_SP7021 Not all features of the PLL are currently supported by the driver. =20 +config COMMON_CLK_RPMI + tristate "Clock driver based on RISC-V RPMI" + depends on MAILBOX + default RISCV + help + Support for clocks based on the clock service group defined by + the RISC-V platform management interface (RPMI) specification. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index bf4bd45adc3a..b8588ab789c3 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) +=3D clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) +=3D clk-pwm.o obj-$(CONFIG_CLK_QORIQ) +=3D clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) +=3D clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RPMI) +=3D clk-rpmi.o obj-$(CONFIG_COMMON_CLK_HI655X) +=3D clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) +=3D clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) +=3D clk-scmi.o diff --git a/drivers/clk/clk-rpmi.c b/drivers/clk/clk-rpmi.c new file mode 100644 index 000000000000..0ab2d916c8be --- /dev/null +++ b/drivers/clk/clk-rpmi.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RISC-V MPXY Based Clock Driver + * + * Copyright (C) 2025 Ventana Micro Systems Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPMI_CLK_DISCRETE_MAX_NUM_RATES 16 +#define RPMI_CLK_NAME_LEN 16 + +#define to_rpmi_clk(clk) container_of(clk, struct rpmi_clk, hw) + +#define rpmi_clkrate_u64(hi, lo) get_u64_from_u32(hi, lo) + +enum rpmi_clk_config { + RPMI_CLK_DISABLE =3D 0, + RPMI_CLK_ENABLE =3D 1 +}; + +enum rpmi_clk_type { + RPMI_CLK_DISCRETE =3D 0, + RPMI_CLK_LINEAR =3D 1, + RPMI_CLK_TYPE_MAX_IDX +}; + +struct rpmi_clk_context { + struct device *dev; + struct mbox_chan *chan; + struct mbox_client client; + u32 max_msg_data_size; +}; + +union rpmi_clk_rates { + u64 discrete[RPMI_CLK_DISCRETE_MAX_NUM_RATES]; + struct { + u64 min; + u64 max; + u64 step; + } linear; +}; + +struct rpmi_clk { + struct rpmi_clk_context *context; + u32 id; + u32 num_rates; + u32 transition_latency; + enum rpmi_clk_type type; + union rpmi_clk_rates *rates; + char name[RPMI_CLK_NAME_LEN]; + struct clk_hw hw; +}; + +struct rpmi_clk_rate_discrete { + __le32 lo; + __le32 hi; +}; + +struct rpmi_clk_rate_linear { + __le32 min_lo; + __le32 min_hi; + __le32 max_lo; + __le32 max_hi; + __le32 step_lo; + __le32 step_hi; +}; + +struct rpmi_get_num_clocks_rx { + __le32 status; + __le32 num_clocks; +}; + +struct rpmi_get_attrs_tx { + __le32 clkid; +}; + +struct rpmi_get_attrs_rx { + __le32 status; + __le32 flags; + __le32 num_rates; + __le32 transition_latency; + char name[RPMI_CLK_NAME_LEN]; +}; + +struct rpmi_get_supp_rates_tx { + __le32 clkid; + __le32 clk_rate_idx; +}; + +struct rpmi_get_supp_rates_rx { + __le32 status; + __le32 flags; + __le32 remaining; + __le32 returned; + __le32 rates[]; +}; + +struct rpmi_get_rate_tx { + __le32 clkid; +}; + +struct rpmi_get_rate_rx { + __le32 status; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_tx { + __le32 clkid; + __le32 flags; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_rx { + __le32 status; +}; + +struct rpmi_set_config_tx { + __le32 clkid; + __le32 config; +}; + +struct rpmi_set_config_rx { + __le32 status; +}; + +static u32 rpmi_clk_get_num_clocks(struct rpmi_clk_context *context) +{ + struct rpmi_get_num_clocks_rx rx; + struct rpmi_mbox_message msg; + int ret; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_NUM_CLOCKS, + NULL, 0, &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + + if (ret || rx.status) + return 0; + + return le32_to_cpu(rx.num_clocks); +} + +static int rpmi_clk_get_attrs(u32 clkid, struct rpmi_clk *rpmi_clk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_attrs_tx tx; + struct rpmi_get_attrs_rx rx; + u8 format; + int ret; + + tx.clkid =3D cpu_to_le32(clkid); + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_ATTRIBUTES, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + rpmi_clk->id =3D clkid; + rpmi_clk->num_rates =3D le32_to_cpu(rx.num_rates); + rpmi_clk->transition_latency =3D le32_to_cpu(rx.transition_latency); + strscpy(rpmi_clk->name, rx.name, RPMI_CLK_NAME_LEN); + + format =3D le32_to_cpu(rx.flags) & 3U; + if (format >=3D RPMI_CLK_TYPE_MAX_IDX) + return -EINVAL; + + rpmi_clk->type =3D format; + + return 0; +} + +static int rpmi_clk_get_supported_rates(u32 clkid, struct rpmi_clk *rpmi_c= lk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_clk_rate_discrete *rate_discrete; + struct rpmi_clk_rate_linear *rate_linear; + struct rpmi_get_supp_rates_rx *rx __free(kfree) =3D NULL; + struct rpmi_get_supp_rates_tx tx; + struct rpmi_mbox_message msg; + size_t clk_rate_idx =3D 0; + int ret, rateidx, j; + + tx.clkid =3D cpu_to_le32(clkid); + tx.clk_rate_idx =3D 0; + + /* + * Make sure we allocate rx buffer sufficient to be accommodate all + * the rates sent in one RPMI message. + */ + rx =3D kzalloc(context->max_msg_data_size, GFP_KERNEL); + if (!rx) + return -ENOMEM; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), rx, context->max_msg_data_size); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx->status) + return rpmi_to_linux_error(le32_to_cpu(rx->status)); + if (!le32_to_cpu(rx->returned)) + return -EINVAL; + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + rate_discrete =3D (struct rpmi_clk_rate_discrete *)rx->rates; + + for (rateidx =3D 0; rateidx < le32_to_cpu(rx->returned); rateidx++) { + rpmi_clk->rates->discrete[rateidx] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[rateidx].hi), + le32_to_cpu(rate_discrete[rateidx].lo)); + } + + /* + * Keep sending the request message until all + * the rates are received. + */ + while (le32_to_cpu(rx->remaining)) { + clk_rate_idx +=3D le32_to_cpu(rx->returned); + tx.clk_rate_idx =3D cpu_to_le32(clk_rate_idx); + + rpmi_mbox_init_send_with_response(&msg, + RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), + rx, context->max_msg_data_size); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx->status) + return rpmi_to_linux_error(le32_to_cpu(rx->status)); + if (!le32_to_cpu(rx->returned)) + return -EINVAL; + + for (j =3D 0; j < le32_to_cpu(rx->returned); j++) { + if (rateidx >=3D clk_rate_idx + le32_to_cpu(rx->returned)) + break; + rpmi_clk->rates->discrete[rateidx++] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[j].hi), + le32_to_cpu(rate_discrete[j].lo)); + } + } + } else if (rpmi_clk->type =3D=3D RPMI_CLK_LINEAR) { + rate_linear =3D (struct rpmi_clk_rate_linear *)rx->rates; + + rpmi_clk->rates->linear.min =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->min_hi), + le32_to_cpu(rate_linear->min_lo)); + rpmi_clk->rates->linear.max =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->max_hi), + le32_to_cpu(rate_linear->max_lo)); + rpmi_clk->rates->linear.step =3D rpmi_clkrate_u64(le32_to_cpu(rate_linea= r->step_hi), + le32_to_cpu(rate_linear->step_lo)); + } + + return 0; +} + +static unsigned long rpmi_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_rate_tx tx; + struct rpmi_get_rate_rx rx; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return rpmi_clkrate_u64(le32_to_cpu(rx.hi), le32_to_cpu(rx.lo)); +} + +static int rpmi_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + u64 fmin, fmax, ftmp; + + /* + * Keep the requested rate if the clock format + * is of discrete type. Let the platform which + * is actually controlling the clock handle that. + */ + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) + return 0; + + fmin =3D rpmi_clk->rates->linear.min; + fmax =3D rpmi_clk->rates->linear.max; + + if (req->rate <=3D fmin) { + req->rate =3D fmin; + return 0; + } else if (req->rate >=3D fmax) { + req->rate =3D fmax; + return 0; + } + + ftmp =3D req->rate - fmin; + ftmp +=3D rpmi_clk->rates->linear.step - 1; + do_div(ftmp, rpmi_clk->rates->linear.step); + + req->rate =3D ftmp * rpmi_clk->rates->linear.step + fmin; + + return 0; +} + +static int rpmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_rate_tx tx; + struct rpmi_set_rate_rx rx; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + tx.lo =3D cpu_to_le32(lower_32_bits(rate)); + tx.hi =3D cpu_to_le32(upper_32_bits(rate)); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static int rpmi_clk_enable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx; + int ret; + + tx.config =3D cpu_to_le32(RPMI_CLK_ENABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static void rpmi_clk_disable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx; + int ret; + + tx.config =3D cpu_to_le32(RPMI_CLK_DISABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret || rx.status) + pr_err("Failed to disable clk-%u\n", rpmi_clk->id); +} + +static const struct clk_ops rpmi_clk_ops =3D { + .recalc_rate =3D rpmi_clk_recalc_rate, + .determine_rate =3D rpmi_clk_determine_rate, + .set_rate =3D rpmi_clk_set_rate, + .prepare =3D rpmi_clk_enable, + .unprepare =3D rpmi_clk_disable, +}; + +static struct clk_hw *rpmi_clk_enumerate(struct rpmi_clk_context *context,= u32 clkid) +{ + struct device *dev =3D context->dev; + unsigned long min_rate, max_rate; + union rpmi_clk_rates *rates; + struct rpmi_clk *rpmi_clk; + struct clk_init_data init =3D {}; + struct clk_hw *clk_hw; + int ret; + + rates =3D devm_kzalloc(dev, sizeof(*rates), GFP_KERNEL); + if (!rates) + return ERR_PTR(-ENOMEM); + + rpmi_clk =3D devm_kzalloc(dev, sizeof(*rpmi_clk), GFP_KERNEL); + if (!rpmi_clk) + return ERR_PTR(-ENOMEM); + + rpmi_clk->context =3D context; + rpmi_clk->rates =3D rates; + + ret =3D rpmi_clk_get_attrs(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Failed to get clk-%u attributes\n", + clkid); + + ret =3D rpmi_clk_get_supported_rates(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Get supported rates failed for clk-%u\n", + clkid); + + init.flags =3D CLK_GET_RATE_NOCACHE; + init.num_parents =3D 0; + init.ops =3D &rpmi_clk_ops; + init.name =3D rpmi_clk->name; + clk_hw =3D &rpmi_clk->hw; + clk_hw->init =3D &init; + + ret =3D devm_clk_hw_register(dev, clk_hw); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Unable to register clk-%u\n", + clkid); + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + min_rate =3D rpmi_clk->rates->discrete[0]; + max_rate =3D rpmi_clk->rates->discrete[rpmi_clk->num_rates - 1]; + } else { + min_rate =3D rpmi_clk->rates->linear.min; + max_rate =3D rpmi_clk->rates->linear.max; + } + + clk_hw_set_rate_range(clk_hw, min_rate, max_rate); + + return clk_hw; +} + +static int rpmi_clk_probe(struct platform_device *pdev) +{ + int ret; + unsigned int num_clocks, i; + struct clk_hw_onecell_data *clk_data; + struct rpmi_clk_context *context; + struct rpmi_mbox_message msg; + struct clk_hw *hw_ptr; + struct device *dev =3D &pdev->dev; + + context =3D devm_kzalloc(dev, sizeof(*context), GFP_KERNEL); + if (!context) + return -ENOMEM; + context->dev =3D dev; + platform_set_drvdata(pdev, context); + + context->client.dev =3D context->dev; + context->client.rx_callback =3D NULL; + context->client.tx_block =3D false; + context->client.knows_txdone =3D true; + context->client.tx_tout =3D 0; + + context->chan =3D mbox_request_channel(&context->client, 0); + if (IS_ERR(context->chan)) + return PTR_ERR(context->chan); + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SPEC_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, ret, "Failed to get spec version\n"); + } + if (msg.attr.value < RPMI_MKVER(1, 0)) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, -EINVAL, + "msg protocol version mismatch, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_ID); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, ret, "Failed to get service group ID\n"); + } + if (msg.attr.value !=3D RPMI_SRVGRP_CLOCK) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, -EINVAL, + "service group match failed, expected 0x%x, found 0x%x\n", + RPMI_SRVGRP_CLOCK, msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, ret, "Failed to get service group version\n"); + } + if (msg.attr.value < RPMI_MKVER(1, 0)) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, -EINVAL, + "service group version failed, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, ret, "Failed to get max message data size\n"); + } + + context->max_msg_data_size =3D msg.attr.value; + num_clocks =3D rpmi_clk_get_num_clocks(context); + if (!num_clocks) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, -ENODEV, "No clocks found\n"); + } + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_clocks), + GFP_KERNEL); + if (!clk_data) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, -ENOMEM, "No memory for clock data\n"); + } + clk_data->num =3D num_clocks; + + for (i =3D 0; i < clk_data->num; i++) { + hw_ptr =3D rpmi_clk_enumerate(context, i); + if (IS_ERR(hw_ptr)) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, PTR_ERR(hw_ptr), + "failed to register clk-%d\n", i); + } + clk_data->hws[i] =3D hw_ptr; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) { + mbox_free_channel(context->chan); + return dev_err_probe(dev, ret, "failed to register clock HW provider\n"); + } + + return 0; +} + +static void rpmi_clk_remove(struct platform_device *pdev) +{ + struct rpmi_clk_context *context =3D platform_get_drvdata(pdev); + + mbox_free_channel(context->chan); +} + +static const struct of_device_id rpmi_clk_of_match[] =3D { + { .compatible =3D "riscv,rpmi-clock" }, + { } +}; +MODULE_DEVICE_TABLE(of, rpmi_clk_of_match); + +static struct platform_driver rpmi_clk_driver =3D { + .driver =3D { + .name =3D "riscv-rpmi-clock", + .of_match_table =3D rpmi_clk_of_match, + }, + .probe =3D rpmi_clk_probe, + .remove =3D rpmi_clk_remove, +}; +module_platform_driver(rpmi_clk_driver); + +MODULE_AUTHOR("Rahul Pathak "); +MODULE_DESCRIPTION("Clock Driver based on RPMI message protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h index 6201d4dd6047..18b606e0023c 100644 --- a/include/linux/mailbox/riscv-rpmi-message.h +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -87,6 +87,22 @@ static inline int rpmi_to_linux_error(int rpmi_error) } } =20 +/* RPMI service group IDs */ +#define RPMI_SRVGRP_CLOCK 0x00008 + +/* RPMI clock service IDs */ +enum rpmi_clock_service_id { + RPMI_CLK_SRV_ENABLE_NOTIFICATION =3D 0x01, + RPMI_CLK_SRV_GET_NUM_CLOCKS =3D 0x02, + RPMI_CLK_SRV_GET_ATTRIBUTES =3D 0x03, + RPMI_CLK_SRV_GET_SUPPORTED_RATES =3D 0x04, + RPMI_CLK_SRV_SET_CONFIG =3D 0x05, + RPMI_CLK_SRV_GET_CONFIG =3D 0x06, + RPMI_CLK_SRV_SET_RATE =3D 0x07, + RPMI_CLK_SRV_GET_RATE =3D 0x08, + RPMI_CLK_SRV_ID_MAX_COUNT +}; + /* RPMI linux mailbox attribute IDs */ enum rpmi_mbox_attribute_id { RPMI_MBOX_ATTR_SPEC_VERSION =3D 0, diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h index 5a7b97bb7c95..1ab72ebd6878 100644 --- a/include/linux/wordpart.h +++ b/include/linux/wordpart.h @@ -31,6 +31,14 @@ */ #define lower_16_bits(n) ((u16)((n) & 0xffff)) =20 +/** + * get_u64_from_u32(hi, lo) - return u64 number by combining + * two u32 numbers. + * @hi: upper 32 bit number + * @lo: lower 32 bit number + */ +#define get_u64_from_u32(hi, lo) (((u64)(hi) << 32) | (u32)(lo)) + /** * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long va= lue * @x: value to repeat --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FC791EEA49 for ; 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Sun, 25 May 2025 01:48:56 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.48.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:48:56 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Date: Sun, 25 May 2025 14:16:58 +0530 Message-ID: <20250525084710.1665648-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI system MSI service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- .../riscv,rpmi-mpxy-system-msi.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,rpmi-mpxy-system-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,r= pmi-mpxy-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-cont= roller/riscv,rpmi-mpxy-system-msi.yaml new file mode 100644 index 000000000000..26dd13731350 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpx= y-system-msi.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-sy= stem-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The SBI implementation machine mode firmware or hypervisor) can + implement an SBI MPXY channel to allow RPMI system MSI service + group access to the supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible =3D "riscv,rpmi-mpxy-system-msi"; + mboxes =3D <&rpmi_shmem_mbox 0x2>; + riscv,sbi-mpxy-channel-id =3D <0x2000>; + }; +... --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C7E11E5734 for ; Sun, 25 May 2025 08:49:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162947; cv=none; b=lI1TjzVuIZQDBtmqiylDznUYVDcl2qaS+v3e2Z7Fk1jU4rkzigaVRsS/c8EPQJgqb+dEGdGunUdAOSkNOI0bQhCgPlNAM11dnQb5pyUpts/06G84zS8pIcJ8ryrkdLzstrAriYbZUcAmSZolsQFWtcYBpYc+Bgrt1/tPOYvkvGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748162947; c=relaxed/simple; bh=jCfuPkwpFJl2q7jmzk6VEllmsuHOcm1t3a2xapvV24I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Sun, 25 May 2025 01:49:04 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Date: Sun, 25 May 2025 14:16:59 +0530 Message-ID: <20250525084710.1665648-13-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the RPMI system MSI service group based interrupt controller for the supervisor software. The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- .../riscv,rpmi-system-msi.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,rpmi-system-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,r= pmi-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controlle= r/riscv,rpmi-system-msi.yaml new file mode 100644 index 000000000000..ac13cec0666e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-sys= tem-msi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-= msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based interrupt controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The supervisor software can access RPMI system MSI service group via + SBI MPXY channel or some dedicated supervisor-mode RPMI transport. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message prox= y channel. + + msi-parent: true + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - mboxes + - msi-parent + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible =3D "riscv,rpmi-system-msi"; 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Sun, 25 May 2025 01:49:12 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 13/23] irqchip: Add driver for the RPMI system MSI service group Date: Sun, 25 May 2025 14:17:00 +0530 Message-ID: <20250525084710.1665648-14-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-rpmi-sysmsi.c | 284 +++++++++++++++++++++ include/linux/mailbox/riscv-rpmi-message.h | 13 + 4 files changed, 305 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-rpmi-sysmsi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 08bb3b031f23..83700fc2ddc9 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -612,6 +612,13 @@ config RISCV_IMSIC select GENERIC_MSI_IRQ select IRQ_MSI_LIB =20 +config RISCV_RPMI_SYSMSI + bool + depends on MAILBOX + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + default RISCV + config SIFIVE_PLIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 365bcea9a61f..515280da499c 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o obj-$(CONFIG_RISCV_APLIC) +=3D irq-riscv-aplic-main.o irq-riscv-aplic-dir= ect.o obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi.o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o +obj-$(CONFIG_RISCV_RPMI_SYSMSI) +=3D irq-riscv-rpmi-sysmsi.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o diff --git a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c b/drivers/irqchip/irq-= riscv-rpmi-sysmsi.c new file mode 100644 index 000000000000..d7b19fb7bf4e --- /dev/null +++ b/drivers/irqchip/irq-riscv-rpmi-sysmsi.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2025 Ventana Micro Systems Inc. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rpmi_sysmsi_get_attrs_rx { + __le32 status; + __le32 sys_num_msi; + __le32 flag0; + __le32 flag1; +}; + +#define RPMI_SYSMSI_MSI_ATTRIBUTES_FLAG0_PREF_PRIV BIT(0) + +struct rpmi_sysmsi_set_msi_state_tx { + __le32 sys_msi_index; + __le32 sys_msi_state; +}; + +struct rpmi_sysmsi_set_msi_state_rx { + __le32 status; +}; + +#define RPMI_SYSMSI_MSI_STATE_ENABLE BIT(0) +#define RPMI_SYSMSI_MSI_STATE_PENDING BIT(1) + +struct rpmi_sysmsi_set_msi_target_tx { + __le32 sys_msi_index; + __le32 sys_msi_address_low; + __le32 sys_msi_address_high; + __le32 sys_msi_data; +}; + +struct rpmi_sysmsi_set_msi_target_rx { + __le32 status; +}; + +struct rpmi_sysmsi_priv { + struct device *dev; + struct mbox_client client; + struct mbox_chan *chan; + u32 nr_irqs; + u32 gsi_base; +}; + +static int rpmi_sysmsi_get_num_msi(struct rpmi_sysmsi_priv *priv) +{ + struct rpmi_sysmsi_get_attrs_rx rx; + struct rpmi_mbox_message msg; + int ret; + + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_GET_ATTRIBUTES, + NULL, 0, &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return le32_to_cpu(rx.sys_num_msi); +} + +static int rpmi_sysmsi_set_msi_state(struct rpmi_sysmsi_priv *priv, + u32 sys_msi_index, u32 sys_msi_state) +{ + struct rpmi_sysmsi_set_msi_state_tx tx; + struct rpmi_sysmsi_set_msi_state_rx rx; + struct rpmi_mbox_message msg; + int ret; + + tx.sys_msi_index =3D cpu_to_le32(sys_msi_index); + tx.sys_msi_state =3D cpu_to_le32(sys_msi_state); + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_STATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static int rpmi_sysmsi_set_msi_target(struct rpmi_sysmsi_priv *priv, + u32 sys_msi_index, struct msi_msg *m) +{ + struct rpmi_sysmsi_set_msi_target_tx tx; + struct rpmi_sysmsi_set_msi_target_rx rx; + struct rpmi_mbox_message msg; + int ret; + + tx.sys_msi_index =3D cpu_to_le32(sys_msi_index); + tx.sys_msi_address_low =3D cpu_to_le32(m->address_lo); + tx.sys_msi_address_high =3D cpu_to_le32(m->address_hi); + tx.sys_msi_data =3D cpu_to_le32(m->data); + rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_TARGET, + &tx, sizeof(tx), &rx, sizeof(rx)); + ret =3D rpmi_mbox_send_message(priv->chan, &msg); + if (ret) + return ret; + if (rx.status) + return rpmi_to_linux_error(le32_to_cpu(rx.status)); + + return 0; +} + +static void rpmi_sysmsi_irq_mask(struct irq_data *d) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + int ret; + + ret =3D rpmi_sysmsi_set_msi_state(priv, irqd_to_hwirq(d), 0); + if (ret) { + dev_warn(priv->dev, "Failed to mask hwirq %lu (error %d)\n", + irqd_to_hwirq(d), ret); + } + irq_chip_mask_parent(d); +} + +static void rpmi_sysmsi_irq_unmask(struct irq_data *d) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + int ret; + + irq_chip_unmask_parent(d); + ret =3D rpmi_sysmsi_set_msi_state(priv, irqd_to_hwirq(d), RPMI_SYSMSI_MSI= _STATE_ENABLE); + if (ret) { + dev_warn(priv->dev, "Failed to unmask hwirq %lu (error %d)\n", + irqd_to_hwirq(d), ret); + } +} + +static void rpmi_sysmsi_write_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct rpmi_sysmsi_priv *priv =3D irq_data_get_irq_chip_data(d); + int ret; + + /* For zeroed MSI, do nothing as of now */ + if (!msg->address_hi && !msg->address_lo && !msg->data) + return; + + ret =3D rpmi_sysmsi_set_msi_target(priv, irqd_to_hwirq(d), msg); + if (ret) { + dev_warn(priv->dev, "Failed to set target for hwirq %lu (error %d)\n", + irqd_to_hwirq(d), ret); + } +} + +static void rpmi_sysmsi_set_desc(msi_alloc_info_t *arg, struct msi_desc *d= esc) +{ + arg->desc =3D desc; + arg->hwirq =3D (u32)desc->data.icookie.value; +} + +static int rpmi_sysmsi_translate(struct irq_domain *d, struct irq_fwspec *= fwspec, + unsigned long *hwirq, unsigned int *type) +{ + struct msi_domain_info *info =3D d->host_data; + struct rpmi_sysmsi_priv *priv =3D info->data; + + if (WARN_ON(fwspec->param_count < 1)) + return -EINVAL; + + /* For DT, gsi_base is always zero. */ + *hwirq =3D fwspec->param[0] - priv->gsi_base; + *type =3D IRQ_TYPE_NONE; + return 0; +} + +static const struct msi_domain_template rpmi_sysmsi_template =3D { + .chip =3D { + .name =3D "RPMI-SYSMSI", + .irq_mask =3D rpmi_sysmsi_irq_mask, + .irq_unmask =3D rpmi_sysmsi_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_write_msi_msg =3D rpmi_sysmsi_write_msg, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, + }, + + .ops =3D { + .set_desc =3D rpmi_sysmsi_set_desc, + .msi_translate =3D rpmi_sysmsi_translate, + }, + + .info =3D { + .bus_token =3D DOMAIN_BUS_WIRED_TO_MSI, + .flags =3D MSI_FLAG_USE_DEV_FWNODE, + .handler =3D handle_simple_irq, + .handler_name =3D "simple", + }, +}; + +static int rpmi_sysmsi_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rpmi_sysmsi_priv *priv; + int rc; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev =3D dev; + platform_set_drvdata(pdev, priv); + + /* Setup mailbox client */ + priv->client.dev =3D priv->dev; + priv->client.rx_callback =3D NULL; + priv->client.tx_block =3D false; + priv->client.knows_txdone =3D true; + priv->client.tx_tout =3D 0; + + /* Request mailbox channel */ + priv->chan =3D mbox_request_channel(&priv->client, 0); + if (IS_ERR(priv->chan)) + return PTR_ERR(priv->chan); + + /* Get number of system MSIs */ + rc =3D rpmi_sysmsi_get_num_msi(priv); + if (rc < 1) { + mbox_free_channel(priv->chan); + if (rc) + return dev_err_probe(dev, rc, "Failed to get number of system MSIs\n"); + else + return dev_err_probe(dev, -ENODEV, "No system MSIs found\n"); + } + priv->nr_irqs =3D rc; + + /* Set the device MSI domain if not available */ + if (!dev_get_msi_domain(dev)) { + /* + * The device MSI domain for OF devices is only set at the + * time of populating/creating OF device. If the device MSI + * domain is discovered later after the OF device is created + * then we need to set it explicitly before using any platform + * MSI functions. + */ + if (is_of_node(dev_fwnode(dev))) + of_msi_configure(dev, to_of_node(dev_fwnode(dev))); + + if (!dev_get_msi_domain(dev)) { + mbox_free_channel(priv->chan); + return -EPROBE_DEFER; + } + } + + if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, + &rpmi_sysmsi_template, + priv->nr_irqs, priv, priv)) { + mbox_free_channel(priv->chan); + return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n"); + } + + dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs); + return 0; +} + +static const struct of_device_id rpmi_sysmsi_match[] =3D { + { .compatible =3D "riscv,rpmi-system-msi" }, + {} +}; + +static struct platform_driver rpmi_sysmsi_driver =3D { + .driver =3D { + .name =3D "rpmi-sysmsi", + .of_match_table =3D rpmi_sysmsi_match, + }, + .probe =3D rpmi_sysmsi_probe, +}; +builtin_platform_driver(rpmi_sysmsi_driver); diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h index 18b606e0023c..90eacb37fdd8 100644 --- a/include/linux/mailbox/riscv-rpmi-message.h +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -88,6 +88,7 @@ static inline int rpmi_to_linux_error(int rpmi_error) } =20 /* RPMI service group IDs */ +#define RPMI_SRVGRP_SYSTEM_MSI 0x00002 #define RPMI_SRVGRP_CLOCK 0x00008 =20 /* RPMI clock service IDs */ @@ -103,6 +104,18 @@ enum rpmi_clock_service_id { RPMI_CLK_SRV_ID_MAX_COUNT }; =20 +/* RPMI system MSI service IDs */ +enum rpmi_sysmsi_service_id { + RPMI_SYSMSI_SRV_ENABLE_NOTIFICATION =3D 0x01, + RPMI_SYSMSI_SRV_GET_ATTRIBUTES =3D 0x02, + RPMI_SYSMSI_SRV_GET_MSI_ATTRIBUTES =3D 0x03, + RPMI_SYSMSI_SRV_SET_MSI_STATE =3D 0x04, + RPMI_SYSMSI_SRV_GET_MSI_STATE =3D 0x05, + RPMI_SYSMSI_SRV_SET_MSI_TARGET =3D 0x06, + RPMI_SYSMSI_SRV_GET_MSI_TARGET =3D 0x07, + RPMI_SYSMSI_SRV_ID_MAX_COUNT +}; + /* RPMI linux mailbox attribute IDs */ enum rpmi_mbox_attribute_id { RPMI_MBOX_ATTR_SPEC_VERSION =3D 0, --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55ECD1EB1BF for ; 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Sun, 25 May 2025 01:49:20 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:49:20 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Date: Sun, 25 May 2025 14:17:01 +0530 Message-ID: <20250525084710.1665648-15-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently acpi_fwnode_get_reference_args() calls the public function __acpi_node_get_property_reference() which ignores the nargs_prop parameter. To fix this, make __acpi_node_get_property_reference() to call the static acpi_fwnode_get_reference() so that callers of fwnode_get_reference_args() can still pass a valid property name to fetch the number of arguments. Signed-off-by: Sunil V L --- drivers/acpi/property.c | 101 ++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 51 deletions(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index 436019d96027..d4863746fb11 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -882,45 +882,10 @@ static struct fwnode_handle *acpi_parse_string_ref(co= nst struct fwnode_handle *f return &dn->fwnode; } =20 -/** - * __acpi_node_get_property_reference - returns handle to the referenced o= bject - * @fwnode: Firmware node to get the property from - * @propname: Name of the property - * @index: Index of the reference to return - * @num_args: Maximum number of arguments after each reference - * @args: Location to store the returned reference with optional arguments - * (may be NULL) - * - * Find property with @name, verifify that it is a package containing at l= east - * one object reference and if so, store the ACPI device object pointer to= the - * target object in @args->adev. If the reference includes arguments, sto= re - * them in the @args->args[] array. - * - * If there's more than one reference in the property value package, @inde= x is - * used to select the one to return. - * - * It is possible to leave holes in the property value set like in the - * example below: - * - * Package () { - * "cs-gpios", - * Package () { - * ^GPIO, 19, 0, 0, - * ^GPIO, 20, 0, 0, - * 0, - * ^GPIO, 21, 0, 0, - * } - * } - * - * Calling this function with index %2 or index %3 return %-ENOENT. If the - * property does not contain any more values %-ENOENT is returned. The NULL - * entry must be single integer and preferably contain value %0. - * - * Return: %0 on success, negative error code on failure. - */ -int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode, - const char *propname, size_t index, size_t num_args, - struct fwnode_reference_args *args) +static int acpi_fwnode_get_reference_args(const struct fwnode_handle *fwno= de, + const char *propname, const char *nargs_prop, + unsigned int args_count, unsigned int index, + struct fwnode_reference_args *args) { const union acpi_object *element, *end; const union acpi_object *obj; @@ -999,7 +964,7 @@ int __acpi_node_get_property_reference(const struct fwn= ode_handle *fwnode, =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, acpi_fwnode_handle(device), - &element, end, num_args); + &element, end, args_count); if (ret < 0) return ret; =20 @@ -1017,7 +982,7 @@ int __acpi_node_get_property_reference(const struct fw= node_handle *fwnode, =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, ref_fwnode, &element, end, - num_args); + args_count); if (ret < 0) return ret; =20 @@ -1039,6 +1004,50 @@ int __acpi_node_get_property_reference(const struct = fwnode_handle *fwnode, =20 return -ENOENT; } + +/** + * __acpi_node_get_property_reference - returns handle to the referenced o= bject + * @fwnode: Firmware node to get the property from + * @propname: Name of the property + * @index: Index of the reference to return + * @num_args: Maximum number of arguments after each reference + * @args: Location to store the returned reference with optional arguments + * (may be NULL) + * + * Find property with @name, verifify that it is a package containing at l= east + * one object reference and if so, store the ACPI device object pointer to= the + * target object in @args->adev. If the reference includes arguments, sto= re + * them in the @args->args[] array. + * + * If there's more than one reference in the property value package, @inde= x is + * used to select the one to return. + * + * It is possible to leave holes in the property value set like in the + * example below: + * + * Package () { + * "cs-gpios", + * Package () { + * ^GPIO, 19, 0, 0, + * ^GPIO, 20, 0, 0, + * 0, + * ^GPIO, 21, 0, 0, + * } + * } + * + * Calling this function with index %2 or index %3 return %-ENOENT. If the + * property does not contain any more values %-ENOENT is returned. The NULL + * entry must be single integer and preferably contain value %0. + * + * Return: %0 on success, negative error code on failure. + */ +int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode, + const char *propname, size_t index, + size_t num_args, + struct fwnode_reference_args *args) +{ + return acpi_fwnode_get_reference_args(fwnode, propname, NULL, index, num_= args, args); +} EXPORT_SYMBOL_GPL(__acpi_node_get_property_reference); =20 static int acpi_data_prop_read_single(const struct acpi_device_data *data, @@ -1558,16 +1567,6 @@ acpi_fwnode_property_read_string_array(const struct = fwnode_handle *fwnode, val, nval); } =20 -static int -acpi_fwnode_get_reference_args(const struct fwnode_handle *fwnode, - const char *prop, const char *nargs_prop, - unsigned int args_count, unsigned int index, - struct fwnode_reference_args *args) -{ - return __acpi_node_get_property_reference(fwnode, prop, index, - args_count, args); -} - static const char *acpi_fwnode_get_name(const struct fwnode_handle *fwnode) { const struct acpi_device *adev; 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Sun, 25 May 2025 01:49:27 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 15/23] ACPI: property: Add support for cells property Date: Sun, 25 May 2025 14:17:02 +0530 Message-ID: <20250525084710.1665648-16-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently, ACPI doesn't support cells property when fwnode_property_get_reference_args() is called. ACPI always expects the number of arguments to be passed. However, the above mentioned call being a common interface for OF and ACPI, it is better to have single calling convention which works for both. Hence, add support for cells property on the reference device to get the number of arguments dynamically. Signed-off-by: Sunil V L --- drivers/acpi/property.c | 22 ++++++++++++++++++++++ drivers/base/property.c | 2 +- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index d4863746fb11..c9c3d6920326 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -882,6 +882,20 @@ static struct fwnode_handle *acpi_parse_string_ref(con= st struct fwnode_handle *f return &dn->fwnode; } =20 +static unsigned int acpi_fwnode_get_args_count(const struct acpi_device *d= evice, + const char *nargs_prop) +{ + const union acpi_object *obj; + + if (!nargs_prop) + return 0; + + if (acpi_dev_get_property(device, nargs_prop, ACPI_TYPE_INTEGER, &obj)) + return 0; + + return obj->integer.value; +} + static int acpi_fwnode_get_reference_args(const struct fwnode_handle *fwno= de, const char *propname, const char *nargs_prop, unsigned int args_count, unsigned int index, @@ -960,6 +974,9 @@ static int acpi_fwnode_get_reference_args(const struct = fwnode_handle *fwnode, if (!device) return -EINVAL; =20 + if (nargs_prop) + args_count =3D acpi_fwnode_get_args_count(device, nargs_prop); + element++; =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, @@ -978,6 +995,11 @@ static int acpi_fwnode_get_reference_args(const struct= fwnode_handle *fwnode, if (!ref_fwnode) return -EINVAL; =20 + if (nargs_prop) { + device =3D to_acpi_device_node(ref_fwnode); + args_count =3D acpi_fwnode_get_args_count(device, nargs_prop); + } + element++; =20 ret =3D acpi_get_ref_args(idx =3D=3D index ? args : NULL, diff --git a/drivers/base/property.c b/drivers/base/property.c index c1392743df9c..172dfb950328 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -578,7 +578,7 @@ EXPORT_SYMBOL_GPL(fwnode_property_match_property_string= ); * @prop: The name of the property * @nargs_prop: The name of the property telling the number of * arguments in the referred node. NULL if @nargs is known, - * otherwise @nargs is ignored. Only relevant on OF. + * otherwise @nargs is ignored. * @nargs: Number of arguments. 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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 16/23] ACPI: scan: Update honor list for RPMI System MSI Date: Sun, 25 May 2025 14:17:03 +0530 Message-ID: <20250525084710.1665648-17-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L The RPMI System MSI interrupt controller (just like PLIC and APLIC) needs to probed prior to devices like GED which use interrupts provided by it. Also, it has dependency on the SBI MPXY mailbox device. Add HIDs of RPMI System MSI and SBI MPXY mailbox devices to the honor list so that those dependencies are handled. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/acpi/scan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index fb1fe9f3b1a3..54181b03b345 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -858,6 +858,8 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ + "RSCV0005", /* RISC-V SBI MPXY MBOX */ + "RSCV0006", /* RISC-V RPMI SYSMSI */ "PNP0C0F", /* PCI Link Device */ NULL }; --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADC071E1A20 for ; Sun, 25 May 2025 08:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order Date: Sun, 25 May 2025 14:17:04 +0530 Message-ID: <20250525084710.1665648-18-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Currently, the interrupt controller list is created without any order. Create the list sorted with the GSI base of the interrupt controllers. Signed-off-by: Sunil V L --- drivers/acpi/riscv/irq.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index cced960c2aef..95b4d7574ce3 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -115,7 +115,7 @@ struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 = gsi) static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, u32 id, u32 type) { - struct riscv_ext_intc_list *ext_intc_element; + struct riscv_ext_intc_list *ext_intc_element, *node; =20 ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); if (!ext_intc_element) @@ -125,7 +125,17 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi= _base, u32 nr_irqs, u32 nr ext_intc_element->nr_irqs =3D nr_irqs; ext_intc_element->nr_idcs =3D nr_idcs; ext_intc_element->id =3D id; - list_add_tail(&ext_intc_element->list, &ext_intc_list); + if (list_empty(&ext_intc_list)) { + list_add(&ext_intc_element->list, &ext_intc_list); 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Sun, 25 May 2025 01:49:52 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.49.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:49:52 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 18/23] ACPI: RISC-V: Add support to update gsi range Date: Sun, 25 May 2025 14:17:05 +0530 Message-ID: <20250525084710.1665648-19-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Some RISC-V interrupt controllers like RPMI based system MSI interrupt controllers do not have MADT entry defined. These interrupt controllers exist only in the namespace. ACPI spec defines _GSB method to get the GSI base of the interrupt controller, However, there is no such standard method to get the GSI range. To support such interrupt controllers, set the GSI range of such interrupt controllers to non-overlapping range and provide API for interrupt controller driver to update it with proper value. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 5 +++++ drivers/acpi/riscv/irq.c | 38 ++++++++++++++++++++++++++++++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 7b038f3b7cb0..2caf049f09c8 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -40,6 +40,7 @@ unsigned long acpi_rintc_ext_parent_to_hartid(unsigned in= t plic_id, unsigned int unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id); unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned in= t ctxt_idx); int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res); +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs); =20 #else static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, @@ -74,6 +75,10 @@ static inline int __init acpi_rintc_get_imsic_mmio_info(= u32 index, struct resour return 0; } =20 +static inline int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs) +{ + return -ENODEV; +} #endif /* CONFIG_ACPI */ =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 95b4d7574ce3..c881cf037f0a 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -10,6 +10,8 @@ =20 #include "init.h" =20 +#define RISCV_ACPI_INTC_FLAG_PENDING BIT(0) + struct riscv_ext_intc_list { acpi_handle handle; u32 gsi_base; @@ -17,6 +19,7 @@ struct riscv_ext_intc_list { u32 nr_idcs; u32 id; u32 type; + u32 flag; struct list_head list; }; =20 @@ -69,6 +72,22 @@ static acpi_status riscv_acpi_update_gsi_handle(u32 gsi_= base, acpi_handle handle return AE_NOT_FOUND; } =20 +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs) +{ + struct riscv_ext_intc_list *ext_intc_element; + + list_for_each_entry(ext_intc_element, &ext_intc_list, list) { + if (gsi_base =3D=3D ext_intc_element->gsi_base && + (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) { + ext_intc_element->nr_irqs =3D nr_irqs; + ext_intc_element->flag &=3D ~RISCV_ACPI_INTC_FLAG_PENDING; + return 0; + } + } + + return -ENODEV; +} + int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs) { @@ -115,14 +134,22 @@ struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u3= 2 gsi) static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, u32 id, u32 type) { - struct riscv_ext_intc_list *ext_intc_element, *node; + struct riscv_ext_intc_list *ext_intc_element, *node, *prev; =20 ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); if (!ext_intc_element) return -ENOMEM; =20 ext_intc_element->gsi_base =3D gsi_base; - ext_intc_element->nr_irqs =3D nr_irqs; + + /* If nr_irqs is zero, indicate it in flag and set to max range possible = */ + if (nr_irqs) { + ext_intc_element->nr_irqs =3D nr_irqs; + } else { + ext_intc_element->flag |=3D RISCV_ACPI_INTC_FLAG_PENDING; + ext_intc_element->nr_irqs =3D U32_MAX - ext_intc_element->gsi_base; + } + ext_intc_element->nr_idcs =3D nr_idcs; ext_intc_element->id =3D id; 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Sun, 25 May 2025 01:50:00 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:50:00 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Date: Sun, 25 May 2025 14:17:06 +0530 Message-ID: <20250525084710.1665648-20-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L The RPMI System MSI device will provide GSIs to downstream devices (such as GED) so add it to the RISC-V GSI to fwnode mapping. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 1 + drivers/acpi/riscv/irq.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 2caf049f09c8..9c9d22f5165e 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -30,6 +30,7 @@ enum riscv_irqchip_type { ACPI_RISCV_IRQCHIP_IMSIC =3D 0x01, ACPI_RISCV_IRQCHIP_PLIC =3D 0x02, ACPI_RISCV_IRQCHIP_APLIC =3D 0x03, + ACPI_RISCV_IRQCHIP_SMSI =3D 0x04, }; =20 int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index c881cf037f0a..f5e91972b5fa 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -173,6 +173,33 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi= _base, u32 nr_irqs, u32 nr return 0; } =20 +static acpi_status __init riscv_acpi_create_gsi_map_smsi(acpi_handle handl= e, u32 level, + void *context, void **return_value) +{ + acpi_status status; + u64 gbase; + + if (!acpi_has_method(handle, "_GSB")) { + acpi_handle_err(handle, "_GSB method not found\n"); + return AE_ERROR; + } + + status =3D acpi_evaluate_integer(handle, "_GSB", NULL, &gbase); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to evaluate _GSB method\n"); + return status; + } + + riscv_acpi_register_ext_intc(gbase, 0, 0, 0, ACPI_RISCV_IRQCHIP_SMSI); + status =3D riscv_acpi_update_gsi_handle((u32)gbase, handle); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); + return status; + } + + return AE_OK; +} + static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u3= 2 level, void *context, void **return_value) { @@ -227,6 +254,9 @@ void __init riscv_acpi_init_gsi_mapping(void) =20 if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); + + /* Unlike PLIC/APLIC, SYSMSI doesn't have MADT */ + acpi_get_devices("RSCV0006", riscv_acpi_create_gsi_map_smsi, NULL, NULL); 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Sun, 25 May 2025 01:50:08 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Date: Sun, 25 May 2025 14:17:07 +0530 Message-ID: <20250525084710.1665648-21-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Add ACPI support for the RISC-V SBI message proxy (MPXY) based mailbox driver. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/mailbox/riscv-sbi-mpxy-mbox.c | 28 +++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/riscv-sbi-mpxy-mbox.c b/drivers/mailbox/riscv-= sbi-mpxy-mbox.c index 121ee5fd3d0d..3d71af6321c3 100644 --- a/drivers/mailbox/riscv-sbi-mpxy-mbox.c +++ b/drivers/mailbox/riscv-sbi-mpxy-mbox.c @@ -6,9 +6,11 @@ */ =20 #include +#include #include #include #include +#include #include #include #include @@ -767,6 +769,7 @@ static int mpxy_mbox_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct mpxy_mbox_channel *mchan; + struct irq_domain *msi_domain; struct mpxy_mbox *mbox; int i, msi_idx, rc; u32 *channel_ids; @@ -892,6 +895,8 @@ static int mpxy_mbox_probe(struct platform_device *pdev) =20 /* Set the MSI domain if not available */ if (!dev_get_msi_domain(dev)) { + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + /* * The device MSI domain for OF devices is only set at the * time of populating/creating OF device. If the device MSI @@ -899,8 +904,13 @@ static int mpxy_mbox_probe(struct platform_device *pde= v) * then we need to set it explicitly before using any platform * MSI functions. */ - if (is_of_node(dev_fwnode(dev))) - of_msi_configure(dev, to_of_node(dev_fwnode(dev))); + if (is_of_node(fwnode)) { + of_msi_configure(dev, to_of_node(fwnode)); + } else if (is_acpi_device_node(fwnode)) { + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + dev_set_msi_domain(dev, msi_domain); + } } =20 /* Setup MSIs for mailbox (if required) */ @@ -945,6 +955,13 @@ static int mpxy_mbox_probe(struct platform_device *pde= v) return rc; } =20 +#ifdef CONFIG_ACPI + struct acpi_device *adev =3D ACPI_COMPANION(dev); + + if (adev) + acpi_dev_clear_dependencies(adev); +#endif + dev_info(dev, "mailbox registered with %d channels\n", mbox->channel_count); return 0; @@ -964,10 +981,17 @@ static const struct of_device_id mpxy_mbox_of_match[]= =3D { }; MODULE_DEVICE_TABLE(of, mpxy_mbox_of_match); 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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 21/23] irqchip/riscv-rpmi-sysmsi: Add ACPI support Date: Sun, 25 May 2025 14:17:08 +0530 Message-ID: <20250525084710.1665648-22-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sunil V L Add ACPI support for the RISC-V RPMI system MSI based irqchip driver. Signed-off-by: Sunil V L Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-riscv-rpmi-sysmsi.c | 48 ++++++++++++++++++++++--- 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 83700fc2ddc9..132e56a596fc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -614,7 +614,7 @@ config RISCV_IMSIC =20 config RISCV_RPMI_SYSMSI bool - depends on MAILBOX + depends on RISCV && MAILBOX select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ default RISCV diff --git a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c b/drivers/irqchip/irq-= riscv-rpmi-sysmsi.c index d7b19fb7bf4e..6d27c036928a 100644 --- a/drivers/irqchip/irq-riscv-rpmi-sysmsi.c +++ b/drivers/irqchip/irq-riscv-rpmi-sysmsi.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2025 Ventana Micro Systems Inc. */ =20 +#include #include #include #include +#include #include #include #include @@ -209,6 +211,9 @@ static int rpmi_sysmsi_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct rpmi_sysmsi_priv *priv; + struct irq_domain *msi_domain; + struct fwnode_handle *fwnode; + u32 id; int rc; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -240,6 +245,22 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) } priv->nr_irqs =3D rc; =20 + fwnode =3D dev_fwnode(dev); + if (is_acpi_node(fwnode)) { + u32 nr_irqs; + + rc =3D riscv_acpi_get_gsi_info(fwnode, &priv->gsi_base, &id, + &nr_irqs, NULL); + if (rc) { + dev_err(dev, "failed to find GSI mapping\n"); + return rc; + } + + /* Update with actual GSI range */ + if (nr_irqs !=3D priv->nr_irqs) + riscv_acpi_update_gsi_range(priv->gsi_base, priv->nr_irqs); + } + /* Set the device MSI domain if not available */ if (!dev_get_msi_domain(dev)) { /* @@ -249,8 +270,13 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) * then we need to set it explicitly before using any platform * MSI functions. */ - if (is_of_node(dev_fwnode(dev))) - of_msi_configure(dev, to_of_node(dev_fwnode(dev))); + if (is_of_node(fwnode)) { + of_msi_configure(dev, to_of_node(fwnode)); + } else if (is_acpi_device_node(fwnode)) { + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + dev_set_msi_domain(dev, msi_domain); + } =20 if (!dev_get_msi_domain(dev)) { mbox_free_channel(priv->chan); @@ -265,6 +291,13 @@ static int rpmi_sysmsi_probe(struct platform_device *p= dev) return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n"); } =20 +#ifdef CONFIG_ACPI + struct acpi_device *adev =3D ACPI_COMPANION(dev); + + if (adev) + acpi_dev_clear_dependencies(adev); +#endif + dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs); return 0; } @@ -274,10 +307,17 @@ static const struct of_device_id rpmi_sysmsi_match[] = =3D { {} }; =20 +static const struct acpi_device_id acpi_rpmi_sysmsi_match[] =3D { + { "RSCV0006" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, acpi_rpmi_sysmsi_match); + static struct platform_driver rpmi_sysmsi_driver =3D { .driver =3D { - .name =3D "rpmi-sysmsi", - .of_match_table =3D rpmi_sysmsi_match, + .name =3D "rpmi-sysmsi", + .of_match_table =3D rpmi_sysmsi_match, + .acpi_match_table =3D acpi_rpmi_sysmsi_match, }, .probe =3D rpmi_sysmsi_probe, }; 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Sun, 25 May 2025 01:50:24 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Date: Sun, 25 May 2025 14:17:09 +0530 Message-ID: <20250525084710.1665648-23-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The GPIO keyboard and event device can be used to receive graceful shutdown or reboot input keys so let us enable it by default for RV64 (just like ARM64). Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 3c8e16d71e17..6aa330f4b67f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -141,6 +141,8 @@ CONFIG_MICREL_PHY=3Dy CONFIG_MICROSEMI_PHY=3Dy CONFIG_MOTORCOMM_PHY=3Dy CONFIG_INPUT_MOUSEDEV=3Dy +CONFIG_INPUT_EVDEV=3Dy +CONFIG_KEYBOARD_GPIO=3Dy CONFIG_KEYBOARD_SUN4I_LRADC=3Dm CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy --=20 2.43.0 From nobody Sat Feb 7 14:06:25 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4498D1F0E50 for ; Sun, 25 May 2025 08:50:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; 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Sun, 25 May 2025 01:50:33 -0700 (PDT) Received: from localhost.localdomain ([122.171.22.180]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf6dd83sm15250627a12.18.2025.05.25.01.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:50:32 -0700 (PDT) From: Anup Patel To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Thomas Gleixner , "Rafael J . Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Date: Sun, 25 May 2025 14:17:10 +0530 Message-ID: <20250525084710.1665648-24-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525084710.1665648-1-apatel@ventanamicro.com> References: <20250525084710.1665648-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Rahul and myself as maintainers for RISC-V RPMI and MPXY drivers. Signed-off-by: Anup Patel --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d48dd6726fe6..f09b865a697e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20963,6 +20963,21 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V RPMI AND MPXY DRIVERS +M: Rahul Pathak +M: Anup Patel +L: linux-riscv@lists.infradead.org +F: Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml +F: Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-= system-msi.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-syste= m-msi.yaml +F: Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml +F: Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml +F: drivers/clk/clk-rpmi.c +F: drivers/irqchip/irq-riscv-rpmi-sysmsi.c +F: drivers/mailbox/riscv-sbi-mpxy-mbox.c +F: include/linux/mailbox/riscv-rpmi-message.h + RISC-V SPACEMIT SoC Support M: Yixun Lan L: linux-riscv@lists.infradead.org --=20 2.43.0