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Sun, 25 May 2025 01:28:22 -0700 (PDT) Received: from [127.0.1.1] ([221.239.193.52]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-234221f8b06sm18716465ad.161.2025.05.25.01.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 01:28:21 -0700 (PDT) From: Stephen Eta Zhou Date: Sun, 25 May 2025 16:28:16 +0800 Subject: [PATCH v5] clocksource: timer-sp804: Fix read_current_timer() issue when clock source is not registered Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250525-sp804-fix-read_current_timer-v5-1-49b64c77a7a6@gmail.com> X-B4-Tracking: v=1; b=H4sIAJ/UMmgC/32OywrCMBREf6VkbSRpEhtc+R9SSkyv7QX78CYtS um/GyvizuUZhjmzsACEENgxWxjBjAGHPoHZZcy3rm+AY52Y5SI3QkvJw2iF5ld8cAJXV34igj5 WETsgLn3hjdPa+oNnaWIkSM1t/lx+mOA+JUv8hS2GONBzuzCrd/q16f+2WXHJjboosKIupFWnp nN42/uhY+W6ri9MSxEC3QAAAA== X-Change-ID: 20250411-sp804-fix-read_current_timer-1c7c5a448c6c To: Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, Stephen Eta Zhou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748161700; l=3828; i=stephen.eta.zhou@gmail.com; s=20250411; h=from:subject:message-id; bh=ejp4wm01HVYCSmFMOQbnLtRgrnY0ZvRQ2FFm4BrYP8g=; b=JJm8AQYEpTYdo9BUZcaRnE0Z522bzD8TiV7Q7vliXE/f9VVK5jkbCgd+XZ8sZ4DH8p9qlHubh ESx2+GxcaVaB081u7O9Y5gajnjzt9YGSwzoDKDEbIVaVqKQhOr5ycGe X-Developer-Key: i=stephen.eta.zhou@gmail.com; a=ed25519; pk=JMRa8Po5ykvp3C9lVKJCeZ9BuRW6xWwa0Sj4KqnLoOk= Register a valid read_current_timer() function for the SP804 timer on ARM32. On ARM32 platforms, when the SP804 timer is selected as the clocksource, the driver does not register a valid read_current_timer() function. As a result, features that rely on this API=E2=80=94such as rdseed=E2=80=94= consistently return incorrect values. To fix this, a delay_timer structure is registered during the SP804 driver's initialization. The read_current_timer() function is implemented using the existing sp804_read() logic, and the timer frequency is reused from the already-initialized clocksource. Signed-off-by: Stephen Eta Zhou --- Changes in v4: - Dropped redundant `delay.freq =3D rate;` assignment in `sp804_clocksource= _and_sched_clock_init()` - Dropped redundant `delay.read_current_timer` and `register_current_timer_= delay()` lines in `sp804_of_init()` - No functional changes to the driver logic; these lines were unnecessary a= s per Daniel's feedback. - Link to v3: https://lore.kernel.org/all/20250414-sp804-fix-read_current_t= imer-v3-1-53b3e80d7183@gmail.com Changes in v3: - Updated the commit message for clarity and structure - Link to v2: https://lore.kernel.org/all/BYAPR12MB3205D7A2BAA2712C89E03C4F= D5D42@BYAPR12MB3205.namprd12.prod.outlook.com Changes in v2: - Added static keyword to struct delay_timer delay - Integrate sp804_read_delay_timer_read and struct delay_timer delay together - I moved the acquisition of delay.freq to sp804_clocksource_and_sched_clock_init. sp804_clocksource_and_sched_clock_init has already acquired and judged freq, so I can use it directly, and in this way I don=E2=80=99t need to consider whether to use clk1 or clk2, which can ensure that the clock source is available and reliable. - Added detailed description information in Commit - Link to v1: https://lore.kernel.org/all/BYAPR12MB3205C9C87EB560CA0CC4984B= D5FB2@BYAPR12MB3205.namprd12.prod.outlook.com --- drivers/clocksource/timer-sp804.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-= sp804.c index cd1916c0532507fb3ce7a11bfab4815906e326d5..e82a95ea472478ae096b2bf7abe= a0d65a7bca480 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -21,6 +21,10 @@ #include #include =20 +#ifdef CONFIG_ARM +#include +#endif + #include "timer-sp.h" =20 /* Hisilicon 64-bit timer(a variant of ARM SP804) */ @@ -102,6 +106,23 @@ static u64 notrace sp804_read(void) return ~readl_relaxed(sched_clkevt->value); } =20 +#ifdef CONFIG_ARM +static struct delay_timer delay; +static unsigned long sp804_read_delay_timer_read(void) +{ + return sp804_read(); +} + +static void sp804_register_delay_timer(int freq) +{ + delay.freq =3D freq; + delay.read_current_timer =3D sp804_read_delay_timer_read; + register_current_timer_delay(&delay); +} +#else +static inline void sp804_register_delay_timer(int freq) {} +#endif + static int __init sp804_clocksource_and_sched_clock_init(void __iomem *bas= e, const char *name, struct clk *clk, @@ -114,6 +135,8 @@ static int __init sp804_clocksource_and_sched_clock_ini= t(void __iomem *base, if (rate < 0) return -EINVAL; =20 + sp804_register_delay_timer(rate); + clkevt =3D sp804_clkevt_get(base); =20 writel(0, clkevt->ctrl); @@ -318,6 +341,7 @@ static int __init sp804_of_init(struct device_node *np,= struct sp804_timer *time if (ret) goto err; } + initialized =3D true; =20 return 0; --- base-commit: 7ee983c850b40043ac4751836fbd9a2b4d0c5937 change-id: 20250411-sp804-fix-read_current_timer-1c7c5a448c6c Best regards, --=20 Stephen Eta Zhou