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[2a02:9142:4580:a00::8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f38142b8sm147078285e9.30.2025.05.23.11.14.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:14:52 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: linux-mtd@lists.infradead.org, dregan@broadcom.com, bcm-kernel-feedback-list@broadcom.com, florian.fainelli@broadcom.com, rafal@milecki.pl, computersforpeace@gmail.com, kamal.dasu@broadcom.com, dan.beygelman@broadcom.com, william.zhang@broadcom.com, frieder.schrempf@kontron.de, linux-kernel@vger.kernel.org, vigneshr@ti.com, richard@nod.at, bbrezillon@kernel.org, kdasu.kdev@gmail.com, jaimeliao.tw@gmail.com, kilobyte@angband.pl, jonas.gorski@gmail.com, dgcbueu@gmail.com Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Subject: [PATCH v6] mtd: rawnand: brcmnand: legacy exec_op implementation Date: Fri, 23 May 2025 20:14:48 +0200 Message-Id: <20250523181448.1181256-1-noltari@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Commit 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") removed legacy interface functions, breaking < v5.0 controllers support. In order to fix older controllers we need to add an alternative exec_op implementation which doesn't rely on low level registers. Fixes: 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas Reviewed-by: David Regan Reviewed-by: Florian Fainelli Reviewed-by: William Zhang --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 223 ++++++++++++++++++++++- 1 file changed, 216 insertions(+), 7 deletions(-) v6: add changes requested by David Regan: - add braces in flash_cache for loop. v5: add changes requested by Miqu=C3=A8l Raynal: - Mention and explain legacy in native_cmd_conv. - EOPNOTSUPP instead of EINVAL for instr->type else. - Implement missing check_only functionality. v4: add changes requested by Jonas Gorski: - Add missing breaks in brcmnand_exec_instructions_legacy. - Restore missing ret assignment in brcmnand_exec_op. v3: add changes requested by Florian and other improvements: - Add associative array for native command conversion. - Add function pointer to brcmnand_controller for exec_instr functionality. - Fix CMD_BLOCK_ERASE address. - Drop NAND_CMD_READOOB support. v2: multiple improvements: - Use proper native commands for checks. - Fix NAND_CMD_PARAM/NAND_CMD_RNDOUT addr calculation. - Remove host->last_addr usage. - Remove sector_size_1k since it only applies to v5.0+ controllers. - Remove brcmnand_wp since it doesn't exist for < v5.0 controllers. - Use j instead of i for flash_cache loop. diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/ra= w/brcmnand/brcmnand.c index b43281b8204f6..610e8557acafe 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -65,6 +65,7 @@ module_param(wp_on, int, 0444); #define CMD_PARAMETER_READ 0x0e #define CMD_PARAMETER_CHANGE_COL 0x0f #define CMD_LOW_LEVEL_OP 0x10 +#define CMD_NOT_SUPPORTED 0xff =20 struct brcm_nand_dma_desc { u32 next_desc; @@ -199,6 +200,30 @@ static const u16 flash_dma_regs_v4[] =3D { [FLASH_DMA_CURRENT_DESC_EXT] =3D 0x34, }; =20 +/* Native command conversion for legacy controllers (< v5.0) */ +static const u8 native_cmd_conv[] =3D { + [NAND_CMD_READ0] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READ1] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_RNDOUT] =3D CMD_PARAMETER_CHANGE_COL, + [NAND_CMD_PAGEPROG] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READOOB] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_ERASE1] =3D CMD_BLOCK_ERASE, + [NAND_CMD_STATUS] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_SEQIN] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_RNDIN] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READID] =3D CMD_DEVICE_ID_READ, + [NAND_CMD_ERASE2] =3D CMD_NULL, + [NAND_CMD_PARAM] =3D CMD_PARAMETER_READ, + [NAND_CMD_GET_FEATURES] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_SET_FEATURES] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_RESET] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READSTART] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READCACHESEQ] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_READCACHEEND] =3D CMD_NOT_SUPPORTED, + [NAND_CMD_RNDOUTSTART] =3D CMD_NULL, + [NAND_CMD_CACHEDPROG] =3D CMD_NOT_SUPPORTED, +}; + /* Controller feature flags */ enum { BRCMNAND_HAS_1K_SECTORS =3D BIT(0), @@ -237,6 +262,12 @@ struct brcmnand_controller { /* List of NAND hosts (one for each chip-select) */ struct list_head host_list; =20 + /* Functions to be called from exec_op */ + int (*check_instr)(struct nand_chip *chip, + const struct nand_operation *op); + int (*exec_instr)(struct nand_chip *chip, + const struct nand_operation *op); + /* EDU info, per-transaction */ const u16 *edu_offsets; void __iomem *edu_base; @@ -2478,18 +2509,191 @@ static int brcmnand_op_is_reset(const struct nand_= operation *op) return 0; } =20 +static int brcmnand_check_instructions(struct nand_chip *chip, + const struct nand_operation *op) +{ + return 0; +} + +static int brcmnand_exec_instructions(struct nand_chip *chip, + const struct nand_operation *op) +{ + struct brcmnand_host *host =3D nand_get_controller_data(chip); + unsigned int i; + int ret =3D 0; + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D brcmnand_exec_instr(host, i, op); + if (ret) + break; + } + + return ret; +} + +static int brcmnand_check_instructions_legacy(struct nand_chip *chip, + const struct nand_operation *op) +{ + const struct nand_op_instr *instr; + unsigned int i; + u8 cmd; + + for (i =3D 0; i < op->ninstrs; i++) { + instr =3D &op->instrs[i]; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + cmd =3D native_cmd_conv[instr->ctx.cmd.opcode]; + if (cmd =3D=3D CMD_NOT_SUPPORTED) + return -EOPNOTSUPP; + break; + case NAND_OP_ADDR_INSTR: + case NAND_OP_DATA_IN_INSTR: + case NAND_OP_WAITRDY_INSTR: + break; + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int brcmnand_exec_instructions_legacy(struct nand_chip *chip, + const struct nand_operation *op) +{ + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct brcmnand_host *host =3D nand_get_controller_data(chip); + struct brcmnand_controller *ctrl =3D host->ctrl; + const struct nand_op_instr *instr; + unsigned int i, j; + u8 cmd =3D CMD_NULL, last_cmd =3D CMD_NULL; + int ret =3D 0; + u64 last_addr; + + for (i =3D 0; i < op->ninstrs; i++) { + instr =3D &op->instrs[i]; + + if (instr->type =3D=3D NAND_OP_CMD_INSTR) { + cmd =3D native_cmd_conv[instr->ctx.cmd.opcode]; + if (cmd =3D=3D CMD_NOT_SUPPORTED) { + dev_err(ctrl->dev, "unsupported cmd=3D%d\n", + instr->ctx.cmd.opcode); + ret =3D -EOPNOTSUPP; + break; + } + } else if (instr->type =3D=3D NAND_OP_ADDR_INSTR) { + u64 addr =3D 0; + + if (cmd =3D=3D CMD_NULL) + continue; + + if (instr->ctx.addr.naddrs > 8) { + dev_err(ctrl->dev, "unsupported naddrs=3D%u\n", + instr->ctx.addr.naddrs); + ret =3D -EOPNOTSUPP; + break; + } + + for (j =3D 0; j < instr->ctx.addr.naddrs; j++) + addr |=3D (instr->ctx.addr.addrs[j]) << (j << 3); + + if (cmd =3D=3D CMD_BLOCK_ERASE) + addr <<=3D chip->page_shift; + else if (cmd =3D=3D CMD_PARAMETER_CHANGE_COL) + addr &=3D ~((u64)(FC_BYTES - 1)); + + brcmnand_set_cmd_addr(mtd, addr); + brcmnand_send_cmd(host, cmd); + last_addr =3D addr; + last_cmd =3D cmd; + cmd =3D CMD_NULL; + brcmnand_waitfunc(chip); + + if (last_cmd =3D=3D CMD_PARAMETER_READ || + last_cmd =3D=3D CMD_PARAMETER_CHANGE_COL) { + /* Copy flash cache word-wise */ + u32 *flash_cache =3D (u32 *)ctrl->flash_cache; + + brcmnand_soc_data_bus_prepare(ctrl->soc, true); + + /* + * Must cache the FLASH_CACHE now, since changes in + * SECTOR_SIZE_1K may invalidate it + */ + for (j =3D 0; j < FC_WORDS; j++) { + /* + * Flash cache is big endian for parameter pages, at + * least on STB SoCs + */ + flash_cache[j] =3D be32_to_cpu(brcmnand_read_fc(ctrl, j)); + } + + brcmnand_soc_data_bus_unprepare(ctrl->soc, true); + } + } else if (instr->type =3D=3D NAND_OP_DATA_IN_INSTR) { + u8 *in =3D instr->ctx.data.buf.in; + + if (last_cmd =3D=3D CMD_DEVICE_ID_READ) { + u32 val; + + if (instr->ctx.data.len > 8) { + dev_err(ctrl->dev, "unsupported len=3D%u\n", + instr->ctx.data.len); + ret =3D -EOPNOTSUPP; + break; + } + + for (j =3D 0; j < instr->ctx.data.len; j++) { + if (j =3D=3D 0) + val =3D brcmnand_read_reg(ctrl, BRCMNAND_ID); + else if (j =3D=3D 4) + val =3D brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT); + + in[j] =3D (val >> (24 - ((j % 4) << 3))) & 0xff; + } + } else if (last_cmd =3D=3D CMD_PARAMETER_READ || + last_cmd =3D=3D CMD_PARAMETER_CHANGE_COL) { + u64 addr; + u32 offs; + + for (j =3D 0; j < instr->ctx.data.len; j++) { + addr =3D last_addr + j; + offs =3D addr & (FC_BYTES - 1); + + if (j > 0 && offs =3D=3D 0) + nand_change_read_column_op(chip, addr, NULL, 0, + false); + + in[j] =3D ctrl->flash_cache[offs]; + } + } + } else if (instr->type =3D=3D NAND_OP_WAITRDY_INSTR) { + ret =3D bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); + if (ret) + break; + } else { + dev_err(ctrl->dev, "unsupported instruction type: %d\n", instr->type); + ret =3D -EOPNOTSUPP; + break; + } + } + + return ret; +} + static int brcmnand_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) { struct brcmnand_host *host =3D nand_get_controller_data(chip); + struct brcmnand_controller *ctrl =3D host->ctrl; struct mtd_info *mtd =3D nand_to_mtd(chip); u8 *status; - unsigned int i; int ret =3D 0; =20 if (check_only) - return 0; + return ctrl->check_instr(chip, op); =20 if (brcmnand_op_is_status(op)) { status =3D op->instrs[1].ctx.data.buf.in; @@ -2513,11 +2717,7 @@ static int brcmnand_exec_op(struct nand_chip *chip, if (op->deassert_wp) brcmnand_wp(mtd, 0); =20 - for (i =3D 0; i < op->ninstrs; i++) { - ret =3D brcmnand_exec_instr(host, i, op); - if (ret) - break; - } + ret =3D ctrl->exec_instr(chip, op); =20 if (op->deassert_wp) brcmnand_wp(mtd, 1); @@ -3130,6 +3330,15 @@ int brcmnand_probe(struct platform_device *pdev, str= uct brcmnand_soc *soc) if (ret) goto err; =20 + /* Only v5.0+ controllers have low level ops support */ + if (ctrl->nand_version >=3D 0x0500) { + ctrl->check_instr =3D brcmnand_check_instructions; + ctrl->exec_instr =3D brcmnand_exec_instructions; + } else { + ctrl->check_instr =3D brcmnand_check_instructions_legacy; + ctrl->exec_instr =3D brcmnand_exec_instructions_legacy; + } + /* * Most chips have this cache at a fixed offset within 'nand' block. * Some must specify this region separately. --=20 2.39.5