From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED7EE22A4FC; Fri, 23 May 2025 10:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997175; cv=none; b=JJAM2l907XvR9enoY9aorLA/XxNpADJHe8vvh5ck8QWiZBPvcA1kMbDiVo3+PZ1uwr1xcwQ/YSrjitloI3RjtHk0ltieVoAP1HmoVtT2JAgDPEEhrxsEm+n/hgt+w+IHLAbyhJyMcqMcE5XzoJK7C2VgkVzDWb7+ZAE7r/qZyPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997175; c=relaxed/simple; bh=R2qt1PgPlfZdW0uCkZD3WsYf2ueDKi37uGThCDgyG14=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pPmRm+5dSz+SVkfYTpSBJ/+tvRI0AGSN7mda/9w3CNNC8+YAOREHL2tC5b5bAAznoLBLlkU7F5p7j4Tnid8KCbKsOa1Kqwj+/Vj6biaiqH/xo6Ux9syXIUazFIFxnYRuqJU9F0S5DEghA5slfGC8Dg1SBSfhMnaFwkThaFwqTXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=co8q+FxF; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="co8q+FxF" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 7314126025; Fri, 23 May 2025 12:46:12 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id e2dD39EOxXH8; Fri, 23 May 2025 12:46:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997171; bh=R2qt1PgPlfZdW0uCkZD3WsYf2ueDKi37uGThCDgyG14=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=co8q+FxFywJ8ydDFnZ/L2TsW4po6DBLilaJclrF8KB4Ry1hXMkizbAYe+FLYdh2+7 ldkP/f96hfZgbcyvLbFvS4OPWqs0xr7mNaLKTUUaYfLb+B653qZZmBLe9/YlBYtyTz YYJ9ztiRoNlbteKJ+pUY/T/iVYtPEP1AD45OhdmBu+GyfecEGSlDPRLwJ+o11B4TnL asgckN3Bv+ygwkmQKyUbqHu1wuC43vhSdLejqnoskQCFAv+Akz7n3YOCWIYAKZlmc6 xrOYtwItJzrQT11koVycgWS0Y4eU8XnjrRT5g/zk+NPQTEuI8bygXmwX2HcA6kBa91 3wYlB5OSRochQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 1/8] dt-bindings: clock: Document Loongson 2K0300 clock controller Date: Fri, 23 May 2025 10:45:45 +0000 Message-ID: <20250523104552.32742-2-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the clock controller shipped in Loongson 2K0300 SoC, which generates various clock signals for SoC peripherals. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/loongson,ls2k0300-clk.yaml | 52 ++++++++++++++++++ .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls2k03= 00-clk.yaml create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.= yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml new file mode 100644 index 000000000000..d96b9d7cb7c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls2k0300-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2K0300 SoC Clock Controller + +maintainers: + - Yao Zi + +description: | + The Loongson 2K0300 clock controller generates various clocks for SoC + peripherals. See include/dt-bindings/clock/loongson,ls2k0300-clk.h for + valid clock IDs. + +properties: + compatible: + const: loongson,ls2k0300-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: External 120MHz reference clock + + clock-names: + items: + - const: ref_120m + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clk: clock-controller@16000400 { + compatible =3D "loongson,ls2k0300-clk"; + reg =3D <0x16000400 0x100>; + clocks =3D <&ref_120m>; + clock-names =3D "ref_120m"; + #clock-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt= -bindings/clock/loongson,ls2k0300-clk.h new file mode 100644 index 000000000000..5e8f7b2f33f2 --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Yao Zi + */ +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ + +/* Derivied from REFCLK */ +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_PLL_NODE 1 +#define LS2K0300_PLL_DDR 2 +#define LS2K0300_PLL_PIX 3 +#define LS2K0300_CLK_THSENS 4 + +/* Derived from PLL_NODE */ +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 + +/* Derived from PLL_DDR */ +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 + +/* Derived from PLL_PIX */ +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 + +/* Derived from CLK_DEV */ +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 + +#define LS2K0300_CLK_GMAC_IN 34 + +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 535E922AE48; Fri, 23 May 2025 10:46:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997179; cv=none; b=ipP8ZMM4+AzdIgbGP9gCtouhOR7hXluQ2SGrT6oz6a46bcgzPmFiSM8pOVArfKbh4XFx7tUwIiErUlEeSKXH2IurW4IGcLChanZmtR1MXjG1z/MQlTFsofg6taBcsgvw1MKMnOJTEpiNOKXbBjYX6T//SjF7KtyfzK+PTlONODo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997179; c=relaxed/simple; bh=aW5yvpNvSkcVrVrORKxyIa2LVFmcbX7kq7M2CNVH9bc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mqwbdjJK5HQ9cp0cmkv9J49JFNSw8324kpTUDgH5nojZ4FzSUnbflbqF/M4vsaUxfEwbBqsh10a677pIv4VrVAxiEL1QEdaN7wRlwMKK+JwV3lWLtoh11zPgb8dtq/AnhxXD/wU8X7u4iG4cxC+vb6HQ45NZXyRtouIHnh546IM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=OHvrrZJZ; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="OHvrrZJZ" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id D200125D81; Fri, 23 May 2025 12:46:16 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id K0yhOC7coVRf; Fri, 23 May 2025 12:46:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997176; bh=aW5yvpNvSkcVrVrORKxyIa2LVFmcbX7kq7M2CNVH9bc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OHvrrZJZFfaJxciP+3f+6DpoXtwHXZUrkGSimt0Q9pnymkyTgGBxPoSbi5JHTXSnk 0r6Gp/6Qm3TN2X6k0gSd/OzuLRyBiYiKaqGi53LusfGn2njXKkYmGe3hnn5y2jIaOT d88GKrFopH6s0Ko1M7Aq8BzsGyiG19UMCsP0s30n42uMC9fgLCGdXqg5YEsDt6w/Zg oTjTghaaYZLduk4ACbmfFiSOqFRaAAPAf6mOodtzuqYJc1kpYIdHgUReNlJ8jcY+bk LuBBIwF5wcTPQPnFna60wfXjiKzo4JheBvE94ulZPeYLAfDkxGaIMAb7y76NHtjOuf W22YnVCF16Y2w== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 2/8] clk: loongson2: Allow specifying clock flags for gate clock Date: Fri, 23 May 2025 10:45:46 +0000 Message-ID: <20250523104552.32742-3-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some gate clocks need to be supplied with flags, e.g., it may be required to specify CLK_IS_CRTICAL for CPU clocks. Add a field to loongson2_clk_board_info for representing clock flags, and specify it when registering gate clocks. A new helper macro, CLK_GATE_FLAGS, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 27e632edd484..cc3fb13e770f 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -50,6 +50,7 @@ struct loongson2_clk_board_info { const char *name; const char *parent_name; unsigned long fixed_rate; + unsigned long flags; u8 reg_offset; u8 div_shift; u8 div_width; @@ -105,6 +106,18 @@ struct loongson2_clk_board_info { .bit_idx =3D _bidx, \ } =20 +#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \ + _flags) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_GATE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .bit_idx =3D _bidx, \ + .flags =3D _flags \ + } + #define CLK_FIXED(_id, _name, _pname, _rate) \ { \ .id =3D _id, \ @@ -332,7 +345,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0, + hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABDBF226D0A; Fri, 23 May 2025 10:47:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997226; cv=none; b=i/oCeR0QxaGi93ZOEFjX+QzJaYK0dneyTcBul+Q3UdU0lPPVQVxP7TStQoroeEKBR2y6IB6h/BJ1tTXuo15JlwF4KTXm0Ib/qlLLD1hCGdIH6kONTgXMg1MSI8SNv4E+j72JdqdTt2OMH3IWDf/TqZMOSaUangbhOmz67i0Rb/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997226; c=relaxed/simple; bh=UelRARJ4L5EQo961j7oIIU5hjPjnKWR1JwdiW487Osg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZZpz0/Ic18AuYNEmIoIyhkUSbLdB9Dyy7F0ColVRPWuV8W3HUmwvt0jOd/YAvrFqJD3tZMeySFBlQko2rFRiPLlvLxh3iMhHEfS7Gr063tKfvDbWnceVLB3m3sErkUZd0lnpPQA//9l6IaKfmh1GRu8BeMlmOLnQW9cBrLG+yQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=CD49Pr7Z; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="CD49Pr7Z" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 203A0259BB; Fri, 23 May 2025 12:47:03 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id cdtLwuN3TYsn; Fri, 23 May 2025 12:47:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997221; bh=UelRARJ4L5EQo961j7oIIU5hjPjnKWR1JwdiW487Osg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=CD49Pr7ZCxTXKrNW7TEz5QaD9tAw6E5drLC8r9TK6pLYqcpvOLiw22agLHj5onGXW iExqOboTeOu2n9w7e9Kzu/amuunt4HmGP4+JOtFslE98fxYZlgVFJ0eGzUusOivxko 1qAJBO1zpa/ZdIIXuUza6wkerri2akjtc2I1BtLeqEBUQPekM9feQV9X3dcRnDlWQz zs9xjDPbZ7c1W7CgyGyLLkrw2oKLwixSu+cPqt1WVloUKDlFuwOjz0ONdWmpfsuM16 9tcg9RTG/5dztVjJuhXkqOh3XGY6WU8cJbh4P/7FP5VXS0rfXTRwhMcUo6h+hLk4kp QW0UJzCVJb2Sw== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 3/8] clk: loongson2: Support scale clocks with an alternative mode Date: Fri, 23 May 2025 10:45:47 +0000 Message-ID: <20250523104552.32742-4-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K1500 ship scale clocks with an alternative mode. There's one mode bit in clock configuration register indicating the operation mode. When mode bit is unset, the scale clock acts the same as previous generation of scale clocks. When it's set, a different equation for calculating result frequency, Fout =3D Fin / (scale + 1), is used. This patch adds frequency calculation support for the scale clock variant. A helper macro, CLK_SCALE_MODE, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index cc3fb13e770f..bba97270376c 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -42,6 +42,7 @@ struct loongson2_clk_data { u8 div_width; u8 mult_shift; u8 mult_width; + u8 bit_idx; }; =20 struct loongson2_clk_board_info { @@ -96,6 +97,19 @@ struct loongson2_clk_board_info { .div_width =3D _dwidth, \ } =20 +#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ + _dshift, _dwidth, _midx) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_SCALE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .bit_idx =3D _midx + 1, \ + } + #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ { \ .id =3D _id, \ @@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = =3D { static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u64 val, mult; + u64 val, scale; + u32 mode =3D 0; struct loongson2_clk_data *clk =3D to_loongson2_clk(hw); =20 val =3D readq(clk->reg); - mult =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + scale =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + + if (clk->bit_idx) + mode =3D val & BIT(clk->bit_idx - 1); =20 - return div_u64((u64)parent_rate * mult, 8); + return mode =3D=3D 0 ? div_u64((u64)parent_rate * scale, 8) : + div_u64((u64)parent_rate, scale); } =20 static const struct clk_ops loongson2_freqscale_recalc_ops =3D { @@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loo= ngson2_clk_provider *clp, clk->div_width =3D cld->div_width; clk->mult_shift =3D cld->mult_shift; clk->mult_width =3D cld->mult_width; + clk->bit_idx =3D cld->bit_idx; clk->hw.init =3D &init; =20 hw =3D &clk->hw; --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C6EF22A4FE; Fri, 23 May 2025 10:47:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997230; cv=none; b=Ly29tv8ySeZfT8b+W4QgHGME5LuWgCE5F8wYweLPehL3UvSDRw0u8LcGnxo+ySQlhV98En4ardzoEXNNexAw8iSn5hVMkiwCsjcWw4a90w9BCi2CgGpEgvfRQ/RqV91gisgwc3qOqcRJUp9LggIHEZfuIqbcnqeq3twb3fgNxi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997230; c=relaxed/simple; bh=hVpvRGbKFKtFx1BRcVBUOZPuHWI/E7Qle7Kn2K+uayU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ElrArThAbMRERAzDlS7v3jMQ7WuIgUVCxU2YXJYQ9D1x/3nRDpWImTPysbAoGxWvNQV4eJ19SB0zPftJtCF9JPQ5WAC4uApJOLtDIMiVRy1aYs/udQvATWYy8dpXtE2HIiSSnr4nw2pGmQTv3FMelbzQhvcouLe0L7ezDSEpzUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=elwaSclK; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="elwaSclK" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B323925D10; Fri, 23 May 2025 12:47:07 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id n-2i_ixPaUTp; Fri, 23 May 2025 12:47:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997226; bh=hVpvRGbKFKtFx1BRcVBUOZPuHWI/E7Qle7Kn2K+uayU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=elwaSclKRUoBAVpmD7afVu+YxmFydtX20NeME3zbM4+f1Y0bzP+0KDrf0R9XE3t4U kDu+MZTnxioVA7nVhzt2TIvqf04E3R9Qw5aUFuQ8Xbaoe8dk1UCRgg0Mmb8AKSXojx dgDaZ9fAhDwyWP+gVb4PIeSPqwLRvPCQKxaYoRRCQcQeRSmJVrI+3VG6YrRKGcPfE+ f3jRIkriHT/E0DQWNE0YNKGx6Q9TGiP0dkNwYw+YYRWaoRR6NRMshU2bZVA2cken1n iEt2FayBf34eI1qSqtyqG47fuHYOwR5N93PQ2goPDmEWVhUosWALEdOiLN2p0GQXV0 PkseRCQzZREwA== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 4/8] clk: loongson2: Allow zero divisors for dividers Date: Fri, 23 May 2025 10:45:48 +0000 Message-ID: <20250523104552.32742-5-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K0500 ship divider clocks which allows zero divisors, in which case the divider acts the same as one is specified. Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to prepare for future introduction of these clocks. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index bba97270376c..7a916c7d2718 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) p->parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, - CLK_DIVIDER_ONE_BASED, + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clp->clk_lock); break; case CLK_TYPE_GATE: --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 314F72288EA; Fri, 23 May 2025 10:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997236; cv=none; b=lsjRdics8FAZoaRodmlwwa2VIxn+Kbssd6cOY6A+g2/gKxK11xhj8Z5vsiS7glbx0+tPxEV5kUHkMrz/navKwRC7j/85APwOq6UUAEUIaxYsiqaZAxuTsLjUW7o34IUAoCbJIdCf9SD4fnpp7xrxX2J/ppFbw1mVSpxyTuk4hjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997236; c=relaxed/simple; bh=yLdR6mHtlRPoNVFrYNKreCLkJDkwlDyjW2OgdjtFUl0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L8H3r7qxX3ERZ/fi1ruObM2KHZJT81RNTS10YOL31KtEAUk99fmoXnDQFYNkavZVJaTAxQUFIWKyQekPQC3lRZ567ob/NcejiVJrcowH66DXwi9bKOq3ncPS9fs+UTj7nehwvGXejaqVSXGFOWyDAXR6QhElPl56rkD51uIaS2w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=bYxwD8zi; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="bYxwD8zi" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id ED65425C17; Fri, 23 May 2025 12:47:11 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id OMg94BEd1Z2s; Fri, 23 May 2025 12:47:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997231; bh=yLdR6mHtlRPoNVFrYNKreCLkJDkwlDyjW2OgdjtFUl0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bYxwD8zitxVOMOnC6g89GONDR5pcOSLwQkgfRyJIMTVed29mUC76i4DtgWQb6ldTW Da6J4+ZqvIrGc6Pv8zO1JsAnHwGcV5sHrFA4j7tZpy4Zk+BtvrKqt0bxLrg4v9npC/ X4f1qCcruPD586j966aeWNPO1omkAgJqJV2qo8f7TbA9JoxnRa4E7DWPXp1P7vUFeh Wc5NZJqdAmyppE4OzxFMZUyva29ElH/DBWGzd0nagVmZAyi56T8ORNlD1EperSR4DR s8+NIYbqRypTwu3zdO7pmzLN4AB/xS/Xw9abEBPkzwO1qxGx3BgMT/VQFg9zoDQEu1 Ipr+c6r6mJ8KQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 5/8] clk: loongson2: Avoid hardcoding firmware name of the reference clock Date: Fri, 23 May 2025 10:45:49 +0000 Message-ID: <20250523104552.32742-6-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 requires a reference clock with a frequency different from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware name of the reference clock as ref_100m isn't a good idea. This patch retrives the clock name of the reference clock dynamically during probe, avoiding the hardcoded pdata structure and preparing for support of future SoCs. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 7a916c7d2718..52a9f1c2794a 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -13,10 +13,6 @@ #include #include =20 -static const struct clk_parent_data pdata[] =3D { - { .fw_name =3D "ref_100m", }, -}; - enum loongson2_clk_type { CLK_TYPE_PLL, CLK_TYPE_SCALE, @@ -275,7 +271,8 @@ static const struct clk_ops loongson2_freqscale_recalc_= ops =3D { .recalc_rate =3D loongson2_freqscale_recalc_rate, }; =20 -static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider= *clp, +static struct clk_hw *loongson2_clk_register(const char *parent, + struct loongson2_clk_provider *clp, const struct loongson2_clk_board_info *cld, const struct clk_ops *ops) { @@ -292,11 +289,7 @@ static struct clk_hw *loongson2_clk_register(struct lo= ongson2_clk_provider *clp, init.ops =3D ops; init.flags =3D 0; init.num_parents =3D 1; - - if (!cld->parent_name) - init.parent_data =3D pdata; - else - init.parent_names =3D &cld->parent_name; + init.parent_names =3D &parent; =20 clk->reg =3D clp->base + cld->reg_offset; clk->div_shift =3D cld->div_shift; @@ -321,11 +314,17 @@ static int loongson2_clk_probe(struct platform_device= *pdev) struct device *dev =3D &pdev->dev; struct loongson2_clk_provider *clp; const struct loongson2_clk_board_info *p, *data; + const char *refclk_name, *parent_name; =20 data =3D device_get_match_data(dev); if (!data) return -EINVAL; =20 + refclk_name =3D of_clk_get_parent_name(dev->of_node, 0); + if (IS_ERR(refclk_name)) + return dev_err_probe(dev, PTR_ERR(refclk_name), + "failed to get refclk name\n"); + for (p =3D data; p->name; p++) clks_num =3D max(clks_num, p->id + 1); =20 @@ -347,18 +346,20 @@ static int loongson2_clk_probe(struct platform_device= *pdev) =20 for (i =3D 0; i < clks_num; i++) { p =3D &data[i]; + parent_name =3D p->parent_name ? p->parent_name : refclk_name; + switch (p->type) { case CLK_TYPE_PLL: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_pll_recalc_ops); break; case CLK_TYPE_SCALE: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_freqscale_recalc_ops); break; case CLK_TYPE_DIVIDER: hw =3D devm_clk_hw_register_divider(dev, p->name, - p->parent_name, 0, + parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, CLK_DIVIDER_ONE_BASED | @@ -366,15 +367,15 @@ static int loongson2_clk_probe(struct platform_device= *pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + hw =3D devm_clk_hw_register_gate(dev, p->name, parent_name, p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); break; case CLK_TYPE_FIXED: - hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata, - 0, p->fixed_rate); + hw =3D devm_clk_hw_register_fixed_rate(dev, p->name, parent_name, + 0, p->fixed_rate); break; default: return dev_err_probe(dev, -EINVAL, "Invalid clk type\n"); --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C0741C5D7B; Fri, 23 May 2025 10:48:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997289; cv=none; b=DIIRYVH1BUTUeim8ok1RhMBfYRq4Z0C6nhnPEv38utGy6L7nRNGj6InLUHTGm6dkujQuj55PzClmQurhdv7XlFXFqNJXcupYIPHCPgSTPwfyLAu8HtN6AW3ubpLhvbmg4aXczlfER1FMgIDz0/wjwA7XTqyhLi8VGA3AkcNHXGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747997289; c=relaxed/simple; bh=gcYtgfygnQQQpxyGja4Ww0pSmxn9UnF2hNVedw7xXtc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LGxisiO+IcfzonbrnJDPLEvvqBYriwyG9RNe/3OT8R46LrV0KKJCYcFykZ9T+QWXCbhkvE7TJLngaZlr+iSR3g9Xn8fDDK9XBwPzyk4fHE1oXhu00BPHYMA0Hx8xWeVUc0vXveb+mG2E/BEkBudDHi8I4i40UD5YYecUGmAkN8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=QV4uzwEk; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="QV4uzwEk" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id E59AE25F0B; Fri, 23 May 2025 12:48:06 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id H16zQKtTlpA6; Fri, 23 May 2025 12:48:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997286; bh=gcYtgfygnQQQpxyGja4Ww0pSmxn9UnF2hNVedw7xXtc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QV4uzwEkguPQFW/rEjH/hp8hz6wUIWv3Qj3RjOcytpYvgugTIUv+dnitlbl5B/nPz bdVa6AYBxMPh1pw7bt82Z0esgi7DUWQH8NVH9UllgRysLG5Hb8T3Mz2cG8t6DVYh7o mOonJYvWKofw00hLkouLUhhFqKafE5Y/91165feaJdX9NZY3rmsBJPhN3MiTe4jglC 2yBgK9ZFejgj3/U75/iG3pA0cBESTEJFefRbrPZAkl73ATHZiwt8vKZlJqISY3VgTi KtRwZL4o4/G6M0tvpN3PzqYtzBTourzZ/evbfcoZuxedv5uh5sFfuoJ51eqyh02+V4 FZH4egyMoiKOQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC Date: Fri, 23 May 2025 10:45:50 +0000 Message-ID: <20250523104552.32742-7-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock controller of Loongson 2K0300 consists of three PLLs, requires an 120MHz external reference clock to function, and generates clocks in various frequencies for SoC peripherals. Clock definitions for previous SoC generations could be reused for most clock hardwares. There're two gates marked as critical, clk_node_gate and clk_boot_gate, which supply the CPU cores and the system configuration bus. Disabling them leads to a SoC hang. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 52a9f1c2794a..1d210a7683ea 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 enum loongson2_clk_type { CLK_TYPE_PLL, @@ -137,6 +138,52 @@ struct loongson2_clk_board_info { .fixed_rate =3D _rate, \ } =20 +static const struct loongson2_clk_board_info ls2k0300_clks[] =3D { + /* Reference Clock */ + CLK_PLL(LS2K0300_PLL_NODE, "pll_node", 0x00, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_DDR, "pll_ddr", 0x08, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_PIX, "pll_pix", 0x10, 15, 9, 8, 7), + CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000), + CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000), + /* Node PLL */ + CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7), + CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7), + CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7), + CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div= ", 0x00, 0), + CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div= ", 0x00, 1), + CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div",= 0x00, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_sca= le", + 0x24, 0, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node= _pll_gate", + 0x20, 0, 3, 3), + /* DDR PLL */ + CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7), + CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7), + CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7), + CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1), + CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", + 0x08, 0, CLK_IS_CRITICAL), + /* PIX PLL */ + CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7), + CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7), + CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x= 10, 0), + CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24= , 6), + CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", = 0x10, 1), + CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate= ", + 0x20, 4, 3, 7), + /* clk_dev_gate */ + CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, = 24, 4), + CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2= ), + CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24,= 4), + CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3= ), + CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", + 0x24, 1, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate",= 0x20, 12, 3, 15), + CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate",= 0x20, 16, 3, 19), + CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate",= 0x20, 8, 3, 11), +}; + static const struct loongson2_clk_board_info ls2k0500_clks[] =3D { CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6), CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6), @@ -393,6 +440,7 @@ static int loongson2_clk_probe(struct platform_device *= pdev) } =20 static const struct of_device_id loongson2_clk_match_table[] =3D { + { .compatible =3D "loongson,ls2k0300-clk", .data =3D &ls2k0300_clks }, { .compatible =3D "loongson,ls2k0500-clk", .data =3D &ls2k0500_clks }, { .compatible =3D "loongson,ls2k-clk", .data =3D &ls2k1000_clks }, { .compatible =3D "loongson,ls2k2000-clk", .data =3D &ls2k2000_clks }, --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130571E0E1A; Fri, 23 May 2025 10:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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charset="utf-8" Describe the clock controller integrated in Loongson 2K0300 SoC and clocks for UARTs. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300.dtsi | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/= boot/dts/loongson-2k0300.dtsi index ce3574691aa9..44e37d6f8e98 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include =20 / { @@ -21,7 +22,7 @@ cpu0: cpu@0 { compatible =3D "loongson,la264"; reg =3D <0>; device_type =3D "cpu"; - clocks =3D <&cpu_clk>; + clocks =3D <&clk LS2K0300_CLK_NODE_GATE>; }; =20 }; @@ -32,9 +33,10 @@ cpuintc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 - cpu_clk: clock-1000m { + refclk: clock-120m { compatible =3D "fixed-clock"; - clock-frequency =3D <1000000000>; + clock-frequency =3D <120000000>; + clock-output-names =3D "refclk_120m"; #clock-cells =3D <0>; }; =20 @@ -46,6 +48,14 @@ soc@10000000 { <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>, <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>; =20 + clk: clock-controller@16000400 { + compatible =3D "loongson,ls2k0300-clk"; + reg =3D <0x0 0x16000400 0x0 0x100>; + clocks =3D <&refclk>; + clock-names =3D "ref_120m"; + #clock-cells =3D <1>; + }; + liointc0: interrupt-controller@16001400 { compatible =3D "loongson,liointc-2.0"; reg =3D <0x0 0x16001400 0x0 0x40>, @@ -87,6 +97,7 @@ liointc1: interrupt-controller@16001440 { uart0: serial@16100000 { compatible =3D "ns16550a"; reg =3D <0 0x16100000 0 0x10>; + clocks =3D <&clk LS2K0300_CLK_APB_GATE>; interrupt-parent =3D <&liointc0>; interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; no-loopback-test; --=20 2.49.0 From nobody Fri Dec 19 14:47:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CA342288D3; Fri, 23 May 2025 10:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="XxZJ5qzF" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 603AC2607B; Fri, 23 May 2025 12:48:18 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id QavgVJNkJmsT; Fri, 23 May 2025 12:48:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1747997297; bh=4FbE9OETQQ7uPyNyavMW6wHUX4plr2tkY6TssAU8IkM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XxZJ5qzFnmkRMD7TfDTa4kSI2L9tt303ixkBXNlcNYUoidyCxTafv6ToZEnGthSBp trfUs+xroYdKS5efb3uVwJ6OQuWzIovakXzJ23RCsuzE2HvLLPGOtkKMUHN1fHc5QH 1hm4RmNrktQBzhfdb7nFA2lkWtB28uIcNG2lnUsYmcpzWergNFcJLDI042L6//ylXd hV2OEKA9l6BbM0akoXlBK/Lt3DvgPS9VM6orLVWXHqbA0rhCc4EN/L8RYvs9aMLWcL 3IDjAROueODOOG2ubcxsCkmuLwN7Rjdqneb0EpuX18nHkrKFDKoFTfwwef93Hw5VsV l5RUZjhVWQ8Sg== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Yinbo Zhu Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH 8/8] LoongArch: dts: Remove clock-frquency from UART0 of CTCISZ Forever Pi Date: Fri, 23 May 2025 10:45:52 +0000 Message-ID: <20250523104552.32742-9-ziyao@disroot.org> In-Reply-To: <20250523104552.32742-1-ziyao@disroot.org> References: <20250523104552.32742-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The property isn't required anymore as the supply clock of UART0 has been described. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts = b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts index a033c086461f..1bdfff7fae92 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts +++ b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts @@ -40,6 +40,5 @@ linux,cma { }; =20 &uart0 { - clock-frequency =3D <100000000>; status =3D "okay"; }; --=20 2.49.0