From nobody Sun Dec 14 12:18:16 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC171293B5D for ; Fri, 23 May 2025 01:01:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747962079; cv=none; b=Olb0Yi0NNJcr/VKT3PlSFWSas/J+OTjWWgVgzdX8cIuo9D+Li8f96Evj0+ZL0qSJtpd6FMIifVRHw2SHfcOOj34LYQWiwhnWx5C0oFrlLnJF0CILNLzWcLjR8Km8GlgNthjN2gTiTijmnxLOYk7WAUcf28o1rZc/p0e1omOlcQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747962079; c=relaxed/simple; bh=gFtnllkdHoK++kmV2uIN5igfGRjKb467ITbvyuZHPpg=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=a/VQmt7YHOD6UAb4kmzWe4Q6hovRYZ7TDbIkEOlvfo+fN+GHHZp1lx+iOFJrWswoOcn9AAQmVJkWkjfSRLB50rnC8SPDPH8cJMhRl8u9v+ChCDDM77Garbrokb7i/LOsZ7xxe286MwegIrjhaLNibp5T8ndGIguBwBo+Y2TSK0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ii/K0F48; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ii/K0F48" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-310c5c2c38cso1551297a91.1 for ; Thu, 22 May 2025 18:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1747962077; x=1748566877; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=hpBhApwrSh8aZyMZyjubfokkuVPDDm+wIxTVx+y5WkM=; b=ii/K0F48V+DnpMyf4bwJKMVHk0QZGDndFtrC3mPrOOikaadQ6pJduPSSPjpb0sBcD1 +i4zYNljViYlrvnqnsMptFvTYayfzSiI6V+NlnRJbp/j1qlt8lE66TccjilGb0BBBTgt kNUNKar8JvKKhClGC3ndcYdry6621cPHU/thIFhowLACGxEZNeHm9BBTonL27mctm1CS IFqJP7Zor3LW5NrHhqzAuPqbfsvGnroXPh3K8VzcPALfss74in7cHbsrvvk7ySyIVWuq 19DVKw6Ua5Ohp4cb5mfNTVhGYR39zTTc6RgHp+VT4Sn7+j38/bG3x183ouHiGbpVUiCA 20ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747962077; x=1748566877; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=hpBhApwrSh8aZyMZyjubfokkuVPDDm+wIxTVx+y5WkM=; b=HgPjkKHPHgymNar9tXgmGUkxHGcZ69pe6cMmiRZx6VQ1+TuPWeAdcBQSd+a4DwNGXA p9ISwesqf4qqfO9Q3BVsc4g4rAX6W6d/dgLDOLoWn5Tp/yuNlJ1mOafC5hWAOKhaJko2 c6PSKkX2XhWRdQ9TZs3VIcN2dTrdP6zmipLB8ng3txtgqqKUf4J7EDGRw1uwMJaYnSJw EK9lpPk5c8wvtdQQR/iZitshc2jRyHLgLtIJ0x841rmetHFificNgf64D3RM0L4rGXcY tTx/7mO7bCfClZLDVbZZRy0cmo0MMw1PZkSXx+oZ2l6iEWlOQkx4x87e3n2s9h/DuCTk mkpg== X-Forwarded-Encrypted: i=1; AJvYcCW95XugRbBfGxve/TMWthQLOX1uxSgdgEA1jfFBNrk+0kBEzL98HRmE7roojJvpgWq14DLeKF3uAsNNFzQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzkoaM+zhVcvLDkGySXKoXuA4WfclIVxBR/l0L99pKA5YApNO0Z 5/scRdaaKJrFqGwNNLsDwhSwAnh7v8qrgOVE7Cm1eTDIaSPJX3ikAb5u4TEEXgx6yIt6DMD3ngt tJp+4hA== X-Google-Smtp-Source: AGHT+IGTYhCOjxbmKRXOrjbAavunsh63uzQMspWrxbHwEJtJhbbYao5aLSwUJ5OJG/DqIAodT2HfVFXoKXw= X-Received: from pjb7.prod.google.com ([2002:a17:90b:2f07:b0:2ff:6132:8710]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4acf:b0:2ee:aa28:79aa with SMTP id 98e67ed59e1d1-30e830c772dmr35674777a91.6.1747962077355; Thu, 22 May 2025 18:01:17 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 22 May 2025 17:59:45 -0700 In-Reply-To: <20250523010004.3240643-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250523010004.3240643-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.1151.ga128411c76-goog Message-ID: <20250523010004.3240643-41-seanjc@google.com> Subject: [PATCH v2 40/59] iommu/amd: KVM: SVM: Set pCPU info in IRTE when setting vCPU affinity From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that setting vCPU affinity is guarded with ir_list_lock, i.e. now that avic_physical_id_entry can be safely accessed, set the pCPU info straight-away when setting vCPU affinity. Putting the IRTE into posted mode, and then immediately updating the IRTE a second time if the target vCPU is running is wasteful and confusing. This also fixes a flaw where a posted IRQ that arrives between putting the IRTE into guest_mode and setting the correct destination could cause the IOMMU to ring the doorbell on the wrong pCPU. Signed-off-by: Sean Christopherson --- arch/x86/include/asm/irq_remapping.h | 1 + arch/x86/kvm/svm/avic.c | 26 ++++++++++++++------------ drivers/iommu/amd/iommu.c | 6 ++++-- include/linux/amd-iommu.h | 4 ++-- 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/ir= q_remapping.h index 2dbc9cb61c2f..4c75a17632f6 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -35,6 +35,7 @@ struct amd_iommu_pi_data { u64 vapic_addr; /* Physical address of the vCPU's vAPIC. */ u32 ga_tag; u32 vector; /* Guest vector of the interrupt */ + int cpu; bool is_guest_mode; void *ir_data; }; diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index c79648d96752..16557328aa58 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -726,6 +726,7 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vcp= u) =20 static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) { + int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); int ret =3D 0; unsigned long flags; struct vcpu_svm *svm =3D to_svm(vcpu); @@ -745,7 +746,7 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu,= bool activate) =20 list_for_each_entry(irqfd, &svm->ir_list, vcpu_list) { if (activate) - ret =3D amd_iommu_activate_guest_mode(irqfd->irq_bypass_data); + ret =3D amd_iommu_activate_guest_mode(irqfd->irq_bypass_data, apic_id); else ret =3D amd_iommu_deactivate_guest_mode(irqfd->irq_bypass_data); if (ret) @@ -809,6 +810,18 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, */ guard(spinlock_irqsave)(&svm->ir_list_lock); =20 + /* + * Update the target pCPU for IOMMU doorbells if the vCPU is + * running. If the vCPU is NOT running, i.e. is blocking or + * scheduled out, KVM will update the pCPU info when the vCPU + * is awakened and/or scheduled in. See also avic_vcpu_load(). + */ + entry =3D svm->avic_physical_id_entry; + if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) + pi_data.cpu =3D entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; + else + pi_data.cpu =3D -1; + ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); if (ret) return ret; @@ -823,17 +836,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, return -EIO; } =20 - /* - * Update the target pCPU for IOMMU doorbells if the vCPU is - * running. If the vCPU is NOT running, i.e. is blocking or - * scheduled out, KVM will update the pCPU info when the vCPU - * is awakened and/or scheduled in. See also avic_vcpu_load(). - */ - entry =3D svm->avic_physical_id_entry; - if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) - amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MAS= K, - pi_data.ir_data); - irqfd->irq_bypass_data =3D pi_data.ir_data; list_add(&irqfd->vcpu_list, &svm->ir_list); return 0; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 15718b7b8bd4..718bd9604f71 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3850,7 +3850,7 @@ int amd_iommu_update_ga(int cpu, void *data) } EXPORT_SYMBOL(amd_iommu_update_ga); =20 -int amd_iommu_activate_guest_mode(void *data) +int amd_iommu_activate_guest_mode(void *data, int cpu) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; @@ -3871,6 +3871,8 @@ int amd_iommu_activate_guest_mode(void *data) entry->hi.fields.vector =3D ir_data->ga_vector; entry->lo.fields_vapic.ga_tag =3D ir_data->ga_tag; =20 + __amd_iommu_update_ga(entry, cpu); + return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, ir_data->irq_2_irte.index, entry); } @@ -3937,7 +3939,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *info) ir_data->ga_root_ptr =3D (pi_data->vapic_addr >> 12); ir_data->ga_vector =3D pi_data->vector; ir_data->ga_tag =3D pi_data->ga_tag; - ret =3D amd_iommu_activate_guest_mode(ir_data); + ret =3D amd_iommu_activate_guest_mode(ir_data, pi_data->cpu); } else { ret =3D amd_iommu_deactivate_guest_mode(ir_data); } diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index fe0e16ffe0e5..c9f2df0c4596 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -32,7 +32,7 @@ extern int amd_iommu_register_ga_log_notifier(int (*notif= ier)(u32)); =20 extern int amd_iommu_update_ga(int cpu, void *data); =20 -extern int amd_iommu_activate_guest_mode(void *data); +extern int amd_iommu_activate_guest_mode(void *data, int cpu); extern int amd_iommu_deactivate_guest_mode(void *data); =20 #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ @@ -48,7 +48,7 @@ static inline int amd_iommu_update_ga(int cpu, void *data) return 0; } =20 -static inline int amd_iommu_activate_guest_mode(void *data) +static inline int amd_iommu_activate_guest_mode(void *data, int cpu) { return 0; } --=20 2.49.0.1151.ga128411c76-goog