From nobody Sun Dec 14 12:18:09 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0254226CF7 for ; Fri, 23 May 2025 01:00:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747962035; cv=none; b=TA40fsrrIJACFo6togmP0wmJxyF1AqKo+fTrCIZKy4HnzASjxaHinI958Y0odEdbgqbucCXNSpfz1gbz8xgkDAIA8J51Qd9ATbEvE/kNfxpPr2VPn+P1aRJtJesUIpYUC1Q7ShcYPn7NyKCrnjOytwOb238yePWfePzjbgkBLpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747962035; c=relaxed/simple; bh=CI55+D0kEm5O6+xiEBD1DyHjTu/geN9Q80IyZ5PbyXI=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=rrB3aWgJQhX+ynG50oyw8A3YKQvnouuSSqdhf4EYMpuC3KLGk85AV9Ee5B8eBAuh2UdnY5sd0Nh+fwtP7rFNTcdvKLecodBMmnmrohxN5nFx/kWcPoFPeGq11dadNdIr24to0YjIaN9krG19ZHLgvQ9RdQIB5nl8VkyIMqVT5CY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=LZRhpwBt; arc=none smtp.client-ip=209.85.215.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="LZRhpwBt" Received: by mail-pg1-f201.google.com with SMTP id 41be03b00d2f7-b2c0cbf9fddso405277a12.3 for ; Thu, 22 May 2025 18:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1747962033; x=1748566833; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=mgom0My0RXyxt3zGYxIwZj5mPyM4HyH/qZA3LIBxvLE=; b=LZRhpwBtd+KpkGdfkoo7EfQXrgfOkZ4Fm8rndgIRCxqmmMicsggfA1cXkx8nlw4yVm 0zx1PKhO1WFqtXsz2awdDlXLc/+DQP/aXaD9oEw6rKOw01682VXWzRzFRi9zFDRVOCOX PffKDCwuokP25ihvdKvZVoNIuPbAX++3IYS4JRp6LrbTgGBcObPQYJNy+Q9rezU2iiWJ AzpPOg34LVophMVxGej9mH+pLbmRUBZZIa+54RgVf15n0dz2L3OyUxQgIrXovpDP8s31 YAqFoEASbIFfI9sCJIjzfCKH0dC48jFnsILPp0vCtY6SAtgipghuHlhKLix3QbcC/6G3 0HbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747962033; x=1748566833; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mgom0My0RXyxt3zGYxIwZj5mPyM4HyH/qZA3LIBxvLE=; b=jIVwbpW/LYOEcdYMXl4xN+YK6rVlhRCoPbF/gqMpCEXCaw+xni8CLkzyaR5va714UJ jFWVkQxjpsFw3t4wFwNp8OGs1o713zcChhm6rWQ2pes6wglT+ulfkQ4QuiJ+hxPEFk78 VAWd7Kp9IJacA93/IJ/jGMh6DjSPmMBcVmZQAYBktR/mD54vOcbfEMaQDanmPZQ1J7Tj 9d9jU+QTtpqYOLY1OfYYmDWOSglBH4B47JenJuksKr2DFfCZNJ0WXufrfj8ae8cQNFt1 Gu+dRQZykbHXgB3G7S/ogSTZ01pyMWqheJz6l04s/3ET/QyggRjgJa9e4zoy65lCgfuW aLhw== X-Forwarded-Encrypted: i=1; AJvYcCXWkeFblCwNpDIVX/z28ra7kx3kw/cHBqotE43sWpku6VWVs/D2YoSRDP47AxKriK5PnlHsclwGk1GZaDo=@vger.kernel.org X-Gm-Message-State: AOJu0Yz94UBzu9b6tC3yPOUrMy1J7iAnxCSCAgmhbwmxnZdZ1YKHchyA xmFS9yj+AGxF/y0eIhIyx+qG9S45Fps88/Vzr61/wLNbEO9zdxQDZc3CayMTTXxmMjAFY60teHZ NaeKVyg== X-Google-Smtp-Source: AGHT+IGxjUT6ZTFdn1fL46e7uP64GFmrOiUImY5wsG9IiTzQ4jbxEpbauT01oNGyrrPeVaV1B6nroWQExuI= X-Received: from pjuw7.prod.google.com ([2002:a17:90a:d607:b0:308:867e:1ced]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3c90:b0:30a:a50e:349c with SMTP id 98e67ed59e1d1-30e83226f25mr38441643a91.30.1747962033065; Thu, 22 May 2025 18:00:33 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 22 May 2025 17:59:18 -0700 In-Reply-To: <20250523010004.3240643-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250523010004.3240643-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.1151.ga128411c76-goog Message-ID: <20250523010004.3240643-14-seanjc@google.com> Subject: [PATCH v2 13/59] KVM: SVM: Drop superfluous "cache" of AVIC Physical ID entry pointer From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the vCPU's pointer to its AVIC Physical ID entry, and simply index the table directly. Caching a pointer address is completely unnecessary for performance, and while the field technically caches the result of the pointer calculation, it's all too easy to misinterpret the name and think that the field somehow caches the _data_ in the table. No functional change intended. Suggested-by: Maxim Levitsky Tested-by: Sairaj Kodilkar Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/avic.c | 27 +++++++++++++++------------ arch/x86/kvm/svm/svm.h | 1 - 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index bf18b0b643d9..0c0be274d29e 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -294,8 +294,6 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 - svm->avic_physical_id_cache =3D &kvm_svm->avic_physical_id_table[id]; - return 0; } =20 @@ -770,13 +768,16 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct kvm_kernel_irqfd *irqfd, struct amd_iommu_pi_data *pi) { + struct kvm_vcpu *vcpu =3D &svm->vcpu; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); unsigned long flags; u64 entry; =20 if (WARN_ON_ONCE(!pi->ir_data)) return -EINVAL; =20 - irqfd->irq_bypass_vcpu =3D &svm->vcpu; + irqfd->irq_bypass_vcpu =3D vcpu; irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); @@ -787,7 +788,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, * will update the pCPU info when the vCPU awkened and/or scheduled in. * See also avic_vcpu_load(). */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); @@ -964,17 +965,18 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu= , int cpu, bool r) =20 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); int h_physical_id =3D kvm_cpu_get_apicid(cpu); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK= )) return; =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -996,14 +998,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); @@ -1011,13 +1013,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) =20 void avic_vcpu_put(struct kvm_vcpu *vcpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -1027,7 +1030,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) * can't be scheduled out and thus avic_vcpu_{put,load}() can't run * recursively. */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) @@ -1046,7 +1049,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) avic_update_iommu_vcpu_affinity(vcpu, -1, 0); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index ec5d77d42a49..f225d0bed152 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -306,7 +306,6 @@ struct vcpu_svm { =20 u32 ldr_reg; u32 dfr_reg; - u64 *avic_physical_id_cache; =20 /* * Per-vCPU list of irqfds that are eligible to post IRQs directly to --=20 2.49.0.1151.ga128411c76-goog