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From: Dylan Hatch To: Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Josh Poimboeuf , Jiri Kosina , Miroslav Benes , Petr Mladek , Joe Lawrence Cc: Dylan Hatch , Song Liu , Ard Biesheuvel , Sami Tolvanen , Peter Zijlstra , "Mike Rapoport (Microsoft)" , Andrew Morton , Dan Carpenter , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, live-patching@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Late module relocations are an issue on any arch that supports livepatch, so move the text_mutex locking to the livepatch core code. Signed-off-by: Dylan Hatch Acked-by: Song Liu --- arch/x86/kernel/module.c | 8 ++------ kernel/livepatch/core.c | 18 +++++++++++++----- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c index ff07558b7ebc6..38767e0047d0c 100644 --- a/arch/x86/kernel/module.c +++ b/arch/x86/kernel/module.c @@ -197,18 +197,14 @@ static int write_relocate_add(Elf64_Shdr *sechdrs, bool early =3D me->state =3D=3D MODULE_STATE_UNFORMED; void *(*write)(void *, const void *, size_t) =3D memcpy; =20 - if (!early) { + if (!early) write =3D text_poke; - mutex_lock(&text_mutex); - } =20 ret =3D __write_relocate_add(sechdrs, strtab, symindex, relsec, me, write, apply); =20 - if (!early) { + if (!early) text_poke_sync(); - mutex_unlock(&text_mutex); - } =20 return ret; } diff --git a/kernel/livepatch/core.c b/kernel/livepatch/core.c index 0e73fac55f8eb..9968441f73510 100644 --- a/kernel/livepatch/core.c +++ b/kernel/livepatch/core.c @@ -294,9 +294,10 @@ static int klp_write_section_relocs(struct module *pmo= d, Elf_Shdr *sechdrs, unsigned int symndx, unsigned int secndx, const char *objname, bool apply) { - int cnt, ret; + int cnt, ret =3D 0; char sec_objname[MODULE_NAME_LEN]; Elf_Shdr *sec =3D sechdrs + secndx; + bool early =3D pmod->state =3D=3D MODULE_STATE_UNFORMED; =20 /* * Format: .klp.rela.sec_objname.section_name @@ -319,12 +320,19 @@ static int klp_write_section_relocs(struct module *pm= od, Elf_Shdr *sechdrs, sec, sec_objname); if (ret) return ret; - - return apply_relocate_add(sechdrs, strtab, symndx, secndx, pmod); } =20 - clear_relocate_add(sechdrs, strtab, symndx, secndx, pmod); - return 0; + if (!early) + mutex_lock(&text_mutex); + + if (apply) + ret =3D apply_relocate_add(sechdrs, strtab, symndx, secndx, pmod); + else + clear_relocate_add(sechdrs, strtab, symndx, secndx, pmod); + + if (!early) + mutex_unlock(&text_mutex); + return ret; } =20 int klp_apply_section_relocs(struct module *pmod, Elf_Shdr *sechdrs, --=20 2.49.0.1151.ga128411c76-goog From nobody Sun Dec 14 06:39:56 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C95871DDC11 for ; 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Thu, 22 May 2025 11:43:42 -0700 (PDT) Date: Thu, 22 May 2025 18:42:49 +0000 In-Reply-To: <20250522184249.3137187-1-dylanbhatch@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250522184249.3137187-1-dylanbhatch@google.com> X-Mailer: git-send-email 2.49.0.1151.ga128411c76-goog Message-ID: <20250522184249.3137187-3-dylanbhatch@google.com> Subject: [PATCH v3 2/2] arm64/module: Use text-poke API for late relocations. From: Dylan Hatch To: Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Josh Poimboeuf , Jiri Kosina , Miroslav Benes , Petr Mladek , Joe Lawrence Cc: Dylan Hatch , Song Liu , Ard Biesheuvel , Sami Tolvanen , Peter Zijlstra , "Mike Rapoport (Microsoft)" , Andrew Morton , Dan Carpenter , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, live-patching@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To enable late module patching, livepatch modules need to be able to apply some of their relocations well after being loaded. In this scenario, use the text-poking API to allow this, even with STRICT_MODULE_RWX. This patch is partially based off commit 88fc078a7a8f6 ("x86/module: Use text_poke() for late relocations"). Signed-off-by: Dylan Hatch Acked-by: Song Liu --- arch/arm64/kernel/module.c | 114 ++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 45 deletions(-) diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index 06bb680bfe975..3998fb3322b73 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -18,11 +18,13 @@ #include #include #include +#include =20 #include #include #include #include +#include =20 enum aarch64_reloc_op { RELOC_OP_NONE, @@ -48,7 +50,8 @@ static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le3= 2 *place, u64 val) return 0; } =20 -static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int = len) +static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int = len, + struct module *me) { s64 sval =3D do_reloc(op, place, val); =20 @@ -66,7 +69,11 @@ static int reloc_data(enum aarch64_reloc_op op, void *pl= ace, u64 val, int len) =20 switch (len) { case 16: - *(s16 *)place =3D sval; + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, sval, sizeof(s16)); + else + *(s16 *)place =3D sval; + switch (op) { case RELOC_OP_ABS: if (sval < 0 || sval > U16_MAX) @@ -82,7 +89,11 @@ static int reloc_data(enum aarch64_reloc_op op, void *pl= ace, u64 val, int len) } break; case 32: - *(s32 *)place =3D sval; + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, sval, sizeof(s32)); + else + *(s32 *)place =3D sval; + switch (op) { case RELOC_OP_ABS: if (sval < 0 || sval > U32_MAX) @@ -98,8 +109,10 @@ static int reloc_data(enum aarch64_reloc_op op, void *p= lace, u64 val, int len) } break; case 64: - *(s64 *)place =3D sval; - break; + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, sval, sizeof(s64)); + else + *(s64 *)place =3D sval; break; default: pr_err("Invalid length (%d) for data relocation\n", len); return 0; @@ -113,7 +126,8 @@ enum aarch64_insn_movw_imm_type { }; =20 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 va= l, - int lsb, enum aarch64_insn_movw_imm_type imm_type) + int lsb, enum aarch64_insn_movw_imm_type imm_type, + struct module *me) { u64 imm; s64 sval; @@ -145,7 +159,10 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, _= _le32 *place, u64 val, =20 /* Update the instruction with the new encoding. */ insn =3D aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); - *place =3D cpu_to_le32(insn); + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, cpu_to_le32(insn), sizeof(insn)); + else + *place =3D cpu_to_le32(insn); =20 if (imm > U16_MAX) return -ERANGE; @@ -154,7 +171,8 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, __= le32 *place, u64 val, } =20 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, - int lsb, int len, enum aarch64_insn_imm_type imm_type) + int lsb, int len, enum aarch64_insn_imm_type imm_type, + struct module *me) { u64 imm, imm_mask; s64 sval; @@ -170,7 +188,10 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, __= le32 *place, u64 val, =20 /* Update the instruction's immediate field. */ insn =3D aarch64_insn_encode_immediate(imm_type, insn, imm); - *place =3D cpu_to_le32(insn); + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, cpu_to_le32(insn), sizeof(insn)); + else + *place =3D cpu_to_le32(insn); =20 /* * Extract the upper value bits (including the sign bit) and @@ -189,17 +210,17 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, _= _le32 *place, u64 val, } =20 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs, - __le32 *place, u64 val) + __le32 *place, u64 val, struct module *me) { u32 insn; =20 if (!is_forbidden_offset_for_adrp(place)) return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21, - AARCH64_INSN_IMM_ADR); + AARCH64_INSN_IMM_ADR, me); =20 /* patch ADRP to ADR if it is in range */ if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21, - AARCH64_INSN_IMM_ADR)) { + AARCH64_INSN_IMM_ADR, me)) { insn =3D le32_to_cpu(*place); insn &=3D ~BIT(31); } else { @@ -211,7 +232,10 @@ static int reloc_insn_adrp(struct module *mod, Elf64_S= hdr *sechdrs, AARCH64_INSN_BRANCH_NOLINK); } =20 - *place =3D cpu_to_le32(insn); + if (me->state !=3D MODULE_STATE_UNFORMED) + aarch64_insn_set(place, cpu_to_le32(insn), sizeof(insn)); + else + *place =3D cpu_to_le32(insn); return 0; } =20 @@ -255,23 +279,23 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, /* Data relocations. */ case R_AARCH64_ABS64: overflow_check =3D false; - ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 64); + ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 64, me); break; case R_AARCH64_ABS32: - ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 32); + ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 32, me); break; case R_AARCH64_ABS16: - ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 16); + ovf =3D reloc_data(RELOC_OP_ABS, loc, val, 16, me); break; case R_AARCH64_PREL64: overflow_check =3D false; - ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 64); + ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 64, me); break; case R_AARCH64_PREL32: - ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 32); + ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 32, me); break; case R_AARCH64_PREL16: - ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 16); + ovf =3D reloc_data(RELOC_OP_PREL, loc, val, 16, me); break; =20 /* MOVW instruction relocations. */ @@ -280,88 +304,88 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, fallthrough; case R_AARCH64_MOVW_UABS_G0: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_UABS_G1_NC: overflow_check =3D false; fallthrough; case R_AARCH64_MOVW_UABS_G1: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_UABS_G2_NC: overflow_check =3D false; fallthrough; case R_AARCH64_MOVW_UABS_G2: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_UABS_G3: /* We're using the top bits so we can't overflow. */ overflow_check =3D false; ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_SABS_G0: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_SABS_G1: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_SABS_G2: ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_PREL_G0_NC: overflow_check =3D false; ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_PREL_G0: ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_PREL_G1_NC: overflow_check =3D false; ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_PREL_G1: ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_PREL_G2_NC: overflow_check =3D false; ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, - AARCH64_INSN_IMM_MOVKZ); + AARCH64_INSN_IMM_MOVKZ, me); break; case R_AARCH64_MOVW_PREL_G2: ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; case R_AARCH64_MOVW_PREL_G3: /* We're using the top bits so we can't overflow. */ overflow_check =3D false; ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, - AARCH64_INSN_IMM_MOVNZ); + AARCH64_INSN_IMM_MOVNZ, me); break; =20 /* Immediate instruction relocations. */ case R_AARCH64_LD_PREL_LO19: ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, - AARCH64_INSN_IMM_19); + AARCH64_INSN_IMM_19, me); break; case R_AARCH64_ADR_PREL_LO21: ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, - AARCH64_INSN_IMM_ADR); + AARCH64_INSN_IMM_ADR, me); break; case R_AARCH64_ADR_PREL_PG_HI21_NC: overflow_check =3D false; fallthrough; case R_AARCH64_ADR_PREL_PG_HI21: - ovf =3D reloc_insn_adrp(me, sechdrs, loc, val); + ovf =3D reloc_insn_adrp(me, sechdrs, loc, val, me); if (ovf && ovf !=3D -ERANGE) return ovf; break; @@ -369,46 +393,46 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, case R_AARCH64_LDST8_ABS_LO12_NC: overflow_check =3D false; ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, - AARCH64_INSN_IMM_12); + AARCH64_INSN_IMM_12, me); break; case R_AARCH64_LDST16_ABS_LO12_NC: overflow_check =3D false; ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, - AARCH64_INSN_IMM_12); + AARCH64_INSN_IMM_12, me); break; case R_AARCH64_LDST32_ABS_LO12_NC: overflow_check =3D false; ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, - AARCH64_INSN_IMM_12); + AARCH64_INSN_IMM_12, me); break; case R_AARCH64_LDST64_ABS_LO12_NC: overflow_check =3D false; ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, - AARCH64_INSN_IMM_12); + AARCH64_INSN_IMM_12, me); break; case R_AARCH64_LDST128_ABS_LO12_NC: overflow_check =3D false; ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, - AARCH64_INSN_IMM_12); + AARCH64_INSN_IMM_12, me); break; case R_AARCH64_TSTBR14: ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, - AARCH64_INSN_IMM_14); + AARCH64_INSN_IMM_14, me); break; case R_AARCH64_CONDBR19: ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, - AARCH64_INSN_IMM_19); + AARCH64_INSN_IMM_19, me); break; case R_AARCH64_JUMP26: case R_AARCH64_CALL26: ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, - AARCH64_INSN_IMM_26); + AARCH64_INSN_IMM_26, me); if (ovf =3D=3D -ERANGE) { val =3D module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym); if (!val) return -ENOEXEC; ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, - 26, AARCH64_INSN_IMM_26); + 26, AARCH64_INSN_IMM_26, me); } break; =20 --=20 2.49.0.1151.ga128411c76-goog