From nobody Fri Dec 19 13:08:33 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6E689208AD; Thu, 22 May 2025 18:23:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938209; cv=none; b=X0PGbLkusZGufnfFzDVSgdLGVl+T6XVNSjDHPPKYybg1zQmAG95dYpsRmzprgGITA4FF3Y5vXbCdF3I//Ss0wTPQif74NaTQV6bUmHW7pICwrCzgza6iNjwaom8wbgRN8/O4yaV3Wx/2UliNUOqlWHYuv54snfcfjY+RUtnlc1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938209; c=relaxed/simple; bh=51fhZD20BOel06rmA5rJI/ZS3uZv0xHZpNK1MLh8n/U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J6XB4IcRGqyMhfswdcY9h+1wtg+WVOohdPJlQk9OoKx+idwkVZ//6G/8wf0C4aAdfmU30virv4uzb7xYWaUnH/ECGLTwaDXFOJapIlreUTWjzUM6zYKZw6lXR47xe3ZuNKWJm9MM87HAIlFHgJaHb3EI6uuvRfYwvKT2irW64xU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: jWA8JtNjRoOWeue8F+6sbg== X-CSE-MsgGUID: GkDLjPMxQ0a68hJBQbgEYg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 May 2025 03:23:20 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.203]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5AD474061FC8; Fri, 23 May 2025 03:23:15 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, rafael@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, niklas.soderlund+renesas@ragnatech.se, Claudiu Beznea Subject: [PATCH v6 1/5] soc: renesas: rz-sysc: Add syscon/regmap support Date: Thu, 22 May 2025 20:22:44 +0200 Message-ID: <20250522182252.1593159-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> References: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, add register a custom regmap configuration. Signed-off-by: John Madieu [claudiu.beznea: - s/rzg3e_sysc_regmap/rzv2h_sysc_regmap in RZ/V2H sysc file - do not check the match->data validity in rz_sysc_probe() as it is always valid - register the regmap if data->regmap_cfg is valid] Signed-off-by: Claudiu Beznea --- Changes: v1 -> v2: no changes v2 -> v3: no changes v3 -> v4: no changes v4 -> v5: no changes v6: Addressed the review comments received at [1]; [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.r= enesas.com/ drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 10 ++++++++++ drivers/soc/renesas/r9a09g047-sys.c | 10 ++++++++++ drivers/soc/renesas/r9a09g057-sys.c | 10 ++++++++++ drivers/soc/renesas/rz-sysc.c | 17 ++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 3 +++ 6 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fbc3b69d21a7..f3b7546092d6 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -437,6 +437,7 @@ config RST_RCAR =20 config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON =20 config SYSC_R9A08G045 bool "Renesas RZ/G3S System controller support" if COMPILE_TEST diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index f4db1431e036..0ef6df77e25f 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -18,6 +18,16 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_= soc_id_init_data __initc .specific_id_mask =3D GENMASK(27, 0), }; =20 +static const struct regmap_config rzg3s_sysc_regmap __initconst =3D { + .name =3D "rzg3s_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0xe20, +}; + const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, + .regmap_cfg =3D &rzg3s_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index cd2eb7782cfe..a3acf6dd2867 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_s= oc_id_init_data __initco .print_id =3D rzg3e_sys_print_id, }; =20 +static const struct regmap_config rzg3e_sysc_regmap __initconst =3D { + .name =3D "rzg3e_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzg3e_sys_init_data =3D { .soc_id_init_data =3D &rzg3e_sys_soc_id_init_data, + .regmap_cfg =3D &rzg3e_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 4c21cc29edbc..c26821636dce 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_s= oc_id_init_data __initco .print_id =3D rzv2h_sys_print_id, }; =20 +static const struct regmap_config rzv2h_sysc_regmap __initconst =3D { + .name =3D "rzv2h_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzv2h_sys_init_data =3D { .soc_id_init_data =3D &rzv2h_sys_soc_id_init_data, + .regmap_cfg =3D &rzv2h_sysc_regmap, }; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ffa65fb4dade..70556a2f55e6 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -6,8 +6,10 @@ */ =20 #include +#include #include #include +#include #include =20 #include "rz-sysc.h" @@ -100,14 +102,19 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); =20 static int rz_sysc_probe(struct platform_device *pdev) { + const struct rz_sysc_init_data *data; const struct of_device_id *match; struct device *dev =3D &pdev->dev; + struct regmap *regmap; struct rz_sysc *sysc; + int ret; =20 match =3D of_match_node(rz_sysc_match, dev->of_node); if (!match) return -ENODEV; =20 + data =3D match->data; + sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) return -ENOMEM; @@ -117,7 +124,15 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); =20 sysc->dev =3D dev; - return rz_sysc_soc_init(sysc, match); + ret =3D rz_sysc_soc_init(sysc, match); + if (ret || !data->regmap_cfg) + return ret; + + regmap =3D devm_regmap_init_mmio(dev, sysc->base, data->regmap_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); } =20 static struct platform_driver rz_sysc_driver =3D { diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 56bc047a1bff..447008140634 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -9,6 +9,7 @@ #define __SOC_RENESAS_RZ_SYSC_H__ =20 #include +#include #include #include =20 @@ -34,9 +35,11 @@ struct rz_sysc_soc_id_init_data { /** * struct rz_sysc_init_data - RZ SYSC initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data + * @regmap_cfg: SoC-specific regmap config */ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; + const struct regmap_config *regmap_cfg; }; =20 extern const struct rz_sysc_init_data rzg3e_sys_init_data; --=20 2.25.1 From nobody Fri Dec 19 13:08:33 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1D0CF1A5B96; Thu, 22 May 2025 18:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938212; cv=none; b=rQMiAfIn3dxYHxfqyb2Q7AKd/v+1YnUhK7+t1vZpfenkOA7/c8Q4++dSn9XpnimPGZ3zVsdp+7P0v20MBPcpEV7MufjMxdkeG8Saejlzerd9V9UJxSazqzLeIzD1y+YlMk7ig3tlhYnmpOcFhYYEIpthn+DrusW2MjIOE7CBq94= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938212; c=relaxed/simple; bh=gaq64C7OjhX21LSbw0E0wC5kTMeUyn4AR8ODhOLT3hE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GNa3BXlAsLSfcDmNnexaWZX6NnMJnRzYNofA3eSCDPCdAs37cuYuyghA8D5IiN/7nhFlooyhyCXkuE8eopjPLH1I0HV965iIs1LClKZxxh7MZFYyPvlU/O7iQKxmwdXXxcqlqFuPaZLVaTBgtmstOrGFYDIyv44OQso0wdEDVbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 2D9ED9aQT6mqZFMv7K/zww== X-CSE-MsgGUID: fPfiYlZ/RsywPEvouBECVw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 May 2025 03:23:26 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.203]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 32A5540621D6; Fri, 23 May 2025 03:23:20 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, rafael@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, niklas.soderlund+renesas@ragnatech.se, Krzysztof Kozlowski Subject: [PATCH v6 2/5] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit Date: Thu, 22 May 2025 20:22:45 +0200 Message-ID: <20250522182252.1593159-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> References: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel (channel 1) for temperature sensing. Reviewed-by: Krzysztof Kozlowski Signed-off-by: John Madieu --- Changes: v1 -> v2: * Fixes reg property specifier to get rid of yamlint warnings * Fixes IRQ name to reflect TSU expectations v2 -> v3: * Removees useless 'renesas,tsu-operating-mode' property=20 v3 -> v4: * Fixes commit message * Fixes interrupt description * Removes trip point definition v5: no changes v6: no changes .../thermal/renesas,r9a09g047-tsu.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09= g047-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml new file mode 100644 index 000000000000..ef9308089bfc --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Temperature Sensor Unit (TSU) + +maintainers: + - John Madieu + +description: + The Temperature Sensor Unit (TSU) is an integrated thermal sensor that + monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides + real-time temperature measurements for thermal management. + +properties: + compatible: + const: renesas,r9a09g047-tsu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: Conversion complete interrupt signal (pulse) + - description: Comparison result interrupt signal (level) + + interrupt-names: + items: + - const: adi + - const: adcmpi + + "#thermal-sensor-cells": + const: 0 + + renesas,tsu-calibration-sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the system controller (sys) that contains the TSU + calibration values used for temperature calculations. + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - renesas,tsu-calibration-sys + +additionalProperties: false + +examples: + - | + #include + #include + + tsu: thermal@14002000 { + compatible =3D "renesas,r9a09g047-tsu"; + reg =3D <0x14002000 0x1000>; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + #thermal-sensor-cells =3D <0>; + renesas,tsu-calibration-sys =3D <&sys>; + }; --=20 2.25.1 From nobody Fri Dec 19 13:08:33 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 984291B3929; Thu, 22 May 2025 18:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938215; cv=none; b=TSj2BV/LgSnpG7IUDxn9URkNnj6xQ33fyv96w59GL4da9ye1srGP/WLyaqwI+CzzRqtSWrac0m3zITE4h+Gp2EdT45qdIVotrHfaJkHa3QBo8BcwmiRdyL6PVU9cwg+5BTqNUNlzs3cOcsybCVDhvIHN6pmL0CM6PVv7BOKn3Ak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938215; c=relaxed/simple; bh=6QrsKbGb0fjkRTfK5uiOT0bkcav4MBRBnTftcjkBDkI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f/u19cG1rmZi4WH1BkLKbNg1LBW5hlkog8CFln2ScE52x+EKF8gDl8EAz2eAJkxYz4rHBBzwcymE9+jJgVLerVJO+ReCsBXrRUF6QMQsyMv1tIvMP+jfi+Jtcw+k0pihoKkRsyOuG16faPRX3llcn277a8L9xtOlAZihHE+HIkk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: wzGw4GCcQoWD+Oz9OKIsCg== X-CSE-MsgGUID: dPfYPwodTmaiCrIzqQgyAg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 May 2025 03:23:32 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.203]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2BBC840621D6; Fri, 23 May 2025 03:23:26 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, rafael@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, niklas.soderlund+renesas@ragnatech.se Subject: [PATCH v6 3/5] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC Date: Thu, 22 May 2025 20:22:46 +0200 Message-ID: <20250522182252.1593159-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> References: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed to monitor the chip's junction temperature. This sensor is connected to channel 1 of the APB port clock/reset and provides temperature measurements. It also requires calibration values stored in the system controller registe= rs for accurate temperature measurement. Add a driver for the Renesas RZ/G3E T= SU. Signed-off-by: John Madieu --- Changes: v1 -> v2: fixes IRQ names v2 -> v3: no changes v3 -> v4: no changes v5: removes curly braces arround single-line protected scoped guards v6: Clarified comments in driver MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 7 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3e_thermal.c | 443 ++++++++++++++++++++++++ 4 files changed, 458 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index 79a8e2c73908..eb11494795e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21161,6 +21161,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c =20 +RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER +M: John Madieu +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +F: drivers/thermal/renesas/rzg3e_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kcon= fig index dcf5fc5ae08e..10cf90fc4bfa 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,10 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3E_THERMAL + tristate "Renesas RZ/G3E thermal driver" + depends on ARCH_RENESAS || COMPILE_TEST + help + Enable this to plug the RZ/G3E thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Mak= efile index bf9cb3cb94d6..5a3eba0dedd0 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) +=3D rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) +=3D rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) +=3D rzg2l_thermal.o +obj-$(CONFIG_RZG3E_THERMAL) +=3D rzg3e_thermal.o diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c new file mode 100644 index 000000000000..348229da9ef4 --- /dev/null +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3E TSU Temperature Sensor Unit + * + * Copyright (C) 2025 Renesas Electronics Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +/* SYS Trimming register offsets macro */ +#define SYS_TSU_TRMVAL(x) (0x330 + (x) * 4) + +/* TSU Register offsets and bits */ +#define TSU_SSUSR 0x00 +#define TSU_SSUSR_EN_TS BIT(0) +#define TSU_SSUSR_ADC_PD_TS BIT(1) +#define TSU_SSUSR_SOC_TS_EN BIT(2) + +#define TSU_STRGR 0x04 +#define TSU_STRGR_ADST BIT(0) + +#define TSU_SOSR1 0x08 +#define TSU_SOSR1_ADCT_8 0x03 +#define TSU_SOSR1_OUTSEL_AVERAGE BIT(9) + +/* Sensor Code Read Register */ +#define TSU_SCRR 0x10 +#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0) + +/* Sensor Status Register */ +#define TSU_SSR 0x14 +#define TSU_SSR_CONV_RUNNING BIT(0) + +/* Compare Mode Setting Register */ +#define TSU_CMSR 0x18 +#define TSU_CMSR_CMPEN BIT(0) +#define TSU_CMSR_CMPCOND BIT(1) + +/* Lower Limit Setting Register */ +#define TSU_LLSR 0x1C +#define TSU_LLSR_LIM GENMASK(11, 0) + +/* Upper Limit Setting Register */ +#define TSU_ULSR 0x20 +#define TSU_ULSR_ULIM GENMASK(11, 0) + +/* Interrupt Status Register */ +#define TSU_SISR 0x30 +#define TSU_SISR_ADF BIT(0) +#define TSU_SISR_CMPF BIT(1) + +/* Interrupt Enable Register */ +#define TSU_SIER 0x34 +#define TSU_SIER_ADIE BIT(0) +#define TSU_SIER_CMPIE BIT(1) + +/* Interrupt Clear Register */ +#define TSU_SICR 0x38 +#define TSU_SICR_ADCLR BIT(0) +#define TSU_SICR_CMPCLR BIT(1) + +/* Temperature calculation constants */ +#define TSU_D 41 +#define TSU_E 126 +#define TSU_TRMVAL_MASK GENMASK(11, 0) + +#define TSU_POLL_DELAY_US 50 +#define TSU_TIMEOUT_US 10000 +#define TSU_MIN_CLOCK_RATE 24000000 + +/** + * struct rzg3e_thermal_priv - RZ/G3E thermal private data structure + * @base: TSU base address + * @dev: device pointer + * @syscon: regmap for calibration values + * @zone: thermal zone pointer + * @mode: current tzd mode + * @conv_complete: ADC conversion completion + * @reg_lock: protect shared register access + * @cached_temp: last computed temperature (milliCelsius) + * @trmval: trim (calibration) values + */ +struct rzg3e_thermal_priv { + void __iomem *base; + struct device *dev; + struct regmap *syscon; + struct thermal_zone_device *zone; + enum thermal_device_mode mode; + struct completion conv_complete; + spinlock_t reg_lock; + int cached_temp; + u32 trmval[2]; +}; + +static void rzg3e_thermal_hw_disable(struct rzg3e_thermal_priv *priv) +{ + /* Disable all interrupts first */ + writel(0, priv->base + TSU_SIER); + /* Clear any pending interrupts */ + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); + /* Put device in power down */ + writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR); +} + +static void rzg3e_thermal_hw_enable(struct rzg3e_thermal_priv *priv) +{ + /* First clear any pending status */ + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); + /* Disable all interrupts */ + writel(0, priv->base + TSU_SIER); + + /* Enable thermal sensor */ + writel(TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS, priv->base + TSU_SSUSR); + /* Setup for averaging mode with 8 samples */ + writel(TSU_SOSR1_OUTSEL_AVERAGE | TSU_SOSR1_ADCT_8, priv->base + TSU_SOSR= 1); +} + +static irqreturn_t rzg3e_thermal_cmp_irq(int irq, void *dev_id) +{ + struct rzg3e_thermal_priv *priv =3D dev_id; + u32 status; + + status =3D readl(priv->base + TSU_SISR); + if (!(status & TSU_SISR_CMPF)) + return IRQ_NONE; + + /* Clear the comparison interrupt flag */ + writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t rzg3e_thermal_cmp_threaded_irq(int irq, void *dev_id) +{ + struct rzg3e_thermal_priv *priv =3D dev_id; + + thermal_zone_device_update(priv->zone, THERMAL_EVENT_UNSPECIFIED); + return IRQ_HANDLED; +} + +static irqreturn_t rzg3e_thermal_adc_irq(int irq, void *dev_id) +{ + struct rzg3e_thermal_priv *priv =3D dev_id; + u32 status; + u32 result; + + /* Check if this is our interrupt */ + status =3D readl(priv->base + TSU_SISR); + if (!(status & TSU_SISR_ADF)) + return IRQ_NONE; + + /* Disable all interrupts */ + writel(0, priv->base + TSU_SIER); + /* Clear conversion complete interrupt */ + writel(TSU_SICR_ADCLR, priv->base + TSU_SICR); + + /* Read ADC conversion result */ + result =3D readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS; + + /* + * Calculate temperature using compensation formula + * Section 7.11.7.8 (Temperature Compensation Calculation) + * + * T(=C2=B0C) =3D ((e - d) / (c -b)) * (a - b) + d + * + * a =3D 12 bits temperature code read from the sensor + * b =3D SYS trmval[0] + * c =3D SYS trmval[1] + * d =3D -41 + * e =3D 126 + */ + s64 temp_val =3D div_s64(((TSU_E + TSU_D) * (s64)(result - priv->trmval[0= ])), + priv->trmval[1] - priv->trmval[0]) - TSU_D; + int new_temp =3D temp_val * MILLIDEGREE_PER_DEGREE; + + scoped_guard(spinlock_irqsave, &priv->reg_lock) + priv->cached_temp =3D new_temp; + + complete(&priv->conv_complete); + + return IRQ_HANDLED; +} + +static int rzg3e_thermal_get_temp(struct thermal_zone_device *zone, int *t= emp) +{ + struct rzg3e_thermal_priv *priv =3D thermal_zone_device_priv(zone); + u32 val; + int ret; + + if (priv->mode =3D=3D THERMAL_DEVICE_DISABLED) + return -EBUSY; + + reinit_completion(&priv->conv_complete); + + /* Enable ADC interrupt */ + writel(TSU_SIER_ADIE, priv->base + TSU_SIER); + + /* Verify no ongoing conversion */ + ret =3D readl_poll_timeout_atomic(priv->base + TSU_SSR, val, + !(val & TSU_SSR_CONV_RUNNING), + TSU_POLL_DELAY_US, TSU_TIMEOUT_US); + if (ret) { + dev_err(priv->dev, "ADC conversion timed out\n"); + return ret; + } + + /* Start conversion */ + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); + + if (!wait_for_completion_timeout(&priv->conv_complete, + msecs_to_jiffies(100))) { + dev_err(priv->dev, "ADC conversion completion timeout\n"); + return -ETIMEDOUT; + } + + scoped_guard(spinlock_irqsave, &priv->reg_lock) + *temp =3D priv->cached_temp; + + return 0; +} + +/* Convert temperature in milliCelsius to raw sensor code */ +static int rzg3e_temp_to_raw(struct rzg3e_thermal_priv *priv, int temp_mc) +{ + s64 raw =3D div_s64(((temp_mc / 1000) - TSU_D) * + (priv->trmval[1] - priv->trmval[0]), + (TSU_E - TSU_D)); + return clamp_val(raw, 0, 0xFFF); +} + +static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz, int low= , int high) +{ + struct rzg3e_thermal_priv *priv =3D thermal_zone_device_priv(tz); + int ret; + int val; + + if (low >=3D high) + return -EINVAL; + + if (priv->mode =3D=3D THERMAL_DEVICE_DISABLED) + return -EBUSY; + + /* Set up comparison interrupt */ + writel(0, priv->base + TSU_SIER); + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); + + /* Set thresholds */ + writel(rzg3e_temp_to_raw(priv, low), priv->base + TSU_LLSR); + writel(rzg3e_temp_to_raw(priv, high), priv->base + TSU_ULSR); + + /* Configure comparison: + * - Enable comparison function (CMPEN =3D 1) + * - Set comparison condition (CMPCOND =3D 0 for out of range) + */ + writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR); + + /* Enable comparison irq */ + writel(TSU_SIER_CMPIE, priv->base + TSU_SIER); + + /* Verify no ongoing conversion */ + ret =3D readl_poll_timeout_atomic(priv->base + TSU_SSR, val, + !(val & TSU_SSR_CONV_RUNNING), + TSU_POLL_DELAY_US, TSU_TIMEOUT_US); + if (ret) { + dev_err(priv->dev, "ADC conversion timed out\n"); + return ret; + } + + /* Start a conversion to trigger comparison */ + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); + + return 0; +} + +static int rzg3e_thermal_get_trimming(struct rzg3e_thermal_priv *priv) +{ + int ret; + + ret =3D regmap_read(priv->syscon, SYS_TSU_TRMVAL(0), &priv->trmval[0]); + if (ret) + return ret; + + ret =3D regmap_read(priv->syscon, SYS_TSU_TRMVAL(1), &priv->trmval[1]); + if (ret) + return ret; + + priv->trmval[0] &=3D TSU_TRMVAL_MASK; + priv->trmval[1] &=3D TSU_TRMVAL_MASK; + + if (!priv->trmval[0] || !priv->trmval[1]) + return dev_err_probe(priv->dev, -EINVAL, "invalid trimming values"); + + return 0; +} + +static int rzg3e_thermal_change_mode(struct thermal_zone_device *tz, + enum thermal_device_mode mode) +{ + struct rzg3e_thermal_priv *priv =3D thermal_zone_device_priv(tz); + + if (mode =3D=3D THERMAL_DEVICE_DISABLED) + rzg3e_thermal_hw_disable(priv); + else + rzg3e_thermal_hw_enable(priv); + + priv->mode =3D mode; + return 0; +} + +static const struct thermal_zone_device_ops rzg3e_tz_of_ops =3D { + .get_temp =3D rzg3e_thermal_get_temp, + .set_trips =3D rzg3e_thermal_set_trips, + .change_mode =3D rzg3e_thermal_change_mode, +}; + +static int rzg3e_thermal_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rzg3e_thermal_priv *priv; + struct reset_control *rstc; + char *adc_name, *cmp_name; + int adc_irq, cmp_irq; + struct clk *clk; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return dev_err_probe(dev, PTR_ERR(priv->base), + "Failed to map I/O memory"); + + priv->syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "renesas,tsu-calibration-sys"); + if (IS_ERR(priv->syscon)) + return dev_err_probe(dev, PTR_ERR(priv->syscon), + "Failed to get calibration syscon"); + + adc_irq =3D platform_get_irq_byname(pdev, "adi"); + if (adc_irq < 0) + return adc_irq; + + cmp_irq =3D platform_get_irq_byname(pdev, "adcmpi"); + if (cmp_irq < 0) + return cmp_irq; + + rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), + "Failed to acquire deasserted reset"); + + platform_set_drvdata(pdev, priv); + + spin_lock_init(&priv->reg_lock); + init_completion(&priv->conv_complete); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get and enable clock"); + + if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE) + return dev_err_probe(dev, -EINVAL, + "Clock rate too low (minimum %d Hz required)", + TSU_MIN_CLOCK_RATE); + + ret =3D rzg3e_thermal_get_trimming(priv); + if (ret) + return ret; + + adc_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s-adc", dev_name(dev)); + if (!adc_name) + return -ENOMEM; + + cmp_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s-cmp", dev_name(dev)); + if (!cmp_name) + return -ENOMEM; + + /* Unit in a known disabled mode */ + rzg3e_thermal_hw_disable(priv); + + ret =3D devm_request_irq(dev, adc_irq, rzg3e_thermal_adc_irq, + IRQF_TRIGGER_RISING, adc_name, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request ADC IRQ"); + + ret =3D devm_request_threaded_irq(dev, cmp_irq, rzg3e_thermal_cmp_irq, + rzg3e_thermal_cmp_threaded_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + cmp_name, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request comparison IRQ"); + + /* Register Thermal Zone */ + priv->zone =3D devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_of_o= ps); + if (IS_ERR(priv->zone)) + return dev_err_probe(dev, PTR_ERR(priv->zone), + "Failed to register thermal zone"); + + ret =3D devm_thermal_add_hwmon_sysfs(dev, priv->zone); + if (ret) + return dev_err_probe(dev, ret, "Failed to add hwmon sysfs"); + + return 0; +} + +static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { + { .compatible =3D "renesas,r9a09g047-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); + +static struct platform_driver rzg3e_thermal_driver =3D { + .driver =3D { + .name =3D "rzg3e_thermal", + .of_match_table =3D rzg3e_thermal_dt_ids, + }, + .probe =3D rzg3e_thermal_probe, +}; +module_platform_driver(rzg3e_thermal_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver"); +MODULE_AUTHOR("John Madieu "); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Fri Dec 19 13:08:33 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D96001C84DE; Thu, 22 May 2025 18:23:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938221; cv=none; b=cJNIso/YW9L9qSututRY8dsqgR32pJtPWT8FhHlD+nyDJ8eql1g3A4vGIwyLL/8A0lJVmZG9qQYc/Jt1e+U/gTy79jUsSEP4hyND8mbLDveSvbzlvc3nViiOay5D7VaRm3jsYUbVGfpjVlPwwA8zYb+t5C7wr0RtdddZcrZs8dE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938221; c=relaxed/simple; bh=CPgLXJqtLmtduRTiBW7NxtXiBBy9O7gWE7UIL3aUTXY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFsPHSXk6KZC+rLmPYg562Kgy7+gWHf/raJ4xlYSfV+4X5KXatOzC1CNXUqR3ehB77eaXbzma+QeHKTVsAx04VIidHzxbmUtIWA8mD4fu63Kr//igPDr6FdCWejwaPZKTLz341h45G+EJSEPyjw3SxB/jsihfizI96YI4DrUTSM= ARC-Authentication-Results: i=1; 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charset="utf-8" Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. Signed-off-by: John Madieu --- Changes: v1 -> v2: Fix IRQ names v2 -> v3: remove useless 'renesas,tsu-operating-mode' property' v3 -> v4: no changes v5: no changes v6: no changes arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 876f70fed433..535da0292d91 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -74,6 +75,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -84,6 +86,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -94,6 +97,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -391,6 +395,19 @@ wdt3: watchdog@13000400 { status =3D "disabled"; }; =20 + tsu: thermal@14002000 { + compatible =3D "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-calibration-sys =3D <&sys>; + }; + i2c0: i2c@14400400 { compatible =3D "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg =3D <0 0x14400400 0 0x400>; @@ -671,6 +688,37 @@ sdhi2_vqmmc: vqmmc-regulator { }; }; =20 + thermal-zones { + cpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor_crit: sensor-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, --=20 2.25.1 From nobody Fri Dec 19 13:08:33 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C97A71A9B39; Thu, 22 May 2025 18:23:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747938226; cv=none; b=b1Oy3QG3SlrOZr+vS1Hkz5W8BsVCsjG8z51mjxZopVWW9UwICuy77oBsy8lqIKSu9OSb4GXXF1xPz6/HRDy6YyefnaLcSx8mRiCMhVo7Vxa2I8Wmrtf6fqFfGx0mKL2cy7fnVylcfkCZ3pAyWjfc+Xdv4NMJPiLELwV8CF5qXow= ARC-Message-Signature: i=1; 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Fri, 23 May 2025 03:23:38 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, rafael@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, niklas.soderlund+renesas@ragnatech.se, Krzysztof Kozlowski Subject: [PATCH v6 5/5] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver Date: Thu, 22 May 2025 20:22:48 +0200 Message-ID: <20250522182252.1593159-6-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> References: <20250522182252.1593159-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Renesas RZ/G3E thermal driver, as used on the Renesas RZ/G3E SMARC EVK board. Reviewed-by: Krzysztof Kozlowski Signed-off-by: John Madieu --- Changes: v1 -> v2: no changes v2 -> v3: no changes v3 -> v4: update commit message v5: no changes v6: no changes arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 368c242fe945..1b9ceab54408 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -720,6 +720,7 @@ CONFIG_ROCKCHIP_THERMAL=3Dm CONFIG_RCAR_THERMAL=3Dy CONFIG_RCAR_GEN3_THERMAL=3Dy CONFIG_RZG2L_THERMAL=3Dy +CONFIG_RZG3E_THERMAL=3Dy CONFIG_ARMADA_THERMAL=3Dy CONFIG_MTK_THERMAL=3Dm CONFIG_MTK_LVTS_THERMAL=3Dm --=20 2.25.1