From nobody Fri Dec 19 14:51:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20BE7289813; Thu, 22 May 2025 16:35:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747931758; cv=none; b=VwxpzHZpuztYbDnKzuN7pltXheSMaSSUOMn1O8pVdVzBsFGDaUN6CGgmWmWNqkufRHln7CCqhL4emXRnfeV4ECVp4jTOCvjI57AIi8y+BS7QpXijee9tnHsVrNGPx8SEaB3lQH8JoZaHLohcFpHHEv+M9YlR29DPR33bhbfMtOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747931758; c=relaxed/simple; bh=L4XK2uId23bQjcHrmh4RiEn3RDvT+HP/4IuSP51IJ/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ed24kV6NlKKlWo2KsCFXZ1OAh1AOpzM+Go42Q/CljtliPhTw3/12HryQUUjqHTSM38XgWATEZouwQaITE+aJ9vCpbk4Djc5zla1T9qfeOfAoOXQusoSwmcuA5UqYXnxBCSHts0R/srkDL+D3wn/WGJs89SAtw4sUqsVpeygIiQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=neO/XT0A; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="neO/XT0A" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747931756; x=1779467756; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L4XK2uId23bQjcHrmh4RiEn3RDvT+HP/4IuSP51IJ/I=; b=neO/XT0A/pvyzNZN+cmsjesJ/kWk7HcWt8CrDaiTo2bzMqiEAgF5vhfo EnYCBo8RL5S0JmHGHWN/q2O6oAWlAdsbxsgSeiDnj/cXSSb6sYNrA2oR0 L4TX0A/H3JGDgex7kF868AyVnu6l4O429HI7T5LKGmEzuQBz3DrRvjrTM baWPtL9J420Y5ZPjGG22FtNme14irUre9A56FrmmNRjoIDLsFjb5++QCA FJxU6/JOsYngIp/3/UL3gIJnGD0/Iak91/8mH2g4td2RJFLRbwnVoKh79 cfyrG/DpC3l7+zimSiBOGjwYFA4ZXon81Hz0NvHYww939hjgntVjarl1X w==; X-CSE-ConnectionGUID: nio5+1UvQkWAKnef+y1iYQ== X-CSE-MsgGUID: NLzfhcmQQuW6YQU422mdvg== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="49889051" X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="49889051" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 09:35:56 -0700 X-CSE-ConnectionGUID: 3y7wTD1IQiaP7wSqZn2tIg== X-CSE-MsgGUID: tyoTmrsxTWm+7sEUNIOdNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="145631381" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by orviesa004.jf.intel.com with ESMTP; 22 May 2025 09:35:51 -0700 From: Arkadiusz Kubalewski To: donald.hunter@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, jiri@resnulli.us, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, andrew+netdev@lunn.ch, aleksandr.loktionov@intel.com, corbet@lwn.net Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-rdma@vger.kernel.org, linux-doc@vger.kernel.org, Arkadiusz Kubalewski , Milena Olech Subject: [PATCH net-next v3 2/3] dpll: add reference sync get/set Date: Thu, 22 May 2025 18:29:37 +0200 Message-Id: <20250522162938.1490791-3-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250522162938.1490791-1-arkadiusz.kubalewski@intel.com> References: <20250522162938.1490791-1-arkadiusz.kubalewski@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define function for reference sync pin registration and callback ops to set/get current feature state. Implement netlink handler to fill netlink messages with reference sync pin configuration of capable pins (pin-get). Implement netlink handler to call proper ops and configure reference sync pin state (pin-set). Reviewed-by: Przemek Kitszel Reviewed-by: Milena Olech Signed-off-by: Arkadiusz Kubalewski --- v3: - fix kdoc missing ':' after argument name ref_sync_pins, - propagate ret in dpll_pin_ref_sync_state_set(). --- drivers/dpll/dpll_core.c | 27 ++++++ drivers/dpll/dpll_core.h | 2 + drivers/dpll/dpll_netlink.c | 188 ++++++++++++++++++++++++++++++++---- include/linux/dpll.h | 10 ++ 4 files changed, 209 insertions(+), 18 deletions(-) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index 20bdc52f63a5..805c7aca58c5 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -506,6 +506,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, refcount_set(&pin->refcount, 1); xa_init_flags(&pin->dpll_refs, XA_FLAGS_ALLOC); xa_init_flags(&pin->parent_refs, XA_FLAGS_ALLOC); + xa_init_flags(&pin->ref_sync_pins, XA_FLAGS_ALLOC); ret =3D xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b, &dpll_pin_xa_id, GFP_KERNEL); if (ret < 0) @@ -514,6 +515,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, err_xa_alloc: xa_destroy(&pin->dpll_refs); xa_destroy(&pin->parent_refs); + xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); err_pin_prop: kfree(pin); @@ -595,6 +597,7 @@ void dpll_pin_put(struct dpll_pin *pin) xa_erase(&dpll_pin_xa, pin->id); xa_destroy(&pin->dpll_refs); xa_destroy(&pin->parent_refs); + xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); kfree_rcu(pin, rcu); } @@ -783,6 +786,30 @@ void dpll_pin_on_pin_unregister(struct dpll_pin *paren= t, struct dpll_pin *pin, } EXPORT_SYMBOL_GPL(dpll_pin_on_pin_unregister); =20 +/** + * dpll_pin_ref_sync_pair_add - create a reference sync signal pin pair + * @base: pin which produces the base frequency + * @sync: pin which produces the sync signal + * + * Once pins are paired, the user-space configuration of reference sync pa= ir + * is possible. + * Context: Acquires a lock (dpll_lock) + * Return: + * * 0 on success + * * negative - error value + */ +int dpll_pin_ref_sync_pair_add(struct dpll_pin *base, struct dpll_pin *syn= c) +{ + int ret; + + mutex_lock(&dpll_lock); + ret =3D xa_insert(&base->ref_sync_pins, sync->pin_idx, sync, GFP_KERNEL); + mutex_unlock(&dpll_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dpll_pin_ref_sync_pair_add); + static struct dpll_device_registration * dpll_device_registration_first(struct dpll_device *dpll) { diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h index 2b6d8ef1cdf3..93c68e78b351 100644 --- a/drivers/dpll/dpll_core.h +++ b/drivers/dpll/dpll_core.h @@ -44,6 +44,7 @@ struct dpll_device { * @module: module of creator * @dpll_refs: hold referencees to dplls pin was registered with * @parent_refs: hold references to parent pins pin was registered with + * @ref_sync_pins: hold references to pins for Reference SYNC feature * @prop: pin properties copied from the registerer * @rclk_dev_name: holds name of device when pin can recover clock from it * @refcount: refcount @@ -56,6 +57,7 @@ struct dpll_pin { struct module *module; struct xarray dpll_refs; struct xarray parent_refs; + struct xarray ref_sync_pins; struct dpll_pin_properties prop; refcount_t refcount; struct rcu_head rcu; diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index c130f87147fa..854bd46a7d27 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -48,6 +48,24 @@ dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 = id) return 0; } =20 +static bool dpll_pin_available(struct dpll_pin *pin) +{ + struct dpll_pin_ref *par_ref; + unsigned long i; + + if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) + return false; + xa_for_each(&pin->parent_refs, i, par_ref) + if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, + DPLL_REGISTERED)) + return true; + xa_for_each(&pin->dpll_refs, i, par_ref) + if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, + DPLL_REGISTERED)) + return true; + return false; +} + /** * dpll_msg_add_pin_handle - attach pin handle attribute to a given message * @msg: pointer to sk_buff message to attach a pin handle @@ -408,6 +426,47 @@ dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpl= l_pin *pin, return -EMSGSIZE; } =20 +static int +dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, + struct dpll_pin_ref *ref, + struct netlink_ext_ack *extack) +{ + const struct dpll_pin_ops *ops =3D dpll_pin_ops(ref); + struct dpll_device *dpll =3D ref->dpll; + enum dpll_pin_state state; + void *pin_priv, *sp_priv; + struct dpll_pin *sp; + struct nlattr *nest; + unsigned long index; + int ret; + + pin_priv =3D dpll_pin_on_dpll_priv(dpll, pin); + xa_for_each(&pin->ref_sync_pins, index, sp) { + if (!dpll_pin_available(sp)) + continue; + sp_priv =3D dpll_pin_on_dpll_priv(dpll, sp); + if (WARN_ON(!ops->ref_sync_get)) + return -EOPNOTSUPP; + ret =3D ops->ref_sync_get(pin, pin_priv, sp, sp_priv, + &state, extack); + if (ret) + return ret; + nest =3D nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); + if (!nest) + return -EMSGSIZE; + if (nla_put_s32(msg, DPLL_A_PIN_ID, sp->id)) + goto nest_cancel; + if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) + goto nest_cancel; + nla_nest_end(msg, nest); + } + return 0; + +nest_cancel: + nla_nest_cancel(msg, nest); + return -EMSGSIZE; +} + static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) { int fs; @@ -550,6 +609,10 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_= pin *pin, if (ret) return ret; ret =3D dpll_msg_add_pin_esync(msg, pin, ref, extack); + if (ret) + return ret; + if (!xa_empty(&pin->ref_sync_pins)) + ret =3D dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); if (ret) return ret; if (xa_empty(&pin->parent_refs)) @@ -642,24 +705,6 @@ __dpll_device_change_ntf(struct dpll_device *dpll) return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); } =20 -static bool dpll_pin_available(struct dpll_pin *pin) -{ - struct dpll_pin_ref *par_ref; - unsigned long i; - - if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) - return false; - xa_for_each(&pin->parent_refs, i, par_ref) - if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, - DPLL_REGISTERED)) - return true; - xa_for_each(&pin->dpll_refs, i, par_ref) - if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, - DPLL_REGISTERED)) - return true; - return false; -} - /** * dpll_device_change_ntf - notify that the dpll device has been changed * @dpll: registered dpll pointer @@ -887,6 +932,108 @@ dpll_pin_esync_set(struct dpll_pin *pin, struct nlatt= r *a, return ret; } =20 +static int +dpll_pin_ref_sync_state_set(struct dpll_pin *pin, unsigned long sync_pin_i= dx, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack) + +{ + struct dpll_pin_ref *ref, *failed; + const struct dpll_pin_ops *ops; + enum dpll_pin_state old_state; + struct dpll_pin *sync_pin; + struct dpll_device *dpll; + unsigned long i; + int ret; + + if (state !=3D DPLL_PIN_STATE_CONNECTED && + state !=3D DPLL_PIN_STATE_DISCONNECTED) + return -EINVAL; + sync_pin =3D xa_find(&pin->ref_sync_pins, &sync_pin_idx, ULONG_MAX, + XA_PRESENT); + if (!sync_pin) { + NL_SET_ERR_MSG(extack, "reference sync pin not found"); + return -EINVAL; + } + if (!dpll_pin_available(sync_pin)) { + NL_SET_ERR_MSG(extack, "reference sync pin not available"); + return -EINVAL; + } + ref =3D dpll_xa_ref_dpll_first(&pin->dpll_refs); + ASSERT_NOT_NULL(ref); + ops =3D dpll_pin_ops(ref); + if (!ops->ref_sync_set || !ops->ref_sync_get) { + NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); + return -EOPNOTSUPP; + } + dpll =3D ref->dpll; + ret =3D ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), sync_pin, + dpll_pin_on_dpll_priv(dpll, sync_pin), + &old_state, extack); + if (ret) { + NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); + return ret; + } + if (state =3D=3D old_state) + return 0; + xa_for_each(&pin->dpll_refs, i, ref) { + ops =3D dpll_pin_ops(ref); + dpll =3D ref->dpll; + ret =3D ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), + sync_pin, + dpll_pin_on_dpll_priv(dpll, sync_pin), + state, extack); + if (ret) { + failed =3D ref; + NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", + dpll->id); + goto rollback; + } + } + __dpll_pin_change_ntf(pin); + + return 0; + +rollback: + xa_for_each(&pin->dpll_refs, i, ref) { + if (ref =3D=3D failed) + break; + ops =3D dpll_pin_ops(ref); + dpll =3D ref->dpll; + if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), + sync_pin, + dpll_pin_on_dpll_priv(dpll, sync_pin), + old_state, extack)) + NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); + } + return ret; +} + +static int +dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, + struct netlink_ext_ack *extack) +{ + struct nlattr *tb[DPLL_A_PIN_MAX + 1]; + enum dpll_pin_state state; + u32 sync_pin_id; + + nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, + dpll_reference_sync_nl_policy, extack); + if (!tb[DPLL_A_PIN_ID]) { + NL_SET_ERR_MSG(extack, "sync pin id expected"); + return -EINVAL; + } + sync_pin_id =3D nla_get_u32(tb[DPLL_A_PIN_ID]); + + if (!tb[DPLL_A_PIN_STATE]) { + NL_SET_ERR_MSG(extack, "sync pin state expected"); + return -EINVAL; + } + state =3D nla_get_u32(tb[DPLL_A_PIN_STATE]); + + return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); +} + static int dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, enum dpll_pin_state state, @@ -1193,6 +1340,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struc= t genl_info *info) if (ret) return ret; break; + case DPLL_A_PIN_REFERENCE_SYNC: + ret =3D dpll_pin_ref_sync_set(pin, a, info->extack); + if (ret) + return ret; + break; } } =20 diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 5e4f9ab1cf75..f1f1fdda67fe 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -95,6 +95,14 @@ struct dpll_pin_ops { const struct dpll_device *dpll, void *dpll_priv, struct dpll_pin_esync *esync, struct netlink_ext_ack *extack); + int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack); + int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + enum dpll_pin_state *state, + struct netlink_ext_ack *extack); }; =20 struct dpll_pin_frequency { @@ -194,6 +202,8 @@ int dpll_pin_on_pin_register(struct dpll_pin *parent, s= truct dpll_pin *pin, void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *= pin, const struct dpll_pin_ops *ops, void *priv); =20 +int dpll_pin_ref_sync_pair_add(struct dpll_pin *base, struct dpll_pin *syn= c); + int dpll_device_change_ntf(struct dpll_device *dpll); =20 int dpll_pin_change_ntf(struct dpll_pin *pin); --=20 2.38.1