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Thu, 22 May 2025 09:09:55 -0700 (PDT) From: Cyril Bur To: samuel.holland@sifive.com, ben.dooks@codethink.co.uk, palmer@dabbelt.com, alex@ghiti.fr, linux-kernel@vger.kernel.org Cc: jszhang@kernel.org, paul.walmsley@sifive.com, charlie@rivosinc.com, jrtc27@jrtc27.com, aou@eecs.berkeley.edu Subject: [PATCH] riscv: uaccess: Only restore the CSR_STATUS SUM bit Date: Thu, 22 May 2025 16:09:54 +0000 Message-Id: <20250522160954.429333-1-cyrilbur@tenstorrent.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During switch to csrs will OR the value of the register into the corresponding csr. In this case we're only interested in restoring the SUM bit not the entire register. Fixes: 788aa64c0 ("riscv: save the SR_SUM status over switches") Signed-off-by: Cyril Bur --- I've put the Fixes tag in but I assume this will get squashed into the patch. Either way I hope this works to fix the immediate issue. arch/riscv/kernel/entry.S | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 00bd0de9faa2..6ed3bd80903d 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -399,14 +399,18 @@ SYM_FUNC_START(__switch_to) REG_S s11, TASK_THREAD_S11_RA(a3) =20 /* save the user space access flag */ - li s0, SR_SUM - csrr s1, CSR_STATUS - REG_S s1, TASK_THREAD_STATUS_RA(a3) + csrr s0, CSR_STATUS + REG_S s0, TASK_THREAD_STATUS_RA(a3) =20 /* Save the kernel shadow call stack pointer */ scs_save_current - /* Restore context from next->thread */ + /* + * Restore context from next->thread. csrs will OR the bits from s0 and + * only want to restore the SR_SUM bit + */ REG_L s0, TASK_THREAD_STATUS_RA(a4) + li s1, SR_SUM + and s0, s0, s1 csrs CSR_STATUS, s0 REG_L ra, TASK_THREAD_RA_RA(a4) REG_L sp, TASK_THREAD_SP_RA(a4) --=20 2.34.1