From nobody Tue Dec 16 15:44:25 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 111E028FABB; Thu, 22 May 2025 15:10:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926642; cv=none; b=HLAv2Qpx0Aqla9ypXzFlNTFbYodoP2iC6e4Vp1FepRa3+aOs7NWGuojfB5XAdTvqyPDR0huWzauu2oY97vGcsq43aRSfAr6vEfljy+X3ksTpHg6xlQvSf0lfcZxnX4Nd9Yi0mIcbX+wQie0fw4FCtMq6EFpXIQ9ppvoDHS0sq+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926642; c=relaxed/simple; bh=mbg5ajRFMEDQQKFEx/vW+1u4KdIzkPdIQePGYoq58H4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gGzIngeJfdGZA+dkaJR1sJOMynmbtsWA8uwMRmUHHx0DpdfhO8e7Xt0owh2n7FFmi4boNZbG72LWykmoeAUV21+Zo4hm2+Nz43CHnkEHzw93Yf9BpYByLPDeBm/u3VZjqCKfkSSZweWr3nxJLnGwidVvN3Phbysa3d2lzEA2bZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FSU97JvM; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FSU97JvM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747926640; x=1779462640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mbg5ajRFMEDQQKFEx/vW+1u4KdIzkPdIQePGYoq58H4=; b=FSU97JvMoGx3jQ9V3WMfT218Ucg0LN8cgLDIKtasykfy6mqlKF1QS/4h Ez6LPP2JDB+4vMANFmjMezh7HPAzzU1sBv0bZjHNf5L2cgybw+Lwcuvm/ zkJ9weJ+w7+q/+R5o5RdJ0iOYHgrVyuRQ9g2JowRLtIqbizjFauX+jAXj fvHHbUbnKMrH3moK+SpcfT8jsHGCroxPpUuLB2egqpyzTXmK/ld1pkyQb CHgNrP/98GOLKeBYPFTyDSXKjrqZtimOjsWLcVPKNFJW9+adeDUFgNTvb gRyc9Dyp7xtqx0Es4Ld9matkmI6AgIe6J7ISgsg4/+gOfynOHffjsoZpR g==; X-CSE-ConnectionGUID: n3F10tDXScOUrA7Pb6ykwA== X-CSE-MsgGUID: +4EoEQ7mRFyfcv+rlGsxfA== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="61006662" X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="61006662" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:40 -0700 X-CSE-ConnectionGUID: PkLlwb8dQtWGXPOVveIQ0w== X-CSE-MsgGUID: CV2DO4OSTCi7yUHNGBPLlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="171627608" Received: from 984fee019967.jf.intel.com ([10.165.54.94]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:39 -0700 From: Chao Gao To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@linutronix.de, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com Cc: peterz@infradead.org, rick.p.edgecombe@intel.com, weijiang.yang@intel.com, john.allen@amd.com, bp@alien8.de, chang.seok.bae@intel.com, xin3.li@intel.com, Chao Gao , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Maxim Levitsky , Mitchell Levy , Kees Cook , Stanislav Spassov , Eric Biggers , Oleg Nesterov , Nikolay Borisov , Vignesh Balasubramanian Subject: [PATCH v8 1/6] x86/fpu/xstate: Differentiate default features for host and guest FPUs Date: Thu, 22 May 2025 08:10:04 -0700 Message-ID: <20250522151031.426788-2-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, guest and host FPUs share the same default features. However, the CET supervisor xstate is the first feature that needs to be enabled exclusively for guest FPUs. Enabling it for host FPUs leads to a waste of 24 bytes in the XSAVE buffer. To support "guest-only" features, add a new structure to hold the default features and sizes for guest FPUs to clearly differentiate them from those for host FPUs. Add two helpers to provide the default feature masks for guest and host FPUs. Default features are derived by applying the masks to the maximum supported features. Note that, 1) for now, guest_default_mask() and host_default_mask() are identical. This will change in a follow-up patch once guest permissions, default xfeatures, and fpstate size are all converted to use the guest defaults. 2) only supervisor features will diverge between guest FPUs and host FPUs, while user features will remain the same [1][2]. So, the new vcpu_fpu_config struct does not include default user features and size for the UABI buffer. An alternative approach is adding a guest_only_xfeatures member to fpu_kernel_cfg and adding two helper functions to calculate the guest default xfeatures and size. However, calculating these defaults at runtime would introduce unnecessary overhead. Suggested-by: Chang S. Bae Suggested-by: Sean Christopherson Signed-off-by: Chao Gao Link: https://lore.kernel.org/kvm/aAwdQ759Y6V7SGhv@google.com/ [1] Link: https://lore.kernel.org/kvm/9ca17e1169805f35168eb722734fbf3579187886.= camel@intel.com/ [2] Acked-by: Sean Christopherson Reviewed-by: John Allen --- v8: provide helpers to provide the default masks (Sean) v6: Drop vcpu_fpu_config.user_* (Rick) Reset guest default size when XSAVE is unavaiable or disabled (Chang) v5: Add a new vcpu_fpu_config instead of adding new members to fpu_state_config (Chang) Extract a helper to set default values (Chang) --- arch/x86/include/asm/fpu/types.h | 26 ++++++++++++++++++++++++++ arch/x86/kernel/fpu/core.c | 1 + arch/x86/kernel/fpu/init.c | 1 + arch/x86/kernel/fpu/xstate.c | 32 ++++++++++++++++++++++++++------ 4 files changed, 54 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index 1c94121acd3d..abd193a1a52e 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -551,6 +551,31 @@ struct fpu_guest { struct fpstate *fpstate; }; =20 +/* + * FPU state configuration data for fpu_guest. + * Initialized at boot time. Read only after init. + */ +struct vcpu_fpu_config { + /* + * @size: + * + * The default size of the register state buffer in guest FPUs. + * Includes all supported features except independent managed + * features and features which have to be requested by user space + * before usage. + */ + unsigned int size; + + /* + * @features: + * + * The default supported features bitmap in guest FPUs. Does not + * include independent managed features and features which have to + * be requested by user space before usage. + */ + u64 features; +}; + /* * FPU state configuration data. Initialized at boot time. Read only after= init. */ @@ -606,5 +631,6 @@ struct fpu_state_config { =20 /* FPU state configuration information */ extern struct fpu_state_config fpu_kernel_cfg, fpu_user_cfg; +extern struct vcpu_fpu_config guest_default_cfg; =20 #endif /* _ASM_X86_FPU_TYPES_H */ diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 1cda5b78540b..2cd5e1910ff8 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -36,6 +36,7 @@ DEFINE_PER_CPU(u64, xfd_state); /* The FPU state configuration data for kernel and user space */ struct fpu_state_config fpu_kernel_cfg __ro_after_init; struct fpu_state_config fpu_user_cfg __ro_after_init; +struct vcpu_fpu_config guest_default_cfg __ro_after_init; =20 /* * Represents the initial FPU state. It's mostly (but not completely) zero= es, diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 6bb3e35c40e2..e19660cdc70c 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -202,6 +202,7 @@ static void __init fpu__init_system_xstate_size_legacy(= void) fpu_kernel_cfg.default_size =3D size; fpu_user_cfg.max_size =3D size; fpu_user_cfg.default_size =3D size; + guest_default_cfg.size =3D size; } =20 /* diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 1c8410b68108..f15be5c3f0cc 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -742,6 +742,9 @@ static int __init init_xstate_size(void) fpu_user_cfg.default_size =3D xstate_calculate_size(fpu_user_cfg.default_features, false); =20 + guest_default_cfg.size =3D + xstate_calculate_size(guest_default_cfg.features, compacted); + return 0; } =20 @@ -762,6 +765,7 @@ static void __init fpu__init_disable_system_xstate(unsi= gned int legacy_size) fpu_kernel_cfg.default_size =3D legacy_size; fpu_user_cfg.max_size =3D legacy_size; fpu_user_cfg.default_size =3D legacy_size; + guest_default_cfg.size =3D legacy_size; =20 /* * Prevent enabling the static branch which enables writes to the @@ -772,6 +776,21 @@ static void __init fpu__init_disable_system_xstate(uns= igned int legacy_size) fpstate_reset(x86_task_fpu(current)); } =20 +static u64 __init host_default_mask(void) +{ + /* Exclude dynamic features, which require userspace opt-in. */ + return ~(u64)XFEATURE_MASK_USER_DYNAMIC; +} + +static u64 __init guest_default_mask(void) +{ + /* + * Exclude dynamic features, which require userspace opt-in even + * for KVM guests. + */ + return ~(u64)XFEATURE_MASK_USER_DYNAMIC; +} + /* * Enable and initialize the xsave feature. * Called once per system bootup. @@ -854,12 +873,13 @@ void __init fpu__init_system_xstate(unsigned int lega= cy_size) fpu_user_cfg.max_features =3D fpu_kernel_cfg.max_features; fpu_user_cfg.max_features &=3D XFEATURE_MASK_USER_SUPPORTED; =20 - /* Clean out dynamic features from default */ - fpu_kernel_cfg.default_features =3D fpu_kernel_cfg.max_features; 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a="61006674" X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="61006674" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:41 -0700 X-CSE-ConnectionGUID: 1xyfw2BKQAWavODZO3D9eg== X-CSE-MsgGUID: 7MDlzroFQqCxIxWUc7LaGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="171627614" Received: from 984fee019967.jf.intel.com ([10.165.54.94]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:40 -0700 From: Chao Gao To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@linutronix.de, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com Cc: peterz@infradead.org, rick.p.edgecombe@intel.com, weijiang.yang@intel.com, john.allen@amd.com, bp@alien8.de, chang.seok.bae@intel.com, xin3.li@intel.com, Chao Gao , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Stanislav Spassov , Eric Biggers , Oleg Nesterov , Kees Cook Subject: [PATCH v8 2/6] x86/fpu: Initialize guest FPU permissions from guest defaults Date: Thu, 22 May 2025 08:10:05 -0700 Message-ID: <20250522151031.426788-3-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, fpu->guest_perm is copied from fpu->perm, which is derived from fpu_kernel_cfg.default_features. Guest defaults were introduced to differentiate the features and sizes of host and guest FPUs. Copying guest FPU permissions from the host will lead to inconsistencies between the guest default features and permissions. Initialize guest FPU permissions from guest defaults instead of host defaults. This ensures that any changes to guest default features are automatically reflected in guest permissions, which in turn guarantees that fpstate_realloc() allocates a correctly sized XSAVE buffer for guest FPUs. Suggested-by: Chang S. Bae Signed-off-by: Chao Gao Reviewed-by: Rick Edgecombe Acked-by: Sean Christopherson Reviewed-by: John Allen --- v8: Refine the comment above fpu->guest_perm.__user_state_size v6: Drop vcpu_fpu_config.user_* and collect reviews (Rick) --- arch/x86/kernel/fpu/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 2cd5e1910ff8..c69432d0ee41 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -553,8 +553,14 @@ void fpstate_reset(struct fpu *fpu) fpu->perm.__state_perm =3D fpu_kernel_cfg.default_features; fpu->perm.__state_size =3D fpu_kernel_cfg.default_size; fpu->perm.__user_state_size =3D fpu_user_cfg.default_size; - /* Same defaults for guests */ - fpu->guest_perm =3D fpu->perm; + + fpu->guest_perm.__state_perm =3D guest_default_cfg.features; + fpu->guest_perm.__state_size =3D guest_default_cfg.size; + /* + * User features and sizes are always identical between host and + * guest FPUs, which allows for common guest and userspace ABI. + */ + fpu->guest_perm.__user_state_size =3D fpu_user_cfg.default_size; } =20 static inline void fpu_inherit_perms(struct fpu *dst_fpu) --=20 2.47.1 From nobody Tue Dec 16 15:44:25 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CABCA28FFF0; Thu, 22 May 2025 15:10:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926644; cv=none; b=LExZZTBdDyZ2Cc/DuQu9HM1n2nJv55lGHbgDyHd1v/lYVlmyoSJYuVA/TJ7EhrDOe45okzvIQkuZRxxBDLfjANwVPxVq/1qGnJrDGtay2DljFRZ5wh1wy0WQD026s9JEoXdUJ+PQXWVRxqD+II/ip365VAL6fvZz+P5BsEICD8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926644; c=relaxed/simple; bh=ZCWTG8k//Yf0VlgdUB1ffPihLYI2QfHtharumNInnA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gjN0G5Qo1faIZ3WCpNuunDz/6iOGqV8eLu6ov06oUVOLrL46gEeR/vStibf4p3l2AHcNq34BCV9fngxeXLEdkH4n3WvoEDDHnW8YjGypmVFwyY3OHCiNVPIwXw6K/zR0EXxFXF+HArDkPiuU3NrLsDd4rMlFioY1uziwh+bY17c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Cmzvo5Z4; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cmzvo5Z4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747926643; x=1779462643; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZCWTG8k//Yf0VlgdUB1ffPihLYI2QfHtharumNInnA4=; b=Cmzvo5Z4V6ai0oPuzXqkgU+Cp0ZxB/Pyd0TRdL1IcGpAqHpsvWWIfnpL hIgpbPUVKyUI3/BfrQfwS44yOEt+7ybVfKPaZuBp6OgH0JuCHbldTtOQI sccVUp1TGN9RSFcah1EN+PAzQ+fQSSrbe3UhIelUtimuut7bRS4Qf+T57 02fM4LPw01EqWhHoc52vn3FJcx4iYYTGBtimTYmTgmOxZkV2NaUcDtu7A l7NbAm4F9bSr11TNuz2U2BjiAPvXN/q8qIgEkHaaOuzRApsOc74zNEG/q AvMq7VukU/mknaDo35vpWUrEwrqYraY/ZygWFsVD3MH5WjvbaKq8QHBLk Q==; X-CSE-ConnectionGUID: skPkOL8wS9q69n7i6maucA== X-CSE-MsgGUID: 3/P/MK7lSTiC7nVrnue7QA== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="61006684" X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="61006684" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:42 -0700 X-CSE-ConnectionGUID: wRo1B/+4SgeJQSblCmpf9g== X-CSE-MsgGUID: NV9UzX07St+XkuGHGba+7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="171627618" Received: from 984fee019967.jf.intel.com ([10.165.54.94]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:41 -0700 From: Chao Gao To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@linutronix.de, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com Cc: peterz@infradead.org, rick.p.edgecombe@intel.com, weijiang.yang@intel.com, john.allen@amd.com, bp@alien8.de, chang.seok.bae@intel.com, xin3.li@intel.com, Chao Gao , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Kees Cook , Stanislav Spassov , Oleg Nesterov , Eric Biggers Subject: [PATCH v8 3/6] x86/fpu: Initialize guest fpstate and FPU pseudo container from guest defaults Date: Thu, 22 May 2025 08:10:06 -0700 Message-ID: <20250522151031.426788-4-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" fpu_alloc_guest_fpstate() currently uses host defaults to initialize guest fpstate and pseudo containers. Guest defaults were introduced to differentiate the features and sizes of host and guest FPUs. Switch to using guest defaults instead. Adjust __fpstate_reset() to handle different defaults for host and guest FPUs. And to distinguish between the types of FPUs, move the initialization of indicators (is_guest and is_valloc) before the reset. Suggested-by: Chang S. Bae Signed-off-by: Chao Gao Reviewed-by: Rick Edgecombe Acked-by: Sean Christopherson Reviewed-by: John Allen --- v8: tweak comment in __fpstate_reset() (Sean) v7: tweak __fpstate_reset() instead of adding a guest-specific reset function (Sean/Dave) v6: Drop vcpu_fpu_config.user_* (Rick) v5: init is_valloc/is_guest in the guest-specific reset function (Chang) --- arch/x86/kernel/fpu/core.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index c69432d0ee41..a5a9c55fcf83 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -236,19 +236,22 @@ bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) struct fpstate *fpstate; unsigned int size; =20 - size =3D fpu_kernel_cfg.default_size + ALIGN(offsetof(struct fpstate, reg= s), 64); + size =3D guest_default_cfg.size + ALIGN(offsetof(struct fpstate, regs), 6= 4); + fpstate =3D vzalloc(size); if (!fpstate) return false; =20 + /* Initialize indicators to reflect properties of the fpstate */ + fpstate->is_valloc =3D true; + fpstate->is_guest =3D true; + /* Leave xfd to 0 (the reset value defined by spec) */ __fpstate_reset(fpstate, 0); fpstate_init_user(fpstate); - fpstate->is_valloc =3D true; - fpstate->is_guest =3D true; =20 gfpu->fpstate =3D fpstate; - gfpu->xfeatures =3D fpu_kernel_cfg.default_features; + gfpu->xfeatures =3D guest_default_cfg.features; =20 /* * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state @@ -535,10 +538,22 @@ void fpstate_init_user(struct fpstate *fpstate) =20 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd) { - /* Initialize sizes and feature masks */ - fpstate->size =3D fpu_kernel_cfg.default_size; + /* + * Supervisor features (and thus sizes) may diverge between guest + * FPUs and host FPUs, as some supervisor features are supported + * for guests despite not being utilized by the host. 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Peter Anvin" , Kees Cook , Eric Biggers , Stanislav Spassov , Oleg Nesterov Subject: [PATCH v8 4/6] x86/fpu: Remove xfd argument from __fpstate_reset() Date: Thu, 22 May 2025 08:10:07 -0700 Message-ID: <20250522151031.426788-5-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The initial values for fpstate::xfd differ between guest and host fpstates. Currently, the initial values are passed as an argument to __fpstate_reset(). But, __fpstate_reset() already assigns different default features and sizes based on the type of fpstates (i.e., guest or host). So, handle fpstate::xfd in a similar way to highlight the differences in the initial xfd value between guest and host fpstates Suggested-by: Sean Christopherson Signed-off-by: Chao Gao Link: https://lore.kernel.org/all/aBuf7wiiDT0Wflhk@google.com/ Acked-by: Sean Christopherson Reviewed-by: John Allen --- v8: tweak comment in __fpstate_reset() (Sean) v7: new --- arch/x86/kernel/fpu/core.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index a5a9c55fcf83..4fafb27e9416 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -211,7 +211,7 @@ void fpu_reset_from_exception_fixup(void) } =20 #if IS_ENABLED(CONFIG_KVM) -static void __fpstate_reset(struct fpstate *fpstate, u64 xfd); +static void __fpstate_reset(struct fpstate *fpstate); =20 static void fpu_lock_guest_permissions(void) { @@ -246,8 +246,7 @@ bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) fpstate->is_valloc =3D true; fpstate->is_guest =3D true; =20 - /* Leave xfd to 0 (the reset value defined by spec) */ - __fpstate_reset(fpstate, 0); + __fpstate_reset(fpstate); fpstate_init_user(fpstate); =20 gfpu->fpstate =3D fpstate; @@ -536,7 +535,7 @@ void fpstate_init_user(struct fpstate *fpstate) fpstate_init_fstate(fpstate); } =20 -static void __fpstate_reset(struct fpstate *fpstate, u64 xfd) +static void __fpstate_reset(struct fpstate *fpstate) { /* * Supervisor features (and thus sizes) may diverge between guest @@ -544,25 +543,29 @@ static void __fpstate_reset(struct fpstate *fpstate, = u64 xfd) * for guests despite not being utilized by the host. User * features and sizes are always identical, which allows for * common guest and userspace ABI. + * + * For the host, set XFD to the kernel's desired initialization + * value. For guests, set XFD to its architectural RESET value. */ if (fpstate->is_guest) { fpstate->size =3D guest_default_cfg.size; fpstate->xfeatures =3D guest_default_cfg.features; + fpstate->xfd =3D 0; } else { fpstate->size =3D fpu_kernel_cfg.default_size; fpstate->xfeatures =3D fpu_kernel_cfg.default_features; + fpstate->xfd =3D init_fpstate.xfd; } =20 fpstate->user_size =3D fpu_user_cfg.default_size; fpstate->user_xfeatures =3D fpu_user_cfg.default_features; - fpstate->xfd =3D xfd; } =20 void fpstate_reset(struct fpu *fpu) { /* Set the fpstate pointer to the default fpstate */ fpu->fpstate =3D &fpu->__fpstate; - __fpstate_reset(fpu->fpstate, init_fpstate.xfd); + __fpstate_reset(fpu->fpstate); =20 /* Initialize the permission related info in fpu */ fpu->perm.__state_perm =3D fpu_kernel_cfg.default_features; --=20 2.47.1 From nobody Tue Dec 16 15:44:25 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 979B4290BD8; Thu, 22 May 2025 15:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926647; cv=none; b=S/Crv3xYLocfsk4l9CbTxBIW8Z97utlW4ZFRFNqSJI9o21+ZWcKWQnF/y9uk0XEfd9wbGGXYkzKACmN2R6o5tXQe4lJ5nEPX4JP7PIMZWQbPVx0K8juSIP5CP6fjXczqXAwx1Ie+cJ6RsJJGHDSMRvqsnRkhSKSvQGbUQ8hmps8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747926647; c=relaxed/simple; bh=DsZIwVY6w9Iitp4Kq16ev6TnmK6/KC1aRYaoCSeutV8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ds7DpCD7e3CRPoCkvwmu1kJlQqz6grScbX+n1c7wukY5BqjLJMUprdAsHxqDYlskkzzAvg3UqXIiPhhtbO5brSozNe1Fri+Y1kbt+OP/31h5R4T2f5SrkM/XLMZfH7u+JdPRYdQc79szZRwr/SNyXEsdWnJgNEVKqmdncNbF0qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YipQcUm5; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YipQcUm5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747926646; x=1779462646; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DsZIwVY6w9Iitp4Kq16ev6TnmK6/KC1aRYaoCSeutV8=; b=YipQcUm5ZGhfKuM9K0zUgW4Eao6zuw+cwyBkfuDxQLjSnCBmzrzOAe6I 3V8KYKcuef93aQh3AwYsTWaSObRoKfIJ2vPbGbCN/OmWHyiY41kfRBl23 Pfc5eOPl6jzZuhpMUYQgAWN/FHL2CriPKagRe8XODL/ZafzX2/aQsTTxy 51KpwwR/0/oa0UXzb84yHSoG6eQYhpqtfu8an2YJDr56C4kr+/wI7+9m3 NIw0Nk7jU41Xp31FcDzw5tvylKaNEC2ennPYe3BnDuMQhIYojIC/Du+aD wHoxbpKw/OoNI1uhBn937WdYQVewsRJTCQRZIweDDU2Bvcsr08Inq1A4f Q==; X-CSE-ConnectionGUID: 6KGJvhHhR32K725cTEs2wQ== X-CSE-MsgGUID: txH+YLhTTCySgYa+tuWnKg== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="61006708" X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="61006708" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:46 -0700 X-CSE-ConnectionGUID: TwK2XDVES4CIzdTGYYRcXQ== X-CSE-MsgGUID: NgmlidEHThewoZ2eNpG+4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,306,1739865600"; d="scan'208";a="171627630" Received: from 984fee019967.jf.intel.com ([10.165.54.94]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:45 -0700 From: Chao Gao To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@linutronix.de, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com Cc: peterz@infradead.org, rick.p.edgecombe@intel.com, weijiang.yang@intel.com, john.allen@amd.com, bp@alien8.de, chang.seok.bae@intel.com, xin3.li@intel.com, Chao Gao , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Maxim Levitsky , Mitchell Levy , Vignesh Balasubramanian Subject: [PATCH v8 5/6] x86/fpu/xstate: Introduce "guest-only" supervisor xfeature set Date: Thu, 22 May 2025 08:10:08 -0700 Message-ID: <20250522151031.426788-6-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Yang Weijiang In preparation for upcoming CET virtualization support, the CET supervisor state will be added as a "guest-only" feature, since it is required only by KVM (i.e., guest FPUs). Establish the infrastructure for "guest-only" features. Define a new XFEATURE_MASK_GUEST_SUPERVISOR mask to specify features that are enabled by default in guest FPUs but not in host FPUs. Specifically, for any bit in this set, permission is granted and XSAVE space is allocated during vCPU creation. Non-guest FPUs cannot enable guest-only features, even dynamically, and no XSAVE space will be allocated for them. The mask is currently empty, but this will be changed by a subsequent patch. Co-developed-by: Chao Gao Signed-off-by: Chao Gao Signed-off-by: Yang Weijiang Reviewed-by: Rick Edgecombe Acked-by: Sean Christopherson Reviewed-by: John Allen --- v8: rebased v6: Collect reviews v5: Explain in detail the reasoning behind the mask name choice below the "---" separator line. In previous versions, the mask was named "XFEATURE_MASK_SUPERVISOR_DYNAMIC" Dave suggested this name [1], but he also noted, "I don't feel strongly abo= ut it and I've said my piece. I won't NAK it one way or the other." The term "dynamic" was initially preferred because it reflects the impact on XSAVE buffers=E2=80=94some buffers accommodate dynamic features while ot= hers do not. This naming allows for the introduction of dynamic features that are not strictly "guest-only", offering flexibility beyond KVM. However, using "dynamic" has led to confusion [2]. Chang pointed out that permission granting and buffer allocation are actually static at VCPU allocation, diverging from the model for user dynamic features. He also questioned the rationale for introducing a kernel dynamic feature mask while using it as a guest-only feature mask [3]. Moreover, Thomas remarked that "the dynamic naming is really bad" [4]. Although his specific concerns are unclear, we should be cautious about reinstating the "kernel dynamic feature" naming. Therefore, in v4, I renamed the mask to "XFEATURE_MASK_SUPERVISOR_GUEST" and further refined it to "XFEATURE_MASK_GUEST_SUPERVISOR" in this v5. [1]: https://lore.kernel.org/all/893ac578-baaf-4f4f-96ee-e012dfc073a8@intel= .com/#t [2]: https://lore.kernel.org/kvm/e15d1074-d5ec-431d-86e5-a58bc6297df8@intel= .com/ [3]: https://lore.kernel.org/kvm/7bee70fd-b2b9-4466-a694-4bf3486b19c7@intel= .com/ [4]: https://lore.kernel.org/all/87sg1owmth.ffs@nanos.tec.linutronix.de/ --- arch/x86/include/asm/fpu/types.h | 9 +++++---- arch/x86/include/asm/fpu/xstate.h | 6 +++++- arch/x86/kernel/fpu/xstate.c | 7 +++++-- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index abd193a1a52e..54ba567258d6 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -592,8 +592,9 @@ struct fpu_state_config { * @default_size: * * The default size of the register state buffer. Includes all - * supported features except independent managed features and - * features which have to be requested by user space before usage. + * supported features except independent managed features, + * guest-only features and features which have to be requested by + * user space before usage. */ unsigned int default_size; =20 @@ -609,8 +610,8 @@ struct fpu_state_config { * @default_features: * * The default supported features bitmap. Does not include - * independent managed features and features which have to - * be requested by user space before usage. + * independent managed features, guest-only features and features + * which have to be requested by user space before usage. */ u64 default_features; /* diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index b308a76afbb7..a3cd25453f94 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -46,9 +46,13 @@ /* Features which are dynamically enabled for a process on request */ #define XFEATURE_MASK_USER_DYNAMIC XFEATURE_MASK_XTILE_DATA =20 +/* Supervisor features which are enabled only in guest FPUs */ +#define XFEATURE_MASK_GUEST_SUPERVISOR 0 + /* All currently supported supervisor features */ #define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID | \ - XFEATURE_MASK_CET_USER) + XFEATURE_MASK_CET_USER | \ + XFEATURE_MASK_GUEST_SUPERVISOR) =20 /* * A supervisor state component may not always contain valuable informatio= n, diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index f15be5c3f0cc..f5eb3e84c3dc 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -778,8 +778,11 @@ static void __init fpu__init_disable_system_xstate(uns= igned int legacy_size) =20 static u64 __init host_default_mask(void) { - /* Exclude dynamic features, which require userspace opt-in. */ - return ~(u64)XFEATURE_MASK_USER_DYNAMIC; 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d="scan'208";a="171627635" Received: from 984fee019967.jf.intel.com ([10.165.54.94]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2025 08:10:47 -0700 From: Chao Gao To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@linutronix.de, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com Cc: peterz@infradead.org, rick.p.edgecombe@intel.com, weijiang.yang@intel.com, john.allen@amd.com, bp@alien8.de, chang.seok.bae@intel.com, xin3.li@intel.com, Chao Gao , Maxim Levitsky , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Mitchell Levy , Vignesh Balasubramanian Subject: [PATCH v8 6/6] x86/fpu/xstate: Add CET supervisor xfeature support as a guest-only feature Date: Thu, 22 May 2025 08:10:09 -0700 Message-ID: <20250522151031.426788-7-chao.gao@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250522151031.426788-1-chao.gao@intel.com> References: <20250522151031.426788-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yang Weijiang =3D=3D Background =3D=3D CET defines two register states: CET user, which includes user-mode control registers, and CET supervisor, which consists of shadow-stack pointers for privilege levels 0-2. Current kernels disable shadow stacks in kernel mode, making the CET supervisor state unused and eliminating the need for context switching. =3D=3D Problem =3D=3D To virtualize CET for guests, KVM must accurately emulate hardware behavior. A key challenge arises because there is no CPUID flag to indicate that shadow stack is supported only in user mode. Therefore, KVM cannot assume guests will not enable shadow stacks in kernel mode and must preserve the CET supervisor state of vCPUs. =3D=3D Solution =3D=3D An initial proposal to manually save and restore CET supervisor states using raw RDMSR/WRMSR in KVM was rejected due to performance concerns and its impact on KVM's ABI. Instead, leveraging the kernel's FPU infrastructure for context switching was favored [1]. The main question then became whether to enable the CET supervisor state globally for all processes or restrict it to vCPU processes. This decision involves a trade-off between a 24-byte XSTATE buffer waste for all non-vCPU processes and approximately 100 lines of code complexity in the kernel [2]. The agreed approach is to first try this optimal solution [3], i.e., restricting the CET supervisor state to guest FPUs only and eliminating unnecessary space waste. The guest-only xfeature infrastructure has already been added. Now, introduce CET supervisor xstate support as the first guest-only feature to prepare for the upcoming CET virtualization in KVM. Signed-off-by: Yang Weijiang Signed-off-by: Chao Gao Reviewed-by: Rick Edgecombe Reviewed-by: Maxim Levitsky Link: https://lore.kernel.org/kvm/ZM1jV3UPL0AMpVDI@google.com/ [1] Link: https://lore.kernel.org/kvm/1c2fd06e-2e97-4724-80ab-8695aa4334e7@inte= l.com/ [2] Link: https://lore.kernel.org/kvm/2597a87b-1248-b8ce-ce60-94074bc67ea4@inte= l.com/ [3] Acked-by: Sean Christopherson Reviewed-by: John Allen --- v5: Introduce CET supervisor xfeature directly as a guest-only feature, rather than first introducing it in one patch and then converting it to guest-only in a subsequent patch. (Chang) Add new features after cleanups/bug fixes (Chang, Dave, Ingo) Improve the commit message to follow the suggested background-problem-solution pattern. --- arch/x86/include/asm/fpu/types.h | 14 ++++++++++++-- arch/x86/include/asm/fpu/xstate.h | 5 ++--- arch/x86/kernel/fpu/xstate.c | 5 ++++- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index 54ba567258d6..93e99d2583d6 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -118,7 +118,7 @@ enum xfeature { XFEATURE_PKRU, XFEATURE_PASID, XFEATURE_CET_USER, - XFEATURE_CET_KERNEL_UNUSED, + XFEATURE_CET_KERNEL, XFEATURE_RSRVD_COMP_13, XFEATURE_RSRVD_COMP_14, XFEATURE_LBR, @@ -142,7 +142,7 @@ enum xfeature { #define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU) #define XFEATURE_MASK_PASID (1 << XFEATURE_PASID) #define XFEATURE_MASK_CET_USER (1 << XFEATURE_CET_USER) -#define XFEATURE_MASK_CET_KERNEL (1 << XFEATURE_CET_KERNEL_UNUSED) +#define XFEATURE_MASK_CET_KERNEL (1 << XFEATURE_CET_KERNEL) #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG) #define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA) @@ -268,6 +268,16 @@ struct cet_user_state { u64 user_ssp; }; =20 +/* + * State component 12 is Control-flow Enforcement supervisor states. + * This state includes SSP pointers for privilege levels 0 through 2. + */ +struct cet_supervisor_state { + u64 pl0_ssp; + u64 pl1_ssp; + u64 pl2_ssp; +} __packed; + /* * State component 15: Architectural LBR configuration state. * The size of Arch LBR state depends on the number of LBRs (lbr_depth). diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index a3cd25453f94..7a7dc9d56027 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -47,7 +47,7 @@ #define XFEATURE_MASK_USER_DYNAMIC XFEATURE_MASK_XTILE_DATA =20 /* Supervisor features which are enabled only in guest FPUs */ -#define XFEATURE_MASK_GUEST_SUPERVISOR 0 +#define XFEATURE_MASK_GUEST_SUPERVISOR XFEATURE_MASK_CET_KERNEL =20 /* All currently supported supervisor features */ #define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID | \ @@ -79,8 +79,7 @@ * Unsupported supervisor features. When a supervisor feature in this mask= is * supported in the future, move it to the supported supervisor feature ma= sk. */ -#define XFEATURE_MASK_SUPERVISOR_UNSUPPORTED (XFEATURE_MASK_PT | \ - XFEATURE_MASK_CET_KERNEL) +#define XFEATURE_MASK_SUPERVISOR_UNSUPPORTED (XFEATURE_MASK_PT) =20 /* All supervisor states including supported and unsupported states. */ #define XFEATURE_MASK_SUPERVISOR_ALL (XFEATURE_MASK_SUPERVISOR_SUPPORTED |= \ diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index f5eb3e84c3dc..bcccb0977809 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -56,7 +56,7 @@ static const char *xfeature_names[] =3D "Protection Keys User registers", "PASID state", "Control-flow User registers", - "Control-flow Kernel registers (unused)", + "Control-flow Kernel registers (KVM only)", "unknown xstate feature", "unknown xstate feature", "unknown xstate feature", @@ -80,6 +80,7 @@ static unsigned short xsave_cpuid_features[] __initdata = =3D { [XFEATURE_PKRU] =3D X86_FEATURE_OSPKE, [XFEATURE_PASID] =3D X86_FEATURE_ENQCMD, [XFEATURE_CET_USER] =3D X86_FEATURE_SHSTK, + [XFEATURE_CET_KERNEL] =3D X86_FEATURE_SHSTK, [XFEATURE_XTILE_CFG] =3D X86_FEATURE_AMX_TILE, [XFEATURE_XTILE_DATA] =3D X86_FEATURE_AMX_TILE, [XFEATURE_APX] =3D X86_FEATURE_APX, @@ -371,6 +372,7 @@ static __init void os_xrstor_booting(struct xregs_state= *xstate) XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_PASID | \ XFEATURE_MASK_CET_USER | \ + XFEATURE_MASK_CET_KERNEL | \ XFEATURE_MASK_XTILE | \ XFEATURE_MASK_APX) =20 @@ -572,6 +574,7 @@ static bool __init check_xstate_against_struct(int nr) case XFEATURE_PASID: return XCHECK_SZ(sz, nr, struct ia32_pasid_state); case XFEATURE_XTILE_CFG: return XCHECK_SZ(sz, nr, struct xtile_cfg); case XFEATURE_CET_USER: return XCHECK_SZ(sz, nr, struct cet_user_state); + case XFEATURE_CET_KERNEL: return XCHECK_SZ(sz, nr, struct cet_supervisor_= state); case XFEATURE_APX: return XCHECK_SZ(sz, nr, struct apx_state); case XFEATURE_XTILE_DATA: check_xtile_data_against_struct(sz); return tru= e; default: --=20 2.47.1