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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 34F873F704D; Thu, 22 May 2025 03:06:45 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 4/4 v4] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Thu, 22 May 2025 15:36:27 +0530 Message-ID: <20250522100627.175210-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522100627.175210-1-bbhushan2@marvell.com> References: <20250522100627.175210-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: fiy2aakT7L7dPgENFes702I92A9IY5M2 X-Proofpoint-ORIG-GUID: fiy2aakT7L7dPgENFes702I92A9IY5M2 X-Authority-Analysis: v=2.4 cv=LYU86ifi c=1 sm=1 tr=0 ts=682ef73b cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDEwMSBTYWx0ZWRfX15NwPiTbS9ke yve0y+n/NiS4vFhMlid9TFZgTrtDqx/fiVdaQSeyQfq5l2DfDcHDjbijGTwHdCJOkM56g7gDtc1 kTBKeCibcvHXc0kICLixuzLEla9ViU55AH2VeBrAH0Ur1gT4sG5OpW5qylELG/oJs3VEESeuLmQ YggzmYRSDmDzvz+EB9qoluVr7UHuo3Yk36JVYRbShX3xJFPCXq2Rz6Ye5e0JPUpvkd3WnJQQ0YF yyUyO5iOVAWjnJEdkudlVoFYsw3l83KcNtS38thZXnImWwqy9YLAUZtBEri8Y9xWP7W9uXUSC8H A3F6kgmLAhFeg6/eq5V+t+gkPJFDfP6ksBw8umOrXBItpRBBKoMdJpfr143zmJPUYRaCB/qSdo4 wT0YbJof5bVZ0pFIKQVe4sZjoUfWCTF+oPr4/ugrsB1VzmYBsguJ1DV3ChpUl6lTo2vCtokW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_05,2025-05-22_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: # v6.8+ --- v3->v4: - Again fixed memory size calculation as per review comment v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 59 ++++++++++++++----- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index 98de93851ba1..90a031421aac 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,48 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen =3D 0, g_len, sg_len, info_len; - int align =3D OTX2_CPT_DMA_MINALIGN; + u32 dlen =3D 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; =20 - g_sz_bytes =3D ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ------------------------------------ + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | --------------------------------| + * | | padding for ARCH_DMA_MINALIGN | + * | | alignment | + * |------------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |---------------------------------- | + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | -------------------------------| + * | | padding for 32B alignment | + * |------------------------------------| + * | Result response memory | + * | Alignment =3D 32Byte | + * ------------------------------------ + */ + + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len =3D ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len =3D g_len + s_len; =20 - g_len =3D ALIGN(g_sz_bytes, align); - sg_len =3D ALIGN(g_len + s_sz_bytes, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s); + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (ARCH_DMA_MINALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D ALIGN(sg_len, OTX2_CPT_RES_ADDR_ALIGN); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +401,8 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, dlen +=3D req->in[i].size; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); + info->out_buffer =3D info->in_buffer + g_len; info->gthr_sz =3D req->in_cnt; info->sctr_sz =3D req->out_cnt; =20 @@ -387,7 +414,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, } =20 if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +431,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct ot= x2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + sg_len; - info->comp_baddr =3D info->dptr_baddr + sg_len; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1