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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id C32F23F704D; Thu, 22 May 2025 03:06:33 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan Subject: [PATCH 1/4 v4] crypto: octeontx2: add timeout for load_fvc completion poll Date: Thu, 22 May 2025 15:36:24 +0530 Message-ID: <20250522100627.175210-2-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522100627.175210-1-bbhushan2@marvell.com> References: <20250522100627.175210-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: WPRcD1qQenSbEK8WwlHzTZuYqVouYnpA X-Authority-Analysis: v=2.4 cv=HfgUTjE8 c=1 sm=1 tr=0 ts=682ef72d cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=dP9LQboaRqI6G61vZ2MA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: WPRcD1qQenSbEK8WwlHzTZuYqVouYnpA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDEwMSBTYWx0ZWRfX2DghlUyE8BTy Nac/WmWvvpsFo6KRa+rf9gBiV/8kGkbhvZ+CJHXSuwFxcttV6GOwYATnkgCKP1JFECbylwcHraz g/f6ihCXsS2LQRFXkVhHpjGrpXzRs5EzB7j6KDKpKeRXjYBJ2+BaklHBRs2wHpVaJjZELWYRVF4 jHrLDcL/brcmYcFml9umEsAVokNxmXbJJ4M18AHYP+H7Xdy4qpc7At6BW13daMEmHFGir/olvAe whq+FK9VOsECDzSsDZdu94WLQdEek1SL0GGNHE5aoqiC7ZFsNSNFaV5q8hTL7JV+YITWxr/Jg1F tWb8OTVhn6K5V1AfytAxGyPqLN0LmBh4Dw6HqoMl6GOK4IZgWF0Qs/sv7vyJGmXYqg5GLH0ltmr CmhyX+rBPJZnyl0eKzslcPtW86NRy/QU6ajcqJOnwacpyVro4C2zq6wP3Qv7yGDiiyJmqOL1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_05,2025-05-22_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Adds timeout to exit from possible infinite loop, which polls on CPT instruction(load_fvc) completion. Signed-off-by: Srujana Challa Signed-off-by: Bharat Bhushan --- .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 42c5484ce66a..3a818ac89295 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1494,6 +1494,7 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) dma_addr_t rptr_baddr; struct pci_dev *pdev; u32 len, compl_rlen; + int timeout =3D 10000; int ret, etype; void *rptr; =20 @@ -1556,16 +1557,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) etype); otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); + timeout =3D 10000; =20 while (lfs->ops->cpt_get_compcode(result) =3D=3D - OTX2_CPT_COMPLETION_CODE_INIT) + OTX2_CPT_COMPLETION_CODE_INIT) { cpu_relax(); + udelay(1); + timeout--; + if (!timeout) { + ret =3D -ENODEV; + cptpf->is_eng_caps_discovered =3D false; + dev_warn(&pdev->dev, "Timeout on CPT load_fvc completion poll\n"); + goto error_no_response; + } + } =20 cptpf->eng_caps[etype].u =3D be64_to_cpup(rptr); } - dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); cptpf->is_eng_caps_discovered =3D true; =20 +error_no_response: + dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); free_result: kfree(result); lf_cleanup: --=20 2.34.1 From nobody Sun Dec 14 12:13:36 2025 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13125288CA1; Thu, 22 May 2025 10:07:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747908424; cv=none; b=NAT9LUtuB7+z1ubeC9QytU4Oiqv+1G6WGMNCyI+4AvthfzubX7hUMZNGKenektUj0/nHS7/Hm4NKYPHJ/+49dijxV3tpqJUGnFRF5xN077SPvyIWQsBWpn2yBu6TkN8qcA+FQYXZnWAqzZ6tzmyzLhUjlK4pqBEu7QHePUUb6Gw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747908424; c=relaxed/simple; bh=mtboeDMY5otbNjIXDqs9HEzEdkdlvsdHOhf4Wb6sTCU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=unaJsnzfRo5DlIy7XSXW4w2kR7lsIKedDmnAm/u7eDw1hE29uTaMXRAS6ysa2bMSty0uWdVbSSwdSiS49MtfRYqM9/5OLf2cxKbJQfJkU3lOEYayrlOL8XUBFIF8m930+zAQuofgNxT/qLU5MX3nQ7mKy0V4vYKIL0pSVqjtxzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=WfdPNCag; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="WfdPNCag" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54M5K8rc014360; Thu, 22 May 2025 03:06:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=B em5GbQzb8pFdcLi28ckFrDdVlDIhuU/H/j2UJ2eTA0=; b=WfdPNCagjHGPWSR3T UQxp5oYjKh2ka5GSdrLc8zWcS4VNPZZpJVQL2czyVmK+cX5RDVsdzO4w4Nd73wd4 KBMDzlIMrhn/5JEt6mMNQUcZF5+wZCSBFsZIymCRPH2m82I6pOIGhWb23f9CRPsf cBIOx9iDmZWm9IX5wDV0TNqxETSYFxPFVo/zZXUSLmxdw/tT4JgIxjEHm8EGzMA4 AYOs6FndNermZ8Arka8Eqgn0oW15HkvREh7WUdL0lhgivzmVm54lYYfuPWOwkbFd 1QBTi4zvl5+uV4/erWc4vD4v3psuG+FjnPcDWp/1j+lXhrxgUB6i0Fj3KKSC+u15 whQqg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 46swp68ge2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 May 2025 03:06:42 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 22 May 2025 03:06:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 22 May 2025 03:06:41 -0700 Received: from bharat-OptiPlex-Tower-Plus-7020.. (unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 912623F704D; Thu, 22 May 2025 03:06:37 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 2/4 v4] crypto: octeontx2: Fix address alignment issue on ucode loading Date: Thu, 22 May 2025 15:36:25 +0530 Message-ID: <20250522100627.175210-3-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522100627.175210-1-bbhushan2@marvell.com> References: <20250522100627.175210-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: LwY1sFshyr7NSYurl1e65pB6wLFNNMA1 X-Authority-Analysis: v=2.4 cv=DO+P4zNb c=1 sm=1 tr=0 ts=682ef732 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=ub5NSpVJfYrinLkKqRIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDEwMSBTYWx0ZWRfX+EsRKjsVKzPS Tp3vUi9Bj97rOPyqLq9Ze5OpuZrglvTYKwXNuuAMCzU+hchuFre3/VqGs8RIcKe/GHUNnK3y1wY V7RzH3M75fNz1SHiE8Eiuc0ic1lmfRRg2EDODeEGC00Z5bD7q1cEbk1RE2gR72KK8kBjm9Cm5WL hyQ/3E2/s6qbzjMzHi36s6Zu8kR1n9f+aZOJuaOzB5XGYuBybmVG0ccgqOkwHorXeqLYLu3oo8f kdZ3/6a+hWgt6LYoUgRaaTRRviEg9ttxW1eJOpyRL5q0i6SzH9ku1mAkCwrzsYaDU3KQ2QVNYu7 12Yom/MTHJolKggfvV6/jSbNLhxkt6qyTdUetbrXMBjj6TzHXJF5fZOZ6qyfhi+GrKr0cc0AFhs fQmBYMq5n5cTEC3hFzZKVX/JB91fdkyzcNHziYdUaNKJ9nItziiVB5fRSQRZ2bSZQ+K5DrkA X-Proofpoint-ORIG-GUID: LwY1sFshyr7NSYurl1e65pB6wLFNNMA1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_05,2025-05-22_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size()" Completion address should be 32-Byte alignment when loading microcode. Signed-off-by: Bharat Bhushan Cc: # v6.5+ --- v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional .../marvell/octeontx2/otx2_cptpf_ucode.c | 35 +++++++++++-------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 3a818ac89295..88f0f72a4462 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1491,12 +1491,13 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) union otx2_cpt_opcode opcode; union otx2_cpt_res_s *result; union otx2_cpt_inst_s inst; + dma_addr_t result_baddr; dma_addr_t rptr_baddr; struct pci_dev *pdev; - u32 len, compl_rlen; int timeout =3D 10000; + void *base, *rptr; int ret, etype; - void *rptr; + u32 len; =20 /* * We don't get capabilities if it was already done @@ -1521,22 +1522,28 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) if (ret) goto delete_grps; =20 - compl_rlen =3D ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN); - len =3D compl_rlen + LOADFVC_RLEN; + /* Allocate extra memory for "rptr" and "result" pointer alignment */ + len =3D LOADFVC_RLEN + ARCH_DMA_MINALIGN + + sizeof(union otx2_cpt_res_s) + OTX2_CPT_RES_ADDR_ALIGN; =20 - result =3D kzalloc(len, GFP_KERNEL); - if (!result) { + base =3D kzalloc(len, GFP_KERNEL); + if (!base) { ret =3D -ENOMEM; goto lf_cleanup; } - rptr_baddr =3D dma_map_single(&pdev->dev, (void *)result, len, - DMA_BIDIRECTIONAL); + + rptr =3D PTR_ALIGN(base, ARCH_DMA_MINALIGN); + rptr_baddr =3D dma_map_single(&pdev->dev, rptr, len, DMA_BIDIRECTIONAL); if (dma_mapping_error(&pdev->dev, rptr_baddr)) { dev_err(&pdev->dev, "DMA mapping failed\n"); ret =3D -EFAULT; - goto free_result; + goto free_rptr; } - rptr =3D (u8 *)result + compl_rlen; + + result =3D (union otx2_cpt_res_s *)PTR_ALIGN(rptr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); + result_baddr =3D ALIGN(rptr_baddr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); =20 /* Fill in the command */ opcode.s.major =3D LOADFVC_MAJOR_OP; @@ -1548,14 +1555,14 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) /* 64-bit swap for microcode data reads, not needed for addresses */ cpu_to_be64s(&iq_cmd.cmd.u); iq_cmd.dptr =3D 0; - iq_cmd.rptr =3D rptr_baddr + compl_rlen; + iq_cmd.rptr =3D rptr_baddr; iq_cmd.cptr.u =3D 0; =20 for (etype =3D 1; etype < OTX2_CPT_MAX_ENG_TYPES; etype++) { result->s.compcode =3D OTX2_CPT_COMPLETION_CODE_INIT; iq_cmd.cptr.s.grp =3D otx2_cpt_get_eng_grp(&cptpf->eng_grps, etype); - otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); + otx2_cpt_fill_inst(&inst, &iq_cmd, result_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); timeout =3D 10000; =20 @@ -1578,8 +1585,8 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) =20 error_no_response: dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); -free_result: - kfree(result); +free_rptr: + kfree(base); lf_cleanup: otx2_cptlf_shutdown(lfs); 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 180483F704D; Thu, 22 May 2025 03:06:41 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 3/4 v4] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Date: Thu, 22 May 2025 15:36:26 +0530 Message-ID: <20250522100627.175210-4-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522100627.175210-1-bbhushan2@marvell.com> References: <20250522100627.175210-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: CzDbLdtoWdgm-6o69KHgHzKEavf6N4Y4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDEwMSBTYWx0ZWRfXweW87W9DUKjw 2JCtyKB4JuFjPvUztPUENJnDpBC23Srv8BZ2a0gsIMGLPWCR5CzhJmuIVHJZWh4K4NRcoOrPzOq XlPYLv2wAU1/FUOKFPBFLJc9r8zuhiuD/UuMINB4zrMfkEHz+OqZjZu3MumaeXLTM2NV/GZ3cBF q+Z9hejOP+1OwSLcWOdAOI5VfhvuKYYpchjLsnhD0HTtWKcCo/OIbH0Nl+dipquEUasmDPGfPU8 o3qF2jJ6HOuyL5iE8ExVIJf9nrAyqCsnAidth8hQKg8sx7wVQGJYVZCL/W/n2WHe+7VhhA1Nm0Z GsS/lL4cOOx4QEW0q1b1wJWAVGXyKtSFetAn6HSMcWR3imQjWRyduRlyNPLIv4X/8qXzrdd1OHp ew16Ptf2cirOY0StzeVfwJta+wQ8h83VvZ3MEUgKxnMqAEvkGddJKzu3hBg5mlZxUeIZAxM8 X-Authority-Analysis: v=2.4 cv=HOrDFptv c=1 sm=1 tr=0 ts=682ef737 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=vPvlv9gvxcbrHEec8UYA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: CzDbLdtoWdgm-6o69KHgHzKEavf6N4Y4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_05,2025-05-22_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: # v6.5+ --- v3->v4: - Again fixed memory size calculation as per review comment v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 66 ++++++++++++++----- 1 file changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..98de93851ba1 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -34,6 +34,9 @@ #define SG_COMP_2 2 #define SG_COMP_1 1 =20 +#define OTX2_CPT_DPTR_RPTR_ALIGN 8 +#define OTX2_CPT_RES_ADDR_ALIGN 32 + union otx2_cpt_opcode { u16 flags; struct { @@ -417,10 +420,9 @@ static inline struct otx2_cpt_inst_info * otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - int align =3D OTX2_CPT_DMA_MINALIGN; struct otx2_cpt_inst_info *info; - u32 dlen, align_dlen, info_len; - u16 g_sz_bytes, s_sz_bytes; + u32 dlen, info_len; + u16 g_len, s_len; u32 total_mem_len; =20 if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || @@ -429,22 +431,54 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2= _cpt_req_info *req, return NULL; } =20 - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ------------------------------------ + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | --------------------------------| + * | | padding for ARCH_DMA_MINALIGN | + * | | alignment | + * |------------------------------------| + * | SG List Header of 8 Byte | + * |------------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |---------------------------------- | + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | -------------------------------| + * | | padding for 32B alignment | + * |------------------------------------| + * | Result response memory | + * | Alignment =3D 32Byte | + * ------------------------------------ + */ =20 - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; - align_dlen =3D ALIGN(dlen, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D align_dlen + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + s_len =3D ((req->out_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + + dlen =3D g_len + s_len + SG_LIST_HDR_SIZE; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (ARCH_DMA_MINALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D ALIGN(dlen, OTX2_CPT_RES_ADDR_ALIGN); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) return NULL; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); + info->out_buffer =3D info->in_buffer + SG_LIST_HDR_SIZE + g_len; =20 ((u16 *)info->in_buffer)[0] =3D req->out_cnt; ((u16 *)info->in_buffer)[1] =3D req->in_cnt; @@ -460,7 +494,7 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_c= pt_req_info *req, } =20 if (setup_sgio_components(pdev, req->out, req->out_cnt, - &info->in_buffer[8 + g_sz_bytes])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -476,8 +510,10 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_= cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + align_dlen; - info->comp_baddr =3D info->dptr_baddr + align_dlen; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + dlen), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + dlen), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1 From nobody Sun Dec 14 12:13:36 2025 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E769C289354; 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 34F873F704D; Thu, 22 May 2025 03:06:45 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 4/4 v4] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Thu, 22 May 2025 15:36:27 +0530 Message-ID: <20250522100627.175210-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250522100627.175210-1-bbhushan2@marvell.com> References: <20250522100627.175210-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: fiy2aakT7L7dPgENFes702I92A9IY5M2 X-Proofpoint-ORIG-GUID: fiy2aakT7L7dPgENFes702I92A9IY5M2 X-Authority-Analysis: v=2.4 cv=LYU86ifi c=1 sm=1 tr=0 ts=682ef73b cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDEwMSBTYWx0ZWRfX15NwPiTbS9ke yve0y+n/NiS4vFhMlid9TFZgTrtDqx/fiVdaQSeyQfq5l2DfDcHDjbijGTwHdCJOkM56g7gDtc1 kTBKeCibcvHXc0kICLixuzLEla9ViU55AH2VeBrAH0Ur1gT4sG5OpW5qylELG/oJs3VEESeuLmQ YggzmYRSDmDzvz+EB9qoluVr7UHuo3Yk36JVYRbShX3xJFPCXq2Rz6Ye5e0JPUpvkd3WnJQQ0YF yyUyO5iOVAWjnJEdkudlVoFYsw3l83KcNtS38thZXnImWwqy9YLAUZtBEri8Y9xWP7W9uXUSC8H A3F6kgmLAhFeg6/eq5V+t+gkPJFDfP6ksBw8umOrXBItpRBBKoMdJpfr143zmJPUYRaCB/qSdo4 wT0YbJof5bVZ0pFIKQVe4sZjoUfWCTF+oPr4/ugrsB1VzmYBsguJ1DV3ChpUl6lTo2vCtokW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_05,2025-05-22_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: # v6.8+ --- v3->v4: - Again fixed memory size calculation as per review comment v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 59 ++++++++++++++----- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index 98de93851ba1..90a031421aac 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,48 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen =3D 0, g_len, sg_len, info_len; - int align =3D OTX2_CPT_DMA_MINALIGN; + u32 dlen =3D 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; =20 - g_sz_bytes =3D ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ------------------------------------ + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | --------------------------------| + * | | padding for ARCH_DMA_MINALIGN | + * | | alignment | + * |------------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |---------------------------------- | + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | -------------------------------| + * | | padding for 32B alignment | + * |------------------------------------| + * | Result response memory | + * | Alignment =3D 32Byte | + * ------------------------------------ + */ + + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len =3D ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len =3D g_len + s_len; =20 - g_len =3D ALIGN(g_sz_bytes, align); - sg_len =3D ALIGN(g_len + s_sz_bytes, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s); + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (ARCH_DMA_MINALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D ALIGN(sg_len, OTX2_CPT_RES_ADDR_ALIGN); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +401,8 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, dlen +=3D req->in[i].size; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); + info->out_buffer =3D info->in_buffer + g_len; info->gthr_sz =3D req->in_cnt; info->sctr_sz =3D req->out_cnt; =20 @@ -387,7 +414,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, } =20 if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +431,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct ot= x2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + sg_len; - info->comp_baddr =3D info->dptr_baddr + sg_len; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1