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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:29:45 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:02 +0200 Subject: [PATCH v6 1/6] Documentation: ABI: IIO: add calibconv_delay documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-1-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1861; i=adureghello@baylibre.com; h=from:subject:message-id; bh=MnikOzSRNNhylv/Xr1wy9eMKECvl3Lvhp3h+t82FVuA=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQV/PsPPz4yyt1d0XL9WesOP3nzfLqn///Zqeg41ql9 VqLcm7yd5SyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZjIPSWGv3LtbmferXqZPzGf 63++a4TZk2QX97OSpeeY702ewS+R0M3I8Jj772/BPzc2T1S55Xozf3o4+77PCfeUXPZd+p396PN 8Pk4A X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add new IIO calibconv_delay documentation. The ad7606 implements a phase calibation feature, in nanoseconds. Being this a time delay, using the conv_delay suffix. Signed-off-by: Angelo Dureghello --- Documentation/ABI/testing/sysfs-bus-iio | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index ef52c427a015cf47bb9847782e13afbee01e9f31..cd79c036b2ccdea016dcc17f4e8= ac5fdb2d0e465 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -559,6 +559,30 @@ Description: - a small discrete set of values like "0 2 4 6 8" - a range specified as "[min step max]" =20 +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Delay of start of conversion from common reference point shared + by all channels. Can be writable when used to compensate for + delay variation introduced by external filters feeding a + simultaneous sampling ADC. + + I.e., for the ad7606 ADC series, this value is intended as a + configurable time delay in seconds, to correct delay introduced + by an optional external filtering circuit. + +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay_available +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Available values of convdelay. Maybe expressed as: + + - a range specified as "[min step max]" + + If shared across all channels, _calibconv_delay_available + is used. + What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibscale --=20 2.49.0 From nobody Sun Dec 14 12:13:33 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48D9128C2A9 for ; Thu, 22 May 2025 13:29:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747920596; cv=none; b=iIN1Yvqp7e5u5BeeaBFXrYZPL4nN0EhAALPMaoZFIF6dzkUSZc3Mq7h0EjibD0+v3ug1ERPcyOrvQx8d3Z296aTYG5oPp5Efow0l7ZJ5QtUEtrGFBJS01qgYxXTo7XYqO5FpHmdMPbSgZeUm+pCvWXKQf5B4AUFFmUMMr13YDUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747920596; c=relaxed/simple; bh=8DecWNX9a+g7ci97Vv7IU6U85+eTrGoiJDNqhMLAwD0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fpbjNOxjfafQZpq0LzE1gxkVyzReNFdVAYbAN5KjRG4jEQYeRuJlooQOGX1MQSGxcr74lf2Gs+dPLVNmFaOFqwHmybFMuw9YRpsrtPLaMXSr5g8e7WqkVFoyv479+H9b6cVPvmhbrOEDPOC06yWHx3o2+no+44yc3sAHLCCf3Xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=pDisP2xz; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="pDisP2xz" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43cfa7e7f54so61574515e9.1 for ; Thu, 22 May 2025 06:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1747920591; x=1748525391; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=pDisP2xz+HijpEunsNT1wisqfHA9xTVmAWD3ip5nUzc63Etm86tAK/EbwCBIinhPTe Ywj2qAIAUrxr1xhImiQdCqT6gNYSWvYyEtCwTNCK97tkPYkcdVw/cdotbgxxOMQqCJdB //FkyPyzTzOfgjz8b9KFmyFx+8a0Awg9hewL7E3cxLt82L6GAy5xwB1ig2iOFsK6nnnS KJgGm6ZAQ3FX+8q5hFMXK2tYV9pmAthIRUiHuZchCCJIm6+dNqz9S9Jt/Qdq88+QtVIa OxZdyyB3MFRQ78TGsIYWpwgVF7RTlXyZLmcEO+pV8WwEJfQL+XtEjDY9qp6e1xq8LfDv tpWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747920591; x=1748525391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=l7bDMCAau0c90p2MsXuIqJ1D/79gc+Y8BLjO6gh2DnVFHOE6KhVM6I/1wJHuQPmglv gb7gur++fdXAkZOE6Lfd5z6cYtrZtjm4cgrVvCsPHeNxVgEJhlkDK31HGpoO4YqZzWcA R8IqkRoK5s88Rv82wzr4X729s4xbNI0/igpa2XIFYn61WlEpSuYC0XB5FL6dF4F5egt9 nv3Kp56+iuhSKZJLwRN7euwoAQcd6KGjb9vrEjFlHrd7Dk3Tj4nBt+DfCoyKc0/l7h7Z qTLomZrAVtRQy3+tJsW7A9HrauyBd8n1H3ZdA1IA5Mm2St8fgxogr3d4ifMY8uK+NsTu vY1A== X-Forwarded-Encrypted: i=1; AJvYcCVDoMBXzPo9NfrS8BSMGn/2LDcr2dmEA1YW2oTWv0AKBf8xur1/5p1GAhR4TsGhtk1yvLtub/91wN/SSFg=@vger.kernel.org X-Gm-Message-State: AOJu0YxJC23d3HUXt723qg9Uja4luoxXtOAwMvZsVU8OC9uLjZP5lmkM Tw5z1COLuMgE7AeExDYx7JIIW/Ld8+AiRouNRa2kcAu/4lxk9REIYRU6ozzr0iKgHak= X-Gm-Gg: ASbGncvWwpFFvHGXesR58K2EXUkwirLEjFCRtDlP8EPwFUYVPRvybZWnuspizlAetO3 cM3aNiu0vaoS3qmX/X32XQ2FSqd5Cj2U4NF90xXj32Z3NAf66knBGzVHy+gABgK8zEayIo2JC9J JUgNyI4g9/033cJ7C79w3rfY4VnJUPv3hMDesL+X+Vrf3va482q6iuIALuYKFA/gxCh7xH1LZcn iuFSwCXjtlD7cM0WInedTBrrJ1ZdKi0JcN63nYwLOOxpUrTKtNPwnEptywnkafOkWRlToCwtLes /GnB4guY7DzW0RRCw1Ul06PPDNOKdrq7+h4ootMQfRW6jegH2gMo01F1RlmHxgjmi8nsIGLmmcb pWTbmzFNbiJgCuDMJpCmZxGBVC5TmJ9c= X-Google-Smtp-Source: AGHT+IHue17ZX9mw4ey3hwkVeMQ6JQCquCW3Ynl5s+S7l/UxkzY5Bqoj4I32hyU+LDWChls+robRsA== X-Received: by 2002:a05:600c:5295:b0:43c:f3e1:a729 with SMTP id 5b1f17b1804b1-442f8514e9emr270779675e9.12.1747920591505; Thu, 22 May 2025 06:29:51 -0700 (PDT) Received: from [192.168.0.2] (host-80-116-51-117.retail.telecomitalia.it. [80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:29:50 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:03 +0200 Subject: [PATCH v6 2/6] iio: core: add ADC delay calibration definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-2-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1303; i=adureghello@baylibre.com; h=from:subject:message-id; bh=4Hb5fAw6wk9UOyjGvMGWLBgqM5yKlaYwdF7azoNoMts=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQV/NLN312tkCt7MRNx1XzP6tp3D0T16i1jZNjoWlp9 6tVG2aydpSyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZjIfR5GhsnLHlX6eC3U3i/6 ZEr2Hl1Oh64MH/On61Zsz1vcz3C0ez7D/9QMS9/mApnn7WJ7M5UafHeUSt5ezc0XUXt7gojfVKk 7XAA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello ADCs as ad7606 implement a phase calibration as a delay. Add such definition, needed for ad7606. Signed-off-by: Angelo Dureghello --- drivers/iio/industrialio-core.c | 1 + include/linux/iio/types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index 178e99b111debc59a247fcc3a6037e429db3bebf..f13c3aa470d774bfe655d6a9fb0= 0c263789db637 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -188,6 +188,7 @@ static const char * const iio_chan_info_postfix[] =3D { [IIO_CHAN_INFO_CALIBAMBIENT] =3D "calibambient", [IIO_CHAN_INFO_ZEROPOINT] =3D "zeropoint", [IIO_CHAN_INFO_TROUGH] =3D "trough_raw", + [IIO_CHAN_INFO_CONVDELAY] =3D "convdelay", }; /** * iio_device_id() - query the unique ID for the device diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index d89982c98368cf72c0fc30fa66ab001e48af4e8b..ad2761efcc8315e1f9907d2a715= 9447fb463333e 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -69,6 +69,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_CALIBAMBIENT, IIO_CHAN_INFO_ZEROPOINT, IIO_CHAN_INFO_TROUGH, + IIO_CHAN_INFO_CONVDELAY, }; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:29:56 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:04 +0200 Subject: [PATCH v6 3/6] iio: adc: ad7606: add offset and phase calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-3-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9455; i=adureghello@baylibre.com; h=from:subject:message-id; bh=7p7MAdn2ceJCkir2IZZuxGPKP4uvLOKDV4uGdI5qSy8=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQVwv5+1ft24KyVV2rK59PF3ro7L/nnsfMJz8ksxeVe FhujY6v7ChlYRDjYpAVU2SpS4wwCb0dKqW8gHE2zBxWJpAhDFycAjCRC1EM/+v+ft1iOGGGxlwx w5/uc3c4T5J9uozRJpTl6f1VF6Y4uWszMpxlrV0apez6NneOP5OC6p1y15R8ryzLLbYzjn9zevJ gPQMA X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add support for offset and phase calibration, only for devices that support software mode, that are: ad7606b ad7606c-16 ad7606c-18 Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 160 +++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 9 +++ 2 files changed, 169 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 2aa59481c52c07537110e7fc1fd1aedbab6b098d..bb0c89fc618874f4a5948d8e537= 716f87127bc92 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -95,6 +95,22 @@ static const unsigned int ad7616_oversampling_avail[8] = =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; =20 +static const int ad7606_calib_offset_avail[3] =3D { + -128, 1, 127, +}; + +static const int ad7606c_18bit_calib_offset_avail[3] =3D { + -512, 4, 508, +}; + +static const int ad7606b_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1250 }, { 0, 318750 }, +}; + +static const int ad7606c_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1000 }, { 0, 255000 }, +}; + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan); static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, @@ -164,6 +180,8 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606b_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -177,6 +195,8 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -226,6 +246,8 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -683,6 +705,40 @@ static int ad7606_scan_direct(struct iio_dev *indio_de= v, unsigned int ch, return ret; } =20 +static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *v= al) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch)); + if (ret < 0) + return ret; + + *val =3D st->chip_info->calib_offset_avail[0] + + ret * st->chip_info->calib_offset_avail[1]; + + return 0; +} + +static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *va= l, + int *val2) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_PHASE(ch)); + if (ret < 0) + return ret; + + *val =3D 0; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + *val2 =3D ret * st->chip_info->calib_phase_avail[1][1]; + + return 0; +} + static int ad7606_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -717,6 +773,22 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); *val =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT_PLUS_NANO; } return -EINVAL; } @@ -767,6 +839,64 @@ static int ad7606_write_os_hw(struct iio_dev *indio_de= v, int val) return 0; } =20 +static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int va= l) +{ + int start_val, step_val, stop_val; + int offset; + + start_val =3D st->chip_info->calib_offset_avail[0]; + step_val =3D st->chip_info->calib_offset_avail[1]; + stop_val =3D st->chip_info->calib_offset_avail[2]; + + if (val < start_val || val > stop_val) + return -EINVAL; + + offset =3D (val - start_val) / step_val; + + return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset); +} + +static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val, + int val2) +{ + int wreg, start_ns, step_ns, stop_ns; + + if (val !=3D 0) + return -EINVAL; + + start_ns =3D st->chip_info->calib_phase_avail[0][1]; + step_ns =3D st->chip_info->calib_phase_avail[1][1]; + stop_ns =3D st->chip_info->calib_phase_avail[2][1]; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + if (val2 < start_ns || val2 > stop_ns) + return -EINVAL; + + wreg =3D val2 / step_ns; + + return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg); +} + +static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + static int ad7606_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, @@ -820,6 +950,18 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, if (val < 0 && val2 !=3D 0) return -EINVAL; return ad7606_set_sampling_freq(st, val); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + return ret; default: return -EINVAL; } @@ -998,6 +1140,14 @@ static int ad7606_read_avail(struct iio_dev *indio_de= v, *type =3D IIO_VAL_INT_PLUS_MICRO; =20 return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals =3D st->chip_info->calib_offset_avail; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + case IIO_CHAN_INFO_CONVDELAY: + *vals =3D (const int *)st->chip_info->calib_phase_avail; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; } return -EINVAL; } @@ -1060,6 +1210,7 @@ static const struct iio_info ad7606_info_sw_mode =3D { .read_raw =3D &ad7606_read_raw, .write_raw =3D &ad7606_write_raw, .read_avail =3D &ad7606_read_avail, + .write_raw_get_fmt =3D ad7606_write_raw_get_fmt, .debugfs_reg_access =3D &ad7606_reg_access, .validate_trigger =3D &ad7606_validate_trigger, .update_scan_mode =3D &ad7606_update_scan_mode, @@ -1252,6 +1403,15 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) chan->info_mask_separate_available |=3D BIT(IIO_CHAN_INFO_SCALE); =20 + if (st->chip_info->calib_offset_avail) { + chan->info_mask_separate |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + chan->info_mask_separate_available |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + } + /* * All chips with software mode support oversampling, * so we skip the oversampling_available check. And the diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 441e62c521bcbea69b4f70bb2d55f65334d22276..f613583a7fa4095115b0b28e3f8= e51cd32b93524 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,6 +40,11 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 +#define AD7606_CALIB_GAIN(ch) (0x09 + (ch)) +#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0) +#define AD7606_CALIB_OFFSET(ch) (0x11 + (ch)) +#define AD7606_CALIB_PHASE(ch) (0x19 + (ch)) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, @@ -61,6 +66,8 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_offset_avail: pointer to offset calibration range/limits array + * @calib_phase_avail: pointer to phase calibration range/limits array */ struct ad7606_chip_info { unsigned int max_samplerate; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:30:02 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:05 +0200 Subject: [PATCH v6 4/6] dt-bindings: iio: adc: adi,ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-4-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2030; i=adureghello@baylibre.com; h=from:subject:message-id; bh=mK1GoQiX2hS20/yC/1czrPjfc5t1uAwSltJDkMx72Mc=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQV0uc4H8k57KT1P9PiW5Hz1v4cRXrzJY8Ity1+9Pi0 My5chztHaUsDGJcDLJiiix1iREmobdDpZQXMM6GmcPKBDKEgYtTACZyq47hf5HbtLVnmRxPVr1j v79x5hZz+zvfLPiO7joasmpCd1pGiyEjw502u+Zy4TeuLZHpOXVNCz4ETlOrN5bb0GDFt75X1f4 aCwA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support by a per-channel resistor value. Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 29 ++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 29f12d650442b8ff2eb455306ce59a0e87867ddd..6926f5f090ad6bbbe7bfd9327dc= 5ae17dafcd1fd 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -204,6 +204,15 @@ patternProperties: considered a bipolar differential channel. Otherwise it is bipol= ar single-ended. =20 + adi,rfilter-ohms: + description: + For ADCs that supports gain calibration, this property must be s= et to + the value of the external RFilter resistor. Proper gain error + correction is applied based on this value. + default: 0 + minimum: 0 + maximum: 64512 + required: - reg - bipolar @@ -256,6 +265,25 @@ allOf: properties: adi,oversampling-ratio-gpios: false =20 + - if: + properties: + compatible: + contains: + enum: + - adi,ad7605-4 + - adi,ad7606-4 + - adi,ad7606-6 + - adi,ad7606-8 + - adi,ad7607 + - adi,ad7608 + - adi,ad7609 + - adi,ad7616 + then: + patternProperties: + "^channel@[0-9a-f]+$": + properties: + adi,rfilter-ohms: false + - if: properties: compatible: @@ -398,6 +426,7 @@ examples: reg =3D <8>; diff-channels =3D <8 8>; bipolar; + adi,rfilter-ohms =3D <2048>; }; =20 }; --=20 2.49.0 From nobody Sun Dec 14 12:13:33 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4908828CF64 for ; Thu, 22 May 2025 13:30:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:30:08 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:06 +0200 Subject: [PATCH v6 5/6] iio: adc: ad7606: exit for invalid fdt dt_schema properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-5-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1250; i=adureghello@baylibre.com; h=from:subject:message-id; bh=NW1JeMg0S+0gI2cAzi0BWwFNupEZsJYBOb/eiNBCbAk=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQV0t7/bf47Y2NQe19O/43/DA9Xn9xbYH61HczMyNOq 3X+5Fl3qqOUhUGMi0FWTJGlLjHCJPR2qJTyAsbZMHNYmUCGMHBxCsBEQlYwMhxcZv5+0mq+PfGV GWorjCueGKy0u7fxtbSNQIr5uZutYr8Y/kptFJTeJZJr/b18a6mJSM7JV47N5evmvv29+cpWNxV zHhYA X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Fix ad7606_get_chan_config() fdt parsing function to exit for error in case of invalid dt_schema values. Idea is to not allowing to proceed over when there are values that are not allowed from the dt_schema. Fixes: f3838e934dff ("iio: adc: ad7606: add support for AD7606C-{16,18} par= ts") Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index bb0c89fc618874f4a5948d8e537716f87127bc92..f832fd0daf50a69a892636018bd= a2e43f73d1570 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -319,15 +319,13 @@ static int ad7606_get_chan_config(struct iio_dev *ind= io_dev, int ch, =20 ret =3D fwnode_property_read_u32(child, "reg", ®); if (ret) - continue; + return ret; =20 /* channel number (here) is from 1 to num_channels */ - if (reg < 1 || reg > num_channels) { - dev_warn(dev, - "Invalid channel number (ignoring): %d\n", reg); - continue; - } + if (reg < 1 || reg > num_channels) + return -EINVAL; =20 + /* Loop until we are in the right channel. */ if (reg !=3D (ch + 1)) continue; =20 --=20 2.49.0 From nobody Sun Dec 14 12:13:33 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34B7028C032 for ; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f1ef0b20sm109837585e9.14.2025.05.22.06.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 06:30:13 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 22 May 2025 15:27:07 +0200 Subject: [PATCH v6 6/6] iio: adc: ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-wip-bl-ad7606-calibration-v6-6-487b90433da0@baylibre.com> References: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> In-Reply-To: <20250522-wip-bl-ad7606-calibration-v6-0-487b90433da0@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5640; i=adureghello@baylibre.com; h=from:subject:message-id; bh=FrnFIjXjnkaraAHZa2fhT+4HMZyAF9OoYi/BTOJJXJg=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsjQV8v78li42GqufW23yOvw1coBLr+UY7ac2syQvermz /NRZ5lmdpSyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZjIljeMDO9WyH9/IRf6rDfy ufT3DzN+6Cnf71TqEH5fPPHVCw+V2suMDL9EXj8+68E9ffN/qfztqdYXrTal3Um2ncbafma+7EV xXk4A X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support, using resistor values set on devicetree, values to be set accordingly with ADC external RFilter, as explained in the ad7606c-16 datasheet, rev0, page 37. Usage example in the fdt yaml documentation. Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 55 ++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 3 +++ 2 files changed, 58 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index f832fd0daf50a69a892636018bda2e43f73d1570..00c498afd942724c9241a8c5908= 0f61a3075bca1 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -33,6 +33,10 @@ =20 #include "ad7606.h" =20 +#define AD7606_CALIB_GAIN_MIN 0 +#define AD7606_CALIB_GAIN_STEP 1024 +#define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP) + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values. @@ -125,6 +129,7 @@ static int ad7609_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan); static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev); =20 const struct ad7606_chip_info ad7605_4_info =3D { .max_samplerate =3D 300 * KILO, @@ -180,6 +185,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606b_calib_phase_avail, }; @@ -195,6 +201,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -246,6 +253,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -355,6 +363,46 @@ static int ad7606_get_chan_config(struct iio_dev *indi= o_dev, int ch, return 0; } =20 +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int num_channels =3D st->chip_info->num_adc_channels; + struct device *dev =3D st->dev; + int ret; + + /* + * This function is called once, and parses all the channel nodes, + * so continuing on next channel node on errors, informing of them. + */ + device_for_each_child_node_scoped(dev, child) { + u32 reg, r_gain; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return ret; + + /* Chan reg is a 1-based index. */ + if (reg < 1 || reg > num_channels) + return ret; + + ret =3D fwnode_property_read_u32(child, "adi,rfilter-ohms", + &r_gain); + if (ret) + /* Keep the default register value. */ + continue; + + if (r_gain > AD7606_CALIB_GAIN_MAX) + return -EINVAL; + + ret =3D st->bops->reg_write(st, AD7606_CALIB_GAIN(reg - 1), + DIV_ROUND_CLOSEST(r_gain, AD7606_CALIB_GAIN_STEP)); + if (ret) + return ret; + } + + return 0; +} + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan) { @@ -1446,6 +1494,13 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) if (slow_bus) channels[i] =3D (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(i); =20 + /* Setting up gain calibration for all channels. */ + if (st->sw_mode_en && st->chip_info->calib_offset_avail) { + ret =3D st->chip_info->calib_gain_setup_cb(indio_dev); + if (ret) + return ret; + } + indio_dev->channels =3D channels; =20 return 0; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index f613583a7fa4095115b0b28e3f8e51cd32b93524..6313eea2bd0ccf97222a50dc26d= 8ec65042d0db7 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -50,6 +50,7 @@ struct ad7606_state; typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan); typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); +typedef int (*ad7606_calib_gain_setup_cb_t)(struct iio_dev *indio_dev); =20 /** * struct ad7606_chip_info - chip specific information @@ -66,6 +67,7 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_gain_setup_cb: callback to setup of gain calibration * @calib_offset_avail: pointer to offset calibration range/limits array * @calib_phase_avail: pointer to phase calibration range/limits array */ @@ -81,6 +83,7 @@ struct ad7606_chip_info { bool os_req_reset; unsigned long init_delay_ms; u8 offload_storagebits; + ad7606_calib_gain_setup_cb_t calib_gain_setup_cb; const int *calib_offset_avail; const int (*calib_phase_avail)[2]; }; --=20 2.49.0