From nobody Sun Dec 14 19:24:45 2025 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7B36275855 for ; Fri, 23 May 2025 05:31:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747978309; cv=none; b=rUAqS9RmjBhx71GpzUmnH1BauEh0VUSe+w7X5Qn3dCgPVygg+zz9E7GQHZEcqD7TxsgyZchLnt3X6O4htLlQKUM0EcB77Vpopi3EnYe2eFCc4Nu8BXeBOvH4ObW8/u003z7TlXVYYCZa1ZLEJZMuhlJPjp0PgF/ry9ALfcL95gA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747978309; c=relaxed/simple; bh=blEoqggQsQhRB0qQ2LOUYe1TBy9Har2a+Y7ff8LDB+0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CvBDhSDKmbivtq+/H2ORTXmtAAJJGTg4cpdAWjU1oWhVzPKBshWnIEh6jd9aEaRDBXRFCqeWYvkxvBG5vrmgOLDD0t1B61AW4yobwDxk2SjcdEf3H9qrJg5/tcxe/AxiLJzftjS2ma91Nm1VfWfpHUJDCSZstN4Zuz68ratvoPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=253H0Dpl; arc=none smtp.client-ip=209.85.210.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="253H0Dpl" Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-742af848148so5285617b3a.1 for ; Thu, 22 May 2025 22:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1747978306; x=1748583106; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YoM38xw3FRuDhuA6RoI5dV9L/poXJy4s4CZPvznw1r4=; b=253H0DplZJTIO5R58hjd73pAdV+J53RCkj7KwC6BV0DesTSMGGUfSn7XJMKSGTz2sW cyoXtgpRjP9B89gHzMfSeVAghLb0kxjEfTJJKRCzdL7ftsAfuMCmbbsEaZXvIzOZXAaJ zmCFssctEIZwd/I+fBU4oFmvvS4FSYPJXLGW19x5i0Hq1oY3tdfU9WpYbG6/V9GCGOYR rboQpnmfETTvLd8cifOzxhXVOtAQCh6el84NQRhmcESmJDu6cOtPrl1Lq9NxbbOsOKlJ yn8WbTs5QDCGn+Sli8vfQPfBvGWWqzOCZqjqUbcLgsuNLqDKr/V0vth/Gcj0exbmf8zE Emqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747978306; x=1748583106; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YoM38xw3FRuDhuA6RoI5dV9L/poXJy4s4CZPvznw1r4=; b=wZxc0muKd71dnZpMCLWpS7/mrM5aC9bsww6bdfWV9J4XHaF34h0AwOE2Ko0Kq1Pl5w IgdFh964DsESpEweJq6x8R6Z92RJ552WoJ6kd4qcCZ1o/Rhk57JhE8DMtabHYobHuAPx 0+mRwQD4COQi3PCT4toDc+EsZhkuwcUk51XSNpFTJWYRfDqdtmtqvNPoIbMsWMHlNKV+ U8Y2JWYS3eAlGSfsokJAmAQ7iGjmlEbH7zGv+6qnlxbiYwdxZpEC9bo7M2K9tKqhwohj o6AaJbNLCqRD+sKTjZahsOFzVJg5vAvzJruPqYv9IE/jZYcEEb40UJNHe39h67AZSDqI C7Xw== X-Gm-Message-State: AOJu0Yy4k00Zy5rf8xRM70omCUib2MIOxtb/pFIZd9u6n6Em8SHl5ywB DzR/WCsFxvNrb7PsVplID4P+gBO4jrsPBLQHiAj4B61ebQdYrSMD7jTNXKhz3flYQrU= X-Gm-Gg: ASbGncsm5lDrMWkoEvt+emcxZlV4xdDuCskI9ucl5yCo0AKZfPzHRxZime8aWjpvPhC OoCO/fdU7FNlEAxnt2rpsoYrSsIRDdg+lxr5pBV1fItt+4Ay8vdHLeo1Tl5i6Y+KVzxWgWhTcF6 pAhZRUhvtlg2TOeGXbyOUS9rM5Ed+cZURCLZCN4q/PTXPL5GAhAgSq1iOg4noePT4lmRs5xda3p mxxEnR2TMpI4/dz6zbAUkEWLxvVHpc9xp2o5g8HtnncHR/xyW+mW/NI4fw8aDuermD0OyXFwvtX Etq9E60h6laWrnbHhkhG4ZL9oQHT7Gc2f+nIdoG6GA8pXSOYd8uLCdD8aw4QTA== X-Google-Smtp-Source: AGHT+IGWbmGlRPd84YoMyyft/eXdZH3sGq7OxzgnEwnMMGWw3l7e+QtU9idc+DxPGc0VGE41ZIwSyQ== X-Received: by 2002:a05:6a00:138e:b0:736:339b:8296 with SMTP id d2e1a72fcca58-745ed8f5bf3mr2696771b3a.18.1747978305981; Thu, 22 May 2025 22:31:45 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-742a982a0a4sm12474336b3a.101.2025.05.22.22.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 22:31:45 -0700 (PDT) From: Deepak Gupta Date: Thu, 22 May 2025 22:31:13 -0700 Subject: [PATCH v16 10/27] riscv/mm: Implement map_shadow_stack() syscall Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-v5_user_cfi_series-v16-10-64f61a35eee7@rivosinc.com> References: <20250522-v5_user_cfi_series-v16-0-64f61a35eee7@rivosinc.com> In-Reply-To: <20250522-v5_user_cfi_series-v16-0-64f61a35eee7@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 As discussed extensively in the changelog for the addition of this syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the existing mmap() and madvise() syscalls do not map entirely well onto the security requirements for shadow stack memory since they lead to windows where memory is allocated but not yet protected or stacks which are not properly and safely initialised. Instead a new syscall map_shadow_stack() has been defined which allocates and initialises a shadow stack page. This patch implements this syscall for riscv. riscv doesn't require token to be setup by kernel because user mode can do that by itself. However to provide compatibility and portability with other architectues, user mode can specify token set flag. Reviewed-by: Zong Li Signed-off-by: Deepak Gupta --- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/usercfi.c | 143 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 144 insertions(+) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 8d186bfced45..3a861d320654 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -125,3 +125,4 @@ obj-$(CONFIG_ACPI) +=3D acpi.o obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o =20 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o +obj-$(CONFIG_RISCV_USER_CFI) +=3D usercfi.o diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c new file mode 100644 index 000000000000..0b3bbb41490a --- /dev/null +++ b/arch/riscv/kernel/usercfi.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Rivos, Inc. + * Deepak Gupta + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SHSTK_ENTRY_SIZE sizeof(void *) + +/* + * Writes on shadow stack can either be `sspush` or `ssamoswap`. `sspush` = can happen + * implicitly on current shadow stack pointed to by CSR_SSP. `ssamoswap` t= akes pointer to + * shadow stack. To keep it simple, we plan to use `ssamoswap` to perform = writes on shadow + * stack. + */ +static noinline unsigned long amo_user_shstk(unsigned long *addr, unsigned= long val) +{ + /* + * Never expect -1 on shadow stack. Expect return addresses and zero + */ + unsigned long swap =3D -1; + + __enable_user_access(); + asm goto( + ".option push\n" + ".option arch, +zicfiss\n" + "1: ssamoswap.d %[swap], %[val], %[addr]\n" + _ASM_EXTABLE(1b, %l[fault]) + ".option pop\n" + : [swap] "=3Dr" (swap), [addr] "+A" (*addr) + : [val] "r" (val) + : "memory" + : fault + ); + __disable_user_access(); + return swap; +fault: + __disable_user_access(); + return -1; +} + +/* + * Create a restore token on the shadow stack. A token is always XLEN wide + * and aligned to XLEN. + */ +static int create_rstor_token(unsigned long ssp, unsigned long *token_addr) +{ + unsigned long addr; + + /* Token must be aligned */ + if (!IS_ALIGNED(ssp, SHSTK_ENTRY_SIZE)) + return -EINVAL; + + /* On RISC-V we're constructing token to be function of address itself */ + addr =3D ssp - SHSTK_ENTRY_SIZE; + + if (amo_user_shstk((unsigned long __user *)addr, (unsigned long)ssp) =3D= =3D -1) + return -EFAULT; + + if (token_addr) + *token_addr =3D addr; + + return 0; +} + +static unsigned long allocate_shadow_stack(unsigned long addr, unsigned lo= ng size, + unsigned long token_offset, bool set_tok) +{ + int flags =3D MAP_ANONYMOUS | MAP_PRIVATE; + struct mm_struct *mm =3D current->mm; + unsigned long populate, tok_loc =3D 0; + + if (addr) + flags |=3D MAP_FIXED_NOREPLACE; + + mmap_write_lock(mm); + addr =3D do_mmap(NULL, addr, size, PROT_READ, flags, + VM_SHADOW_STACK | VM_WRITE, 0, &populate, NULL); + mmap_write_unlock(mm); + + if (!set_tok || IS_ERR_VALUE(addr)) + goto out; + + if (create_rstor_token(addr + token_offset, &tok_loc)) { + vm_munmap(addr, size); + return -EINVAL; + } + + addr =3D tok_loc; + +out: + return addr; +} + +SYSCALL_DEFINE3(map_shadow_stack, unsigned long, addr, unsigned long, size= , unsigned int, flags) +{ + bool set_tok =3D flags & SHADOW_STACK_SET_TOKEN; + unsigned long aligned_size =3D 0; + + if (!cpu_supports_shadow_stack()) + return -EOPNOTSUPP; + + /* Anything other than set token should result in invalid param */ + if (flags & ~SHADOW_STACK_SET_TOKEN) + return -EINVAL; + + /* + * Unlike other architectures, on RISC-V, SSP pointer is held in CSR_SSP = and is available + * CSR in all modes. CSR accesses are performed using 12bit index program= med in instruction + * itself. This provides static property on register programming and writ= es to CSR can't + * be unintentional from programmer's perspective. As long as programmer = has guarded areas + * which perform writes to CSR_SSP properly, shadow stack pivoting is not= possible. Since + * CSR_SSP is writeable by user mode, it itself can setup a shadow stack = token subsequent + * to allocation. Although in order to provide portablity with other arch= itecture (because + * `map_shadow_stack` is arch agnostic syscall), RISC-V will follow expec= tation of a token + * flag in flags and if provided in flags, setup a token at the base. + */ + + /* If there isn't space for a token */ + if (set_tok && size < SHSTK_ENTRY_SIZE) + return -ENOSPC; + + if (addr && (addr & (PAGE_SIZE - 1))) + return -EINVAL; + + aligned_size =3D PAGE_ALIGN(size); + if (aligned_size < size) + return -EOVERFLOW; + + return allocate_shadow_stack(addr, aligned_size, size, set_tok); +} --=20 2.43.0