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Thu, 22 May 2025 07:52:46 -0700 (PDT) From: James Clark Date: Thu, 22 May 2025 15:51:34 +0100 Subject: [PATCH v2 05/14] spi: spi-fsl-dspi: Define regmaps per device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-james-nxp-spi-v2-5-bea884630cfb@linaro.org> References: <20250522-james-nxp-spi-v2-0-bea884630cfb@linaro.org> In-Reply-To: <20250522-james-nxp-spi-v2-0-bea884630cfb@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Matti Vaittinen Cc: Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Chao Fu , Xiubo Li , Lukasz Majewski , linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vladimir Oltean , Dan Carpenter , James Clark X-Mailer: b4 0.14.0 Refactor the regmaps so they can be defined per device rather than programmatically. This will allow us to add two new regmaps for S32G in a later commit. No functional changes. Reviewed-by: Vladimir Oltean Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 136 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 74 insertions(+), 62 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 09b2b25ed274..437a8db9fa2b 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -122,6 +122,7 @@ struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; int fifo_size; + const struct regmap_config *regmap; }; =20 enum { @@ -137,60 +138,130 @@ enum { VF610, }; =20 +static const struct regmap_range dspi_yes_ranges[] =3D { + regmap_reg_range(SPI_MCR, SPI_MCR), + regmap_reg_range(SPI_TCR, SPI_CTAR(3)), + regmap_reg_range(SPI_SR, SPI_TXFR3), + regmap_reg_range(SPI_RXFR0, SPI_RXFR3), + regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + +static const struct regmap_access_table dspi_access_table =3D { + .yes_ranges =3D dspi_yes_ranges, + .n_yes_ranges =3D ARRAY_SIZE(dspi_yes_ranges), +}; + +static const struct regmap_range dspi_volatile_ranges[] =3D { + regmap_reg_range(SPI_MCR, SPI_TCR), + regmap_reg_range(SPI_SR, SPI_SR), + regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + +static const struct regmap_access_table dspi_volatile_table =3D { + .yes_ranges =3D dspi_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(dspi_volatile_ranges), +}; + +enum { + DSPI_REGMAP, + DSPI_XSPI_REGMAP, + DSPI_PUSHR, +}; + +static const struct regmap_config dspi_regmap_config[] =3D { + [DSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D SPI_RXFR3, + .volatile_table =3D &dspi_volatile_table, + .rd_table =3D &dspi_access_table, + .wr_table =3D &dspi_access_table, + }, + [DSPI_XSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D SPI_SREX, + .volatile_table =3D &dspi_volatile_table, + .rd_table =3D &dspi_access_table, + .wr_table =3D &dspi_access_table, + }, + [DSPI_PUSHR] =3D { + .name =3D "pushr", + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_stride =3D 2, + .max_register =3D 0x2, + }, +}; + static const struct fsl_dspi_devtype_data devtype_data[] =3D { [VF610] =3D { .trans_mode =3D DSPI_DMA_MODE, .max_clock_factor =3D 2, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_REGMAP], }, [LS1021A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS1012A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS1028A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS1043A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS1046A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS2080A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LS2085A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [LX2160A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP], }, [MCF5441X] =3D { .trans_mode =3D DSPI_DMA_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_REGMAP], }, }; =20 @@ -1191,61 +1262,6 @@ static int dspi_resume(struct device *dev) =20 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); =20 -static const struct regmap_range dspi_yes_ranges[] =3D { - regmap_reg_range(SPI_MCR, SPI_MCR), - regmap_reg_range(SPI_TCR, SPI_CTAR(3)), - regmap_reg_range(SPI_SR, SPI_TXFR3), - regmap_reg_range(SPI_RXFR0, SPI_RXFR3), - regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)), - regmap_reg_range(SPI_SREX, SPI_SREX), -}; - -static const struct regmap_access_table dspi_access_table =3D { - .yes_ranges =3D dspi_yes_ranges, - .n_yes_ranges =3D ARRAY_SIZE(dspi_yes_ranges), -}; - -static const struct regmap_range dspi_volatile_ranges[] =3D { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), - regmap_reg_range(SPI_SREX, SPI_SREX), -}; - -static const struct regmap_access_table dspi_volatile_table =3D { - .yes_ranges =3D dspi_volatile_ranges, - .n_yes_ranges =3D ARRAY_SIZE(dspi_volatile_ranges), -}; - -static const struct regmap_config dspi_regmap_config =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D SPI_RXFR3, - .volatile_table =3D &dspi_volatile_table, - .rd_table =3D &dspi_access_table, - .wr_table =3D &dspi_access_table, -}; - -static const struct regmap_config dspi_xspi_regmap_config[] =3D { - { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D SPI_SREX, - .volatile_table =3D &dspi_volatile_table, - .rd_table =3D &dspi_access_table, - .wr_table =3D &dspi_access_table, - }, - { - .name =3D "pushr", - .reg_bits =3D 16, - .val_bits =3D 16, - .reg_stride =3D 2, - .max_register =3D 0x2, - }, -}; - static int dspi_init(struct fsl_dspi *dspi) { unsigned int mcr; @@ -1305,7 +1321,6 @@ static int dspi_target_abort(struct spi_controller *h= ost) static int dspi_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; - const struct regmap_config *regmap_config; struct fsl_dspi_platform_data *pdata; struct spi_controller *ctlr; int ret, cs_num, bus_num =3D -1; @@ -1388,11 +1403,8 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } =20 - if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) - regmap_config =3D &dspi_xspi_regmap_config[0]; - else - regmap_config =3D &dspi_regmap_config; - dspi->regmap =3D devm_regmap_init_mmio(&pdev->dev, base, regmap_config); + dspi->regmap =3D devm_regmap_init_mmio(&pdev->dev, base, + dspi->devtype_data->regmap); if (IS_ERR(dspi->regmap)) { dev_err(&pdev->dev, "failed to init regmap: %ld\n", PTR_ERR(dspi->regmap)); @@ -1403,7 +1415,7 @@ static int dspi_probe(struct platform_device *pdev) if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) { dspi->regmap_pushr =3D devm_regmap_init_mmio( &pdev->dev, base + SPI_PUSHR, - &dspi_xspi_regmap_config[1]); + &dspi_regmap_config[DSPI_PUSHR]); if (IS_ERR(dspi->regmap_pushr)) { dev_err(&pdev->dev, "failed to init pushr regmap: %ld\n", --=20 2.34.1