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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:53 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:49 +0300 Subject: [PATCH v5 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-dpu-drop-features-v5-30-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9308; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=dgx5X1yBWFmdPYdJIyIJkCBg1wG8k1o1xqWmN09qE7Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3UASwCzosHgATZQUnLox3XCPuv+4AVOC29Tj MumKA94GnWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC91AAAKCRCLPIo+Aiko 1cbUCACJvWLcGeFkg+EAr5zx6HgmYzUF2dvnrwysp2WFEjMLCMkVCj2dk0Ovje2soVWWQTHj50s Vz095jwZ7VFHI5yivyNwPsoSxm8U5fE4DFFXphvSdQzIiNoBrKlI5pjnmstVHxc1hOngUehz4Hg 7AmvbIeS4TvSrMT4TDJvbLWDZa5LHioiM1xzm/lehHP7txJ88Ewl+bNQdowA5ZZpZvRh0rYTDz5 jotguW5IHzzCn0TIM902nOUqcD2ddSrqieyju3YSkuBfmZMyaZV//htlbzjln8udBRt30pAig4r n+BOu8P0GhDneFo8WlBgD0KzmginBzQOSi2l2k2nfhYLD927 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 9rYNaZ5uL1ys1Mt-pxvh8sHJoQRVUIwB X-Authority-Analysis: v=2.4 cv=J/Sq7BnS c=1 sm=1 tr=0 ts=682f756e cx=c_pps a=UbhLPJ621ZpgOD2l3yZY1w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=-ycWNAup90JVQjvHN6MA:9 a=QEXdDO2ut3YA:10 a=TOPH6uDL9cOC6tEoww4z:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 9rYNaZ5uL1ys1Mt-pxvh8sHJoQRVUIwB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MiBTYWx0ZWRfX3uEUtewjg4vI +tXT6LaSzmipPmoD81U2yDnYGJ7Fk3M8QTpdbsITy2P89JWIt/qYEEF2LBG8uYjILzuWxjqM2FZ eY9eRmz54R9o2z1XuNCbFzvH31yFXlEUF8rBqCEvsbuMA6fo6mGUyfTlek8+AaDB3rOVY9lp2j7 JCFgZ3BARQ78sckOel2tSycImYlP+Q2n3o5R3r07GrTtYftuw5pYdgLDvpXtnyl2h+BXqYmV3+O ax2H02JricOUARoKA6MlB2MA++29UmavD+uVAKl+a1OvKPTYLi/ZKSubFHB2tWN6J0gGiOpfg4k UOkgdN9LgGKm2LDVn0+1foetMNRbB7ULhLjVzbGeUjDNxxtGKQj6ZiAMffA11yWIOE8UkiwHApf 6v01Giy6o78PAa8FhxW2UFjttdyaTADkmM3AwceELTwlvH8lV4Jk/k93+IBNidLkHRXePhqJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220192 From: Dmitry Baryshkov As features bits are now unused by some of the hardware block configuration structures, remove the 'features' from the DPU_HW_BLK_INFO so that it doesn't get included into hw info structures by default and only include it when necessary. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +++++++-------= --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 ++-- 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index a065f102ce592311376f1186add7a47dca7fd84f..26883f6b66b3e506d14eeb1c0bd= 64f556d19fef8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -20,7 +20,6 @@ static const struct dpu_caps sm6150_dpu_caps =3D { static const struct dpu_mdp_cfg sm6150_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D 0, .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 2950245e7b3f5e38f3f501a7314bb97c66d05982..fbf50f279e6628cb0f92b0188e1= fbdf156a899e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -22,7 +22,6 @@ static const struct dpu_caps sm6125_dpu_caps =3D { static const struct dpu_mdp_cfg sm6125_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D 0, .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index d51f6c5cdf62f3c00829167172ef6fd61f069986..47d82b83ac5378cb0001b3ea660= 5dc0f98aec5ef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -154,14 +154,12 @@ enum { * @id: enum identifying this block * @base: register base offset to mdss * @len: length of hardware block - * @features bit mask identifying sub-blocks/features */ #define DPU_HW_BLK_INFO \ char name[DPU_HW_BLK_NAME_LEN]; \ u32 id; \ u32 base; \ - u32 len; \ - unsigned long features + u32 len =20 /** * struct dpu_scaler_blk: Scaler information @@ -376,7 +374,6 @@ struct dpu_clk_ctrl_reg { /* struct dpu_mdp_cfg : MDP TOP-BLK instance info * @id: index identifying this block * @base: register base offset to mdss - * @features bit mask identifying sub-blocks/features * @clk_ctrls clock control register definition */ struct dpu_mdp_cfg { @@ -392,6 +389,7 @@ struct dpu_mdp_cfg { */ struct dpu_ctl_cfg { DPU_HW_BLK_INFO; + unsigned long features; unsigned int intr_start; }; =20 @@ -407,6 +405,7 @@ struct dpu_ctl_cfg { */ struct dpu_sspp_cfg { DPU_HW_BLK_INFO; + unsigned long features; const struct dpu_sspp_sub_blks *sblk; u32 xin_id; enum dpu_clk_ctrl_type clk_ctrl; @@ -424,6 +423,7 @@ struct dpu_sspp_cfg { */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; + unsigned long features; const struct dpu_lm_sub_blks *sblk; u32 pingpong; u32 dspp; @@ -434,7 +434,6 @@ struct dpu_lm_cfg { * struct dpu_dspp_cfg - information of DSPP blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * supported by this block * @sblk sub-blocks information */ @@ -447,7 +446,6 @@ struct dpu_dspp_cfg { * struct dpu_pingpong_cfg - information of PING-PONG blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * @intr_done: index for PINGPONG done interrupt * @intr_rdptr: index for PINGPONG readpointer done interrupt * @sblk sub-blocks information @@ -464,8 +462,6 @@ struct dpu_pingpong_cfg { * struct dpu_merge_3d_cfg - information of DSPP blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features - * supported by this block * @sblk sub-blocks information */ struct dpu_merge_3d_cfg { @@ -483,6 +479,7 @@ struct dpu_merge_3d_cfg { */ struct dpu_dsc_cfg { DPU_HW_BLK_INFO; + unsigned long features; const struct dpu_dsc_sub_blks *sblk; }; =20 @@ -490,7 +487,6 @@ struct dpu_dsc_cfg { * struct dpu_intf_cfg - information of timing engine blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * @type: Interface type(DSI, DP, HDMI) * @controller_id: Controller Instance ID in case of multiple of intf = type * @prog_fetch_lines_worst_case Worst case latency num lines needed to pre= fetch @@ -521,6 +517,7 @@ struct dpu_intf_cfg { */ struct dpu_wb_cfg { DPU_HW_BLK_INFO; + unsigned long features; u8 vbif_idx; u32 maxlinewidth; u32 xin_id; @@ -589,6 +586,7 @@ struct dpu_vbif_qos_tbl { */ struct dpu_vbif_cfg { DPU_HW_BLK_INFO; + unsigned long features; u32 default_ot_rd_limit; u32 default_ot_wr_limit; u32 xin_halt_timeout; @@ -606,7 +604,6 @@ struct dpu_vbif_cfg { * @name string name for debug purposes * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features */ struct dpu_cdm_cfg { DPU_HW_BLK_INFO; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_dsc_1_2.c index b9c433567262a954b7f02233f6670ee6a8476846..b3395e9c34a19363019ec0ccfb0= c87943553b4c9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c @@ -360,8 +360,7 @@ static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu= _hw_dsc *hw_dsc, DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg); } =20 -static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops, - const unsigned long features) +static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops) { ops->dsc_disable =3D dpu_hw_dsc_disable_1_2; ops->dsc_config =3D dpu_hw_dsc_config_1_2; @@ -391,7 +390,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_devic= e *dev, =20 c->idx =3D cfg->id; c->caps =3D cfg; - _setup_dcs_ops_1_2(&c->ops, c->caps->features); + _setup_dcs_ops_1_2(&c->ops); =20 return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_merge3d.c index 0b3325f9c8705999e1003e5c88872562e880229b..83b1dbecddd2b30402f47155fa2= f9a148ead02c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -33,8 +33,7 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_m= erge_3d *merge_3d, } } =20 -static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, - unsigned long features) +static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c) { c->ops.setup_3d_mode =3D dpu_hw_merge_3d_setup_3d_mode; }; @@ -62,7 +61,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_d= evice *dev, =20 c->idx =3D cfg->id; c->caps =3D cfg; - _setup_merge_3d_ops(c, c->caps->features); + _setup_merge_3d_ops(c); =20 return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 5c811f0142d5e2a012d7e9b3a918818f22ec11cf..96dc10589bee6cf144eabaecf9f= 8ec5777431ac3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -264,7 +264,7 @@ static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *m= dp, } =20 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, - unsigned long cap, const struct dpu_mdss_version *mdss_rev) + const struct dpu_mdss_version *mdss_rev) { ops->setup_split_pipe =3D dpu_hw_setup_split_pipe; ops->setup_clk_force_ctrl =3D dpu_hw_setup_clk_force_ctrl; @@ -313,7 +313,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device= *dev, * Assign ops */ mdp->caps =3D cfg; - _setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev); + _setup_mdp_ops(&mdp->ops, mdss_rev); =20 return mdp; } --=20 2.39.5