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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:44 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:44 +0300 Subject: [PATCH v5 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-dpu-drop-features-v5-25-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14624; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=AvH0+m/lcq7fYeoRmjqLFbsVRzIu9NAfIv+c2dZOgqc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3T/K87DFWOOs9sUYduaoPHtiFnKMQ+vT5y6Q nzAoQn6PrmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC90/wAKCRCLPIo+Aiko 1fqtB/9KvXoY5LQ7Yhg5vpBdBujHtE1rnj9R9GsShoDpOa+5Jhe/Aohza/6mjFZxoRQ0IdDxhBe MqpMZimhdwtY9fEsGCyhj24gv1gAMzU8f3CAiFK6+5sXDKFSjOLwKNI/Z9kMEUd2ca3AgMFM3e2 hk8TDeqWQCSeX5KE0QIWhuaFgS93Syys+fVsxQx33xf31CfA1BAlNVrGwp3NjydFvEd29cDLwRb qaiNZBCtw1Ev3g/K/+niHrF4Bgdgbv3sJgVrP9lMK/3Gw5By9/7UTkOR/OmAiH2NyLtP06YT/3Y +5kkmxTdBCFwVclyAKCkGLzpTh3DKfBac4UmTNrmxVms0gpU X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=WJl/XmsR c=1 sm=1 tr=0 ts=682f7551 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=qMlBm1ryi7ijQuv_G2cA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: n4aBrwxbelIHVjvbRKyVlYLln7rmhSJI X-Proofpoint-GUID: n4aBrwxbelIHVjvbRKyVlYLln7rmhSJI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MiBTYWx0ZWRfXw9psA994F1Nj QP9VMsaPcWn3zUNG3PQHuMmiL/HvCjRV8lVt0t37K6qOcKqNGL7YUfWz/5xdV/R3eNH6Z1nsaNy ApTYy2q2muD+7q+NmxZIy9dKvlv+PAmDhAFRZ/G9lJNR3XZRJG7Muxn7ieDDCHjlodyuawFXvEw pDKZG9cRK/tPw1SM5f+0qqStY0H3nX5PumUkkwZd/RkOLkJXpHzo9a40QVszJGqaXikKnmoJlI5 BybkF1kFNFuAE7g00Di+IqsZ3wEVVgaVhF0eJEPds+6MkdXtUUQcBINM/6dC/LwsKDgbtOnRRyU yE8YTS5MSrG/jH8DsioWAcNn0UN2UmSvtuieGbw0rsQi4HuqP04ocWoqulGRFFGLX4Upt5GtkRW kaANDIVZaGFRE3eHH3tWMuAoe5jyo4SlQxq7IuH7vEFL5SyXaOHDTeaOIa4RDVCWGdjdBjs/ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 adultscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220192 Continue migration to the MDSS-revision based checks and replace DPU_WB_INPUT_CTRL feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- 19 files changed, 17 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 013314b2e716a6d939393b77b0edc87170dba27b..56d3c38c87781edb438b277c773= 82848b679198f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -318,7 +318,7 @@ static const struct dpu_wb_cfg sm8650_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 5d3b864d28a86fb86fc4576210c9418604afd844..ae1b2ed96e9f10a6e7a710fc8bb= 4e40dec665cf9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -275,7 +275,7 @@ static const struct dpu_wb_cfg sm8150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index a6e9dfc583f283d752545b3f700c3d509e2a2965..fc80406759cd52f0d633927c8ba= 876feaff48e07 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -281,7 +281,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca..a56c288ac10cd3dfe8d49a6e476= b9fff062f8003 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -241,7 +241,7 @@ static const struct dpu_wb_cfg sm7150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 8fb926bff36d32fb4ce1036cb69513599dc7b6b7..a065f102ce592311376f1186add= 7a47dca7fd84f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -154,7 +154,7 @@ static const struct dpu_wb_cfg sm6150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 5c2c8c5f812347970c534769d72f9699e6e7049a..2950245e7b3f5e38f3f501a7314= bb97c66d05982 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -133,7 +133,7 @@ static const struct dpu_wb_cfg sm6125_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 9ceff398fd6f554085440f509b6f8398b4fbf304..7b8b7a1c2d767eafca7e7440098= bb28e2e108902 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -312,7 +312,7 @@ static const struct dpu_wb_cfg sm8250_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index f6a0f1a39dcc3c9e82c07889d71905434274cdf9..c990ba3b5db02d65934179d5ad4= 2bd740f6944b2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -148,7 +148,7 @@ static const struct dpu_wb_cfg sc7180_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a..093d16bdc450af348da1775ff01= 7d982236b11b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -142,7 +142,7 @@ static const struct dpu_wb_cfg sm6350_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b..85aae40c210f3aa1b29bf0b5ea8= 1ee1f551a6ef6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -285,7 +285,7 @@ static const struct dpu_wb_cfg sm8350_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 5d88f0261d8320a78f8d64c9bb68b938f83160a0..8f978b9c345202d3ea1a7781e4e= f2763b46c6f6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -159,7 +159,7 @@ static const struct dpu_wb_cfg sc7280_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3c0728a4b37ea6af25ab64315cfe63ba6f8d2774..b09a6af4c474aa9301c0ef6bc0c= e71ba42cce3a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -298,7 +298,7 @@ static const struct dpu_wb_cfg sm8450_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index b8a1646395916fde04b9750cf548edca5729d9c2..0f7b4a224e4c971f482c3778c92= e8c170b44223f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -305,7 +305,7 @@ static const struct dpu_wb_cfg sa8775p_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c..465b6460f8754df18bbcf4baac2= f8a3ebdea3324 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sm8550_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index 2e7d4403835353927bc85a5acd3e6c5967cac455..6caa7d40f368802793c8690544c= 1c82b49a617cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sar2130p_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6..7243eebb85f36f2a8ae848f2c95= d21b0bc3bebef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index ad0460aa5b5ce5a373dab18c89e4159855da4d2b..6d7be74bafe326a1998a69ed9b3= 495c5acf6350f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -98,9 +98,6 @@ BIT(DPU_WB_QOS_8LVL) | \ BIT(DPU_WB_CDP)) =20 -#define WB_SM8250_MASK (WB_SDM845_MASK | \ - BIT(DPU_WB_INPUT_CTRL)) - #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 41906dadff5a8ef39b2e90f3e80bb699a5cf59b7..8c394e7d6496ca2d120c81c7776= b4b979368be23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -140,8 +140,6 @@ enum { * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/c= req * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control * @DPU_WB_CDP Writeback supports client driven prefetch - * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input = pixel - * data arrives. * @DPU_WB_CROP CWB supports cropping * @DPU_WB_MAX maximum value */ @@ -155,7 +153,6 @@ enum { DPU_WB_QOS, DPU_WB_QOS_8LVL, DPU_WB_CDP, - DPU_WB_INPUT_CTRL, DPU_WB_CROP, DPU_WB_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_wb.c index 4853e516c48733231de240b9c32ad51d4cf18f0d..478a091aeccfc7cf298798e1c11= 9df56737e3dc4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -208,7 +208,7 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, if (test_bit(DPU_WB_CDP, &features)) ops->setup_cdp =3D dpu_hw_wb_setup_cdp; =20 - if (test_bit(DPU_WB_INPUT_CTRL, &features)) + if (mdss_rev->core_major_ver >=3D 5) ops->bind_pingpong_blk =3D dpu_hw_wb_bind_pingpong_blk; =20 if (mdss_rev->core_major_ver >=3D 9) --=20 2.39.5