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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:40 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:42 +0300 Subject: [PATCH v5 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-dpu-drop-features-v5-23-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14207; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=2pUPR12iDS3m0TMaHz0bJCFdiC/MPlCtiYT3r9GpT0U=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3T/ByDcPnvvkbWYuVeCr4Q+6KVkRxsuw9dlf zVjdKvxzoCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC90/wAKCRCLPIo+Aiko 1YESCACz4/17gptjaKpu036M7oW2RAmH+Wk3mLkJLjXRjMrmzSGqavyVje0l607Nr78nTdCpbLn UF95zwpueD5oH9x14YqGxnxrwlwmEPb3AGzBsHrSdatGjvevzyfQIHKfnUuKfDegAzbgU5MPhtt v8nj8uCYOzgA/Ly4SmUuRyeHvNZO1yG23878bIyw7xbZjRE6gJDlyxg4HWW5sOhLfXFUg8Buer7 v7Y3zv8/1JYbkGGTpsyHKaUqZx9QXstxvADApA63apAZPskKjnrLNmkvlcnSbv9ryQP2qJb+CSk RmdE8POB7A3ivl5kzD5xCaLzo5HiK9/BtXXnqYpidDfi/IXZ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=QKBoRhLL c=1 sm=1 tr=0 ts=682f754d cx=c_pps a=5fI0PjkolUL5rJELGcJ+0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=NuLJBD-5AyVUfQYi_k8A:9 a=QEXdDO2ut3YA:10 a=HaQ4K6lYObfyUnnIi04v:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: HQNi6SuEUJOsJfmrI-QXWWuC-QPQ4TKc X-Proofpoint-GUID: HQNi6SuEUJOsJfmrI-QXWWuC-QPQ4TKc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MSBTYWx0ZWRfX212mUqZp1wgI uHb96n+VGhjx9VfG24F3QtD4jSrt5itYmT+r5m4HjI3gyN04z7fiFzp0xUXGFJtwUgs5EUEEtfn KFWwwAe49PkyoKVyz1VLlvSz8t6K4MscCt7XqpCLzqcn1jC/rMvtjV8AeYUm0Fe/+jgbj6EkzdS eoZnHv8qV7pPuDAxbJv5WEqmMGZz4+S7ssnOr7n3ALLuSJVr1Wsb7FtMXtYjw5uLyX98miWGcSj xVrJqMgyr1tS0VDG1erh1e095Pocvqps1BUbu3nlJck6Iyrr8OoYEYXdlDXp5Q6vjKQ/J2te2lK hLNpmEavlNNttxDF6UR4OiNfQS6Ly+zQkzx/XJpTYohOvO/5KH5w8s87XhrZMZuGOMBBvzzvmOp D/gzJ4kPNkj82FN2CFBculuTwRztMRpxYA8E/DUn32IVNqf3NfBBU5ZBLHCZR8tPilMJMHk6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220191 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 12 files changed, 21 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 9a8f6043370997cb12414c4132eb68cc73f7030a..013314b2e716a6d939393b77b0e= dc87170dba27b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -286,32 +286,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index e81a2a02e0a6379382058fd89500cf2064a2193f..b4d41e2644349bdbdbdacbe1e9b= 3748f90df4f3b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -263,22 +263,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d..5d88f0261d8320a78f8d64c9bb6= 8b938f83160a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 2cf30234e45da8a7776d61c49c26abd75d070941..303d33dc7783ac91a496fa0a198= 60564ad0b6d5d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -262,32 +262,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index dcef56683224b5715c2608b5472d2d5a0da62010..3c0728a4b37ea6af25ab64315cf= e63ba6f8d2774 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -276,22 +276,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 5f5987d5fc602df29c5eb289823de5dd359df014..b8a1646395916fde04b9750cf54= 8edca5729d9c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -275,32 +275,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 6f310216fbccb985308f617db20c1878e622340a..ef22a9adf43ddc9d15be5f1359e= a5f6690e9f27c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd..2e7d4403835353927bc85a5acd3= e6c5967cac455 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sar2130p_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 77986a7bd62c1b6323482426e596e5974ba40865..ac95d46b3ecf2d95ec0d516a795= 67fe9c204b5f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315..01430ff90ab0988bdaa91b85458= dd649aab543b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -176,13 +176,11 @@ enum { * DSC sub-blocks/features * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets * the pixel output from this DSC. - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_HW_REV_1_2, DPU_DSC_NATIVE_42x_EN, DPU_DSC_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42..d478a7bce7568ab000d73467bca= d91e29f049abc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, "%s", cat->dsc[i].name); =20 - if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { + if (cat->mdss_ver->core_major_ver >=3D 7) { struct dpu_dsc_blk enc =3D cat->dsc[i].sblk->enc; struct dpu_dsc_blk ctl =3D cat->dsc[i].sblk->ctl; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 7bcb1e057b143a5512aafbd640199c8f3b436527..c2a659512cb747e1dd5ed9e2853= 4286ff8d67f4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -168,7 +168,7 @@ int dpu_rm_init(struct drm_device *dev, struct dpu_hw_dsc *hw; const struct dpu_dsc_cfg *dsc =3D &cat->dsc[i]; =20 - if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features)) + if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); else hw =3D dpu_hw_dsc_init(dev, dsc, mmio); --=20 2.39.5