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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:28 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:38 +0300 Subject: [PATCH v5 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-dpu-drop-features-v5-19-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8072; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Qi0NNNo/ojFGNk6vS+7/bJMwBSgR2imtHjPMD1duIkM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3T+wySmWg7YfVngh+Td4RycmAZl5rljsGgEs WySFuwl+AWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC90/gAKCRCLPIo+Aiko 1U9eB/40od/EbrZgTV/Hf/dOGbu59uGgoLNGpP4xxBPkpiO9O+8bmNGuL2Fmc4TiqhlFuE+/vyO UhsB8MbbmVa+m+QQK9QLJpUIMfQ/HmD8sSy3PrzAiriXHEDc0+6Sd4xvFKxV2XtB8GF0Ae340iw 6r+z0y6ICPKDxEtRVKhhtdQOOcyiVdVNQWNzlsxktgS8BwE/aAy76d0sKvrLnMoBmoyyAuIk1s5 m2W1IM8eHy/gB9ITjbAZnTG4/ryojO1VOCwCDD9bf99V8BUxBeYf3l9TBz45zQbx6mj3aAUl0RV pp0hgJYzX10FaJtk4GRx0rU4wS9U9y+2Q922L89I3gzNjm/f X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=V9990fni c=1 sm=1 tr=0 ts=682f7549 cx=c_pps a=WJcna6AvsNCxL/DJwPP1KA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=mpK4J0can4W2gMZkP7IA:9 a=QEXdDO2ut3YA:10 a=_Y9Zt4tPzoBS9L09Snn2:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 47oY0Y06PypzC-RSWHSeGpPWeOroe2u1 X-Proofpoint-GUID: 47oY0Y06PypzC-RSWHSeGpPWeOroe2u1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MiBTYWx0ZWRfXwk7KEf+/JbOo Uc0ci69XY7XSfV+opCXSYf/TXtfBNDU9R0BbfH7GNjSbDqa1oJyQKaHBk6j4Z6hHoeN+bvlP4o9 iZG1RGBd5VyNS0Nolnu5CnDHEpkDm5WuAxkGuzUO6SvKivBrmrTk836CFfGYr9Y9QGRBIm7ubWb Z9GnGpE4wZL1fxP+jxdhFEAMlpWarrid+bJUBWifm4B4uyy6M2zic6JgTumjFlTTa1AIKznu6cd rY6eqRBUo33vl0NCfhtRiYRes9s+4NT4wQs9qv5OkSicd3HTK15osKOKT1PtPPxd4oXZBYyT9dJ BlsUNzsijioSTKzxgbG4L0CkuiZ32ny3gPQUw6aSaF5PQsF2MI+cRg8GeeU1iBeZ8w9HHw9MsK7 bdeeIQxMZQMM8WObRwZS/6/rb2ehdV7zVB6XVMFGVsTDJ1Wmz0xqbdKBrwIgjPJdzu0+yNvn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 mlxscore=0 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220192 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >=3D 8 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- 10 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 37c88b393c12d8a04395b6e5dffb67211d2db9cd..ae66c338250664f9306a7d431cf= a18ca07a916a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8650_dpu_caps =3D { static const struct dpu_mdp_cfg sm8650_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 785ca2b2e60f073b0a2db0c0c4ed3b2722de033c..85778071bc1347008dbe4522aeb= 9ca4fd21aa097 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -21,7 +21,6 @@ static const struct dpu_caps sc8280xp_dpu_caps =3D { static const struct dpu_mdp_cfg sc8280xp_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 1401a84e0da5754fd2a3661d1421bb9b998271ca..f9676f804f9132296467bc751e1= 1036696afa942 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8450_dpu_caps =3D { static const struct dpu_mdp_cfg sm8450_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9..7462cfc4cf8de4a10326c83d334= 1dbee76e437e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -20,7 +20,6 @@ static const struct dpu_caps sa8775p_dpu_caps =3D { static const struct dpu_mdp_cfg sa8775p_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index cc4413432cfdc636e38a56011d39f18d7e94c23a..695ae7581a88b36fa1f28aa3cd0= c9166090e940c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8550_dpu_caps =3D { static const struct dpu_mdp_cfg sm8550_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index 32f88533154584dc98a515b1ddef27ab2005fecd..9a25113df5aec527baa514aaa61= f2b47c2443d27 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -21,7 +21,6 @@ static const struct dpu_caps sar2130p_dpu_caps =3D { static const struct dpu_mdp_cfg sar2130p_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index e053324d76a2e5020e6a7477ddadc9f7d94fe57e..54815c613f087454aa7b4befc84= 462265d8dfc23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -20,7 +20,6 @@ static const struct dpu_caps x1e80100_dpu_caps =3D { static const struct dpu_mdp_cfg x1e80100_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44..d3a7f46488a21e81a24a9af5071= a9a7f5f48cdac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -32,8 +32,6 @@ * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats - * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block re= sults - * in a failure * @DPU_MDP_MAX Maximum value =20 */ @@ -41,7 +39,6 @@ enum { DPU_MDP_PANIC_PER_PIPE =3D 0x1, DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, - DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index cebe7ce7b258fc178a687770906f7c4c20aa0d4c..c49a67da86b0d46d12c32466981= be7f00519974c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, =20 if (mdss_rev->core_major_ver < 5) ops->setup_vsync_source =3D dpu_hw_setup_vsync_sel; - else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) + else if (mdss_rev->core_major_ver < 8) ops->setup_vsync_source =3D dpu_hw_setup_wd_timer; =20 ops->get_safe_status =3D dpu_hw_get_safe_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 1fd82b6747e9058ce11dc2620729921492d5ebdd..80ffd46cbfe69fc90afcdc1a144= fc5de7bb6af42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1022,7 +1022,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k dpu_kms->mmio + cat->wb[i].base, "%s", cat->wb[i].name); =20 - if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + if (dpu_kms->catalog->mdss_ver->core_major_ver >=3D 8) { msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, dpu_kms->mmio + cat->mdp[0].base, "top"); msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP= 0_END, --=20 2.39.5