From nobody Sun Dec 14 12:16:59 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A9542BF3C2 for ; Thu, 22 May 2025 19:04:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747940654; cv=none; b=HFwa6lHjeMjfKdjGTJQ9GqLP5Ju1qWGx7aSJXPs99y5VNUuuJkpEHOFoyjk9aBhWTdJfVzISz/NY6PdAeKv7SKcmOhOohJLb5wW+usbIjUoDFEhm8OFFcyYoe1fi8fkbjztsIJ/97icLBT4cI/Sq332Dkkk3EQWyYk5Ut9YooZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747940654; c=relaxed/simple; bh=IBOdvAi4zoG/rA+TrDbUIbU5YKy9vCpRbdTOVGzRJjc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DWYy1jHTEGCrrsSsu27GYVQi4mr6nxpfdBAJ34mL6N2wEaskyqIZpYv16BpjMqO1A+KxRONNsD3/Y4v892dMbHCxZnPavfSl+OHPxCyYadhyrMySmwPdeo5DQaTGLgvmqga84PIy4Md7MYjVBfQ2nFciVpuB4Y/DcZXfr9/jgRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=W4PHLOBA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="W4PHLOBA" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54MI5NLL011354 for ; Thu, 22 May 2025 19:04:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jrmL4KXzGUfPUzCokAbLgPfU4jMCQqdkBU6ZAzVap6A=; b=W4PHLOBA6yWirSIR mXchwlDn673u2YqSq/ewahy6JASksyB47wKhaR/dhAc0t6TUVgAOyhqhXq731Cq6 miPVPsnAezCSoQTFc57dECzJLwx9CKOtEtAs76O8NJY5rpaN7EgMSje9y7o8YhfM bdkPHqE3KuIDh0cflprUX2Hu0NRSf3z8ihP4RLYkO54H9Lb9ObJVKNp8oTiVAfyI N52FKz6UG7d1Tw8VkpDjSZmVODQzYicikCtNRpr9pgqQByx+CyPNll5l5iQf/6JM c/Wu6rKJPsaOPA68HFGJ8v8lZie/A++Mg8kFOZ/EEIAaQ6DbX/4jfJ6C7FFtWBKg weWpBw== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46rwfb7b5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 22 May 2025 19:04:10 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-7caef20a528so2141705785a.0 for ; Thu, 22 May 2025 12:04:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747940647; x=1748545447; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jrmL4KXzGUfPUzCokAbLgPfU4jMCQqdkBU6ZAzVap6A=; b=LudqVuxFZH0zlpp0noFE6Q6b2Eg9qdW/b120yM6gPPZDsil/V8qBqJEkhagUtFOvBS riJEoXgQK9d01MS3PWLUY2B0lJEoTy3y+ZTwEs7b9nEYgsTC3N0ddg0QnnxJqqRXdpQe 4V4jdQLk8uPPU9zcVRVQL93ffOJ/rMW1VIWvCQbUNz7OCu9W0iBG02g9k6JJu79FaPRb PN0DbGQ1ayUmX8RtgnijvQ0Ygpb2cj4iAX8cDClH+bjBriiuoOlNRRF3x58J2F8NFwo7 lOvNoFCLQ1alail4wzN26Wj343qVLYJ5Ecxm9LoV+JOZpYUll7o2B8D19vD4rPW2q13D gq5g== X-Forwarded-Encrypted: i=1; AJvYcCVc2getjoeVeqKKneZUq6Bo8Wg15gM0Ao4U29FeYxJMuQSSpjeCLyHBSeF58d95FR2nPit01qQocH5XZDg=@vger.kernel.org X-Gm-Message-State: AOJu0YwXZgDgtS/pSPG1rEHguj4+NrN5vklCyp1jEXfJs6IzIspyAhwa kkb3yoiWf0OZXBxzmQaetUJnaHfdfAQSZhiZKzrb056ufQLv85gikOLcdgc8i3mYNJoiIeBrHCV 06v2qSD9mp2SGMO74LtqIUqfgcp3Vsf+HsZcdpqc1Qe3QzVRiHPpiqz58Qao4NX1sMg3WZ9peyf 8= X-Gm-Gg: ASbGncva5ULMj+k95lBGN8rWbTz7uS2+zBe0tB16R0TCWPIrCEm3dQfweEd4foNW/76 6p8X3vcX6MiXSvNCfwVO2Hq9R7XM1GAWJPI5MqM23D0HZlRYH0ZJ4A/2mZ7iIvEcLT1gzDsXCTh J4fnJVsOhfIDzIBK2H4VYk8rsK3Fq743kK7i3Ift2rtOPjZTkTRF1d7o/3oyb9LAqPv7idEdYKq APeUab41d8gFHB/iUSXLeAfQpjRsP64yg72UlHguqdU/7IYOjvrCYY43pNwVLAFBI0KdZyn1PsL orbVQMMqmXfbXAdvFSuwTBV8bP6rJur53FCqQdApxmOq0xVV59Ozj2X+BJoIeIeiSsY3hXaOMIA o4u6w2lMUvkxRy/w7mL743yl7 X-Received: by 2002:a05:620a:bc4:b0:7ca:f3ac:9eae with SMTP id af79cd13be357-7cd47f4e05bmr3524019985a.30.1747940647150; Thu, 22 May 2025 12:04:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEaok1w26NpJcA+0Y6ZF/oWrRabFmCrBIdEFyxytQ5/z49p8Kd4nxIBccPjDkri+2xFFysNmQ== X-Received: by 2002:a05:620a:bc4:b0:7ca:f3ac:9eae with SMTP id af79cd13be357-7cd47f4e05bmr3524016785a.30.1747940646731; Thu, 22 May 2025 12:04:06 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703c2f3sm3482506e87.214.2025.05.22.12.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 12:04:04 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:31 +0300 Subject: [PATCH v5 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250522-dpu-drop-features-v5-12-3b2085a07884@oss.qualcomm.com> References: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> In-Reply-To: <20250522-dpu-drop-features-v5-0-3b2085a07884@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15653; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=VMCzGo1aaigqZYNYCi6bGBuVqybCE2/hi7mFwhs0Juc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoL3T9dfYtg41QXV7Yw5HOMjk+fx8OovjyuXoQq JiDjgbvzquJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaC90/QAKCRCLPIo+Aiko 1RRxCACcyXNEWtdsYW+XUefcA5/e1n/FxSg4ed2c6qJXpx9fh+wIimBb3MxbaZL19xUEUE3PPnh yJpU/IbFcSbQWvJ5n97GdQsaGvi15MCdqnCRCjI29C7ind3rX2xNxXaKfE4dZ0HhLuvfxWFxadQ +6FyRGL1BAu6z0EPImSI079qccH84UEqEcsrRHnb9ZvOfPqaG3OeGavFM3GZ8Oze9b5Uv+FbE79 1wQV1iOftRvwFwxvT5T+lSQJpffuKgidVzdSb9YHW/gAfSn+Thzii/ZM4TbmBAcb+FvDWjRoZqk SEYyMgjHyZAMh9ed7d+Yp4ym9VQAobBJSc1suhABQENLSGOe X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: hisXUp52ex0fl8HmRPi1UpVYC3F6_uoV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIyMDE5MSBTYWx0ZWRfX8S9cm88bC8eL ao9ALeLt/vcySGMRXKpjzURWS9sWLxsd5R/ij2VZCXhhXAO+fE/sZ/3Q7spdu8A0yhF4ZshYVJn i4Q2+lfMZQVJ28yXsHilXb4Ydf3v3HueK8WiOZFTSvBWeqVJjNQgBfvIIx9PJiD3wmhGNBuAoQQ WoQIEYOV9ASlIPVVazN8weYznRytSOcrtJjz34cF7dNtdvLpZYwPz56esmS7lE0xhh8OmhWdUAx Gh2bEBucfC0mBNOTsNjBIou3IEO5v3kNU/GwsPzmx6VXPPGK9cPG+raeZ/wrPzsQKmPkgDopFMR moZ4CVcB+fv/CYcWDILBUfjDnnOZ45v6kBEn1q3uls7fViKgb46RCnKXlSbfggR1d/zyHO9aR1p OJlcCJreLbKZf8QhXBBeBxWEKs3dKttgkjT4fWfnVAH4UYT4MZDrqCkE1zumhWP0zLbzwi6Q X-Proofpoint-GUID: hisXUp52ex0fl8HmRPi1UpVYC3F6_uoV X-Authority-Analysis: v=2.4 cv=dLCmmPZb c=1 sm=1 tr=0 ts=682f752a cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=HAIgJQPtztWyLQ5mXWkA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-22_09,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505220191 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_CTL_VM_CFG feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- 12 files changed, 1 insertion(+), 58 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 52ad7e2af0148c9ea81a2c95b270be7058fbaec1..bbdb7e1668fee33cb7d99a7cb8a= b001e58f079be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8650_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index bbef0e1c597299d24a923e1f0d977c99afedb8fb..3c6da0acdc3b81db65e2544f16d= 90322fe7e92a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8350_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 281826170da082fc90a05c641060901ece0fbed3..2ee29c56224596b378610409029= 0b88cecf7b223 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -32,22 +32,18 @@ static const struct dpu_ctl_cfg sc7280_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 1dd0a1aa222d65f03013d634a87371dc552b5bd8..2f20d0014a94e707a5f0548fc1c= 6bf0983b0cad0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 50142b14e24eb875e72e5cff3b28ff8aba89fc9c..314875e2dca96b3b5c40aae0d15= fb80da8ebd42c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -40,32 +40,26 @@ static const struct dpu_ctl_cfg sm8450_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 264cd6d3640be1bf321fda429748ecdafbeed214..36775f444af4b2654231cd9456a= c4eea1f0f18e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sa8775p_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 83f73c7cdcc3a280285fa32230796fac57167ed6..624f24c8a33a182634d49058014= fc3175f5ac9d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8550_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index b21aab274703ac1f38698bee82d5d28b0fb6a0d0..857dc8465bf5571cd08cf3115fb= 96002873c004b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index d7e5f4dd3bccab125b0a42f67eddf194359dc761..05b0962c2d937f077d0b42fa8af= 6e2da40c7dcae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -30,32 +30,26 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 19a859e2a1f80c2321789af4ec7c5e299f0fb873..5cd87b13e839e7ad60356cde162= 405fdfb6f9498 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -104,9 +104,6 @@ #define PINGPONG_SM8150_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 -#define CTL_SC7280_MASK \ - (BIT(DPU_CTL_VM_CFG)) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 1e5fc1d5873975189a1759212b8a6c6078de22f9..3b6133e1bb581741fe87b049ad0= c89bf30b76019 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -132,12 +132,10 @@ enum { /** * CTL sub-blocks * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display - * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY =3D 0x1, - DPU_CTL_VM_CFG, DPU_CTL_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index edb82c81b0a449b1a7273fc258961b9447be8d9d..fe4fdfb8774b176fb024d76dc0b= d269d9736d226 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -575,7 +575,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *c= tx, * per VM. Explicitly disable it until VM support is * added in SW. Power on reset value is not disable. */ - if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) + if (ctx->mdss_ver->core_major_ver >=3D 7) mode_sel =3D CTL_DEFAULT_GROUP_ID << 28; =20 if (cfg->intf_mode_sel =3D=3D DPU_CTL_MODE_SEL_CMD) --=20 2.39.5