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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:09:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 01/12] soc: renesas: rz-sysc: Add syscon/regmap support Date: Wed, 21 May 2025 17:09:32 +0300 Message-ID: <20250521140943.3830195-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: John Madieu The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, add register a custom regmap configuration. Signed-off-by: John Madieu [claudiu.beznea: - s/rzg3e_sysc_regmap/rzv2h_sysc_regmap in RZ/V2H sysc file - do not check the match->data validity in rz_sysc_probe() as it is always valid - register the regmap if data->regmap_cfg is valid] Signed-off-by: Claudiu Beznea --- Changes in v3: - none, this patch is new, it was picked from John after he addressed the review comments received at [1]; - I adjusted as specified in the SoB area, and included it here as it is the base for the signal support presented in the next commits [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.r= enesas.com/ drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 10 ++++++++++ drivers/soc/renesas/r9a09g047-sys.c | 10 ++++++++++ drivers/soc/renesas/r9a09g057-sys.c | 10 ++++++++++ drivers/soc/renesas/rz-sysc.c | 17 ++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 3 +++ 6 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fbc3b69d21a7..f3b7546092d6 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -437,6 +437,7 @@ config RST_RCAR =20 config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON =20 config SYSC_R9A08G045 bool "Renesas RZ/G3S System controller support" if COMPILE_TEST diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index f4db1431e036..0ef6df77e25f 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -18,6 +18,16 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_= soc_id_init_data __initc .specific_id_mask =3D GENMASK(27, 0), }; =20 +static const struct regmap_config rzg3s_sysc_regmap __initconst =3D { + .name =3D "rzg3s_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0xe20, +}; + const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, + .regmap_cfg =3D &rzg3s_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index cd2eb7782cfe..a3acf6dd2867 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_s= oc_id_init_data __initco .print_id =3D rzg3e_sys_print_id, }; =20 +static const struct regmap_config rzg3e_sysc_regmap __initconst =3D { + .name =3D "rzg3e_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzg3e_sys_init_data =3D { .soc_id_init_data =3D &rzg3e_sys_soc_id_init_data, + .regmap_cfg =3D &rzg3e_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 4c21cc29edbc..c26821636dce 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_s= oc_id_init_data __initco .print_id =3D rzv2h_sys_print_id, }; =20 +static const struct regmap_config rzv2h_sysc_regmap __initconst =3D { + .name =3D "rzv2h_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzv2h_sys_init_data =3D { .soc_id_init_data =3D &rzv2h_sys_soc_id_init_data, + .regmap_cfg =3D &rzv2h_sysc_regmap, }; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ffa65fb4dade..70556a2f55e6 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -6,8 +6,10 @@ */ =20 #include +#include #include #include +#include #include =20 #include "rz-sysc.h" @@ -100,14 +102,19 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); =20 static int rz_sysc_probe(struct platform_device *pdev) { + const struct rz_sysc_init_data *data; const struct of_device_id *match; struct device *dev =3D &pdev->dev; + struct regmap *regmap; struct rz_sysc *sysc; + int ret; =20 match =3D of_match_node(rz_sysc_match, dev->of_node); if (!match) return -ENODEV; =20 + data =3D match->data; + sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) return -ENOMEM; @@ -117,7 +124,15 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); =20 sysc->dev =3D dev; - return rz_sysc_soc_init(sysc, match); + ret =3D rz_sysc_soc_init(sysc, match); + if (ret || !data->regmap_cfg) + return ret; + + regmap =3D devm_regmap_init_mmio(dev, sysc->base, data->regmap_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); } =20 static struct platform_driver rz_sysc_driver =3D { diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 56bc047a1bff..447008140634 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -9,6 +9,7 @@ #define __SOC_RENESAS_RZ_SYSC_H__ =20 #include +#include #include #include =20 @@ -34,9 +35,11 @@ struct rz_sysc_soc_id_init_data { /** * struct rz_sysc_init_data - RZ SYSC initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data + * @regmap_cfg: SoC-specific regmap config */ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:09:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 02/12] soc: renesas: rz-sysc: Add signal support Date: Wed, 21 May 2025 17:09:33 +0300 Message-ID: <20250521140943.3830195-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G3S system controller (SYSC) has various registers that control signals specific to individual IPs. IP drivers must control these signals at different configuration phases. Update the SYSC driver to allows individual SYSC consumers to control these signals. The SYSC driver exports a syscon regmap enabling IP drivers to use a specific SYSC offset and mask from the device tree, which can then be accessed through regmap_update_bits(). Currently, the SYSC driver provides control to the USB PWRRDY signal, which is routed to the USB PHY. This signal needs to be managed before or after powering the USB PHY off or on. Other SYSC signals candidates (as exposed in the hardware manual of the RZ/G3S SoC) include: * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=3D0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=3D0..1) Signed-off-by: Claudiu Beznea --- Changes in v3: - this patch is new, however, most of its parts were picked from [1] Compared with [1]: - kept only the signals part - droped double "the" in description - mark init data with __initconst - use flexible arrays to store the signals - simplified the code in rz_sysc_off_to_signal() and rz_sysc_reg_update_bits() as proposed in the review process - dropped rz_sysc_writeable_reg(), rz_sysc_readable_reg() - fixed rz_sysc_signals_init() as it didn't work with more than one signal - embedded rz_sysc_signal_init_data in rz_sysc_signal for simpler memory allocation - added rz_sysc_get_signal_map() and struct rz_sysc_signal_map as a unified helper and data structure to handle a signal - use rz_sysc_reg_read(), rz_sysc_reg_write(), rz_sysc_reg_update_bits() in all the rz-sysc consummers [1] https://lore.kernel.org/all/20241126092050.1825607-3-claudiu.beznea.uj@= bp.renesas.com/ drivers/soc/renesas/r9a08g045-sysc.c | 3 + drivers/soc/renesas/r9a09g047-sys.c | 3 + drivers/soc/renesas/r9a09g057-sys.c | 3 + drivers/soc/renesas/rz-sysc.c | 185 ++++++++++++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 35 +++++ include/linux/soc/renesas/rz-sysc.h | 30 +++++ 6 files changed, 257 insertions(+), 2 deletions(-) create mode 100644 include/linux/soc/renesas/rz-sysc.h diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index 0ef6df77e25f..d2c9e3b77f41 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -25,6 +25,9 @@ static const struct regmap_config rzg3s_sysc_regmap __ini= tconst =3D { .val_bits =3D 32, .fast_io =3D true, .max_register =3D 0xe20, + .reg_read =3D rz_sysc_reg_read, + .reg_write =3D rz_sysc_reg_write, + .reg_update_bits =3D rz_sysc_reg_update_bits, }; =20 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index a3acf6dd2867..fd4018e0aca1 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -69,6 +69,9 @@ static const struct regmap_config rzg3e_sysc_regmap __ini= tconst =3D { .val_bits =3D 32, .fast_io =3D true, .max_register =3D 0x170c, + .reg_read =3D rz_sysc_reg_read, + .reg_write =3D rz_sysc_reg_write, + .reg_update_bits =3D rz_sysc_reg_update_bits, }; =20 const struct rz_sysc_init_data rzg3e_sys_init_data =3D { diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index c26821636dce..cfa5be48f049 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -69,6 +69,9 @@ static const struct regmap_config rzv2h_sysc_regmap __ini= tconst =3D { .val_bits =3D 32, .fast_io =3D true, .max_register =3D 0x170c, + .reg_read =3D rz_sysc_reg_read, + .reg_write =3D rz_sysc_reg_write, + .reg_update_bits =3D rz_sysc_reg_update_bits, }; =20 const struct rz_sysc_init_data rzv2h_sys_init_data =3D { diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 70556a2f55e6..3dd5d444050b 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -5,11 +5,16 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ =20 +#include +#include #include #include #include #include +#include #include +#include +#include #include =20 #include "rz-sysc.h" @@ -20,12 +25,183 @@ * struct rz_sysc - RZ SYSC private data structure * @base: SYSC base address * @dev: SYSC device pointer + * @num_signals: number of SYSC signals + * @signals: SYSC signals */ struct rz_sysc { void __iomem *base; struct device *dev; + u8 num_signals; + struct rz_sysc_signal signals[] __counted_by(num_signals); }; =20 +struct rz_sysc_signal_map *rz_sysc_get_signal_map(struct device *dev) +{ + struct rz_sysc_signal_map *map; + struct of_phandle_args args; + struct regmap *regmap; + int ret; + + if (!dev) + return ERR_PTR(-EINVAL); + + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "renesas,sysc-sign= als", 2, + 0, &args); + if (ret) + return ERR_PTR(ret); + + regmap =3D syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + map =3D devm_kzalloc(dev, sizeof(*map), GFP_KERNEL); + if (!map) + return ERR_PTR(-ENOMEM); + + map->regmap =3D regmap; + map->offset =3D args.args[0]; + map->mask =3D args.args[1]; + + return map; +} + +int rz_sysc_reg_read(void *context, unsigned int off, unsigned int *val) +{ + struct rz_sysc *sysc =3D context; + + *val =3D readl(sysc->base + off); + + return 0; +} + +static struct rz_sysc_signal *rz_sysc_off_to_signal(struct rz_sysc *sysc, = unsigned int offset, + unsigned int mask) +{ + struct rz_sysc_signal *signals =3D sysc->signals; + + for (u32 i =3D 0; i < sysc->num_signals; i++) { + if (signals[i].init_data.offset !=3D offset) + continue; + + /* + * In case mask =3D=3D 0 we just return the signal data w/o checking the= mask. + * This is useful when calling through rz_sysc_reg_write() to check + * if the requested setting is for a mapped signal or not. + */ + if (!mask || signals[i].init_data.mask =3D=3D mask) + return &signals[i]; + } + + return NULL; +} + +int rz_sysc_reg_update_bits(void *context, unsigned int off, unsigned int = mask, unsigned int val) +{ + unsigned int shifted_val =3D field_get(mask, val); + struct rz_sysc *sysc =3D context; + struct rz_sysc_signal *signal; + bool update =3D false; + + signal =3D rz_sysc_off_to_signal(sysc, off, mask); + if (!signal) { + update =3D true; + } else if (signal->init_data.refcnt_incr_val !=3D shifted_val) { + update =3D refcount_dec_and_test(&signal->refcnt); + } else if (!refcount_read(&signal->refcnt)) { + refcount_set(&signal->refcnt, 1); + update =3D true; + } else { + refcount_inc(&signal->refcnt); + } + + if (update) { + u32 tmp; + + tmp =3D readl(sysc->base + off); + tmp &=3D ~mask; + tmp |=3D val & mask; + writel(tmp, sysc->base + off); + } + + return 0; +} + +int rz_sysc_reg_write(void *context, unsigned int off, unsigned int val) +{ + struct rz_sysc *sysc =3D context; + struct rz_sysc_signal *signal; + + /* + * Force using regmap_update_bits() for signals to have reference counter + * per individual signal in case there are multiple signals controlled + * through the same register. + */ + signal =3D rz_sysc_off_to_signal(sysc, off, 0); + if (signal) { + dev_err(sysc->dev, + "regmap_write() not allowed on register controlling a signal. Use regma= p_update_bits()!"); + return -EOPNOTSUPP; + } + + writel(val, sysc->base + off); + + return 0; +} + +static int rz_sysc_signals_show(struct seq_file *s, void *what) +{ + struct rz_sysc *sysc =3D s->private; + + seq_printf(s, "%-20s Enable count\n", "Signal"); + seq_printf(s, "%-20s ------------\n", "--------------------"); + + for (u8 i =3D 0; i < sysc->num_signals; i++) { + seq_printf(s, "%-20s %d\n", sysc->signals[i].init_data.name, + refcount_read(&sysc->signals[i].refcnt)); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(rz_sysc_signals); + +static void rz_sysc_debugfs_remove(void *data) +{ + debugfs_remove_recursive(data); +} + +static int rz_sysc_signals_init(struct rz_sysc *sysc, + const struct rz_sysc_signal_init_data *init_data, + u32 num_signals) +{ + struct dentry *root; + int ret; + + for (unsigned int i =3D 0; i < num_signals; i++) { + struct rz_sysc_signal_init_data *data =3D &sysc->signals[i].init_data; + + data->name =3D devm_kstrdup(sysc->dev, init_data[i].name, GFP_KERNEL); + if (!data->name) + return -ENOMEM; + + data->offset =3D init_data[i].offset; + data->mask =3D init_data[i].mask; + data->refcnt_incr_val =3D init_data[i].refcnt_incr_val; + + refcount_set(&sysc->signals[i].refcnt, 0); + } + + sysc->num_signals =3D num_signals; + + root =3D debugfs_create_dir("renesas-rz-sysc", NULL); + ret =3D devm_add_action_or_reset(sysc->dev, rz_sysc_debugfs_remove, root); + if (ret) + return ret; + debugfs_create_file("signals", 0444, root, sysc, &rz_sysc_signals_fops); + + return 0; +} + static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_i= d *match) { const struct rz_sysc_init_data *sysc_data =3D match->data; @@ -115,7 +291,8 @@ static int rz_sysc_probe(struct platform_device *pdev) =20 data =3D match->data; =20 - sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + sysc =3D devm_kzalloc(dev, struct_size(sysc, signals, data->num_signals), + GFP_KERNEL); if (!sysc) return -ENOMEM; =20 @@ -128,7 +305,11 @@ static int rz_sysc_probe(struct platform_device *pdev) if (ret || !data->regmap_cfg) return ret; =20 - regmap =3D devm_regmap_init_mmio(dev, sysc->base, data->regmap_cfg); + ret =3D rz_sysc_signals_init(sysc, data->signals_init_data, data->num_sig= nals); + if (ret) + return ret; + + regmap =3D devm_regmap_init(dev, NULL, sysc, data->regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 447008140634..111f79ef9573 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -9,10 +9,35 @@ #define __SOC_RENESAS_RZ_SYSC_H__ =20 #include +#include #include #include #include =20 +/** + * struct rz_sysc_signal_init_data - RZ SYSC signals init data + * @name: signal name + * @offset: register offset controling this signal + * @mask: bitmask in register specific to this signal + * @refcnt_incr_val: increment refcnt when setting this value + */ +struct rz_sysc_signal_init_data { + const char *name; + u32 offset; + u32 mask; + u32 refcnt_incr_val; +}; + +/** + * struct rz_sysc_signal - RZ SYSC signals + * @init_data: signals initialization data + * @refcnt: reference counter + */ +struct rz_sysc_signal { + struct rz_sysc_signal_init_data init_data; + refcount_t refcnt; +}; + /** * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initializat= ion data * @family: RZ SoC family @@ -35,13 +60,23 @@ struct rz_sysc_soc_id_init_data { /** * struct rz_sysc_init_data - RZ SYSC initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data + * @signals_init_data: RZ SYSC signals initialization data * @regmap_cfg: SoC-specific regmap config + * @num_signals: number of SYSC signals */ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; + const struct rz_sysc_signal_init_data *signals_init_data; const struct regmap_config *regmap_cfg; + u32 max_register_offset; + u32 num_signals; }; =20 +extern int rz_sysc_reg_read(void *context, unsigned int off, unsigned int = *val); +extern int rz_sysc_reg_write(void *context, unsigned int off, unsigned int= val); +extern int rz_sysc_reg_update_bits(void *context, unsigned int off, + unsigned int mask, unsigned int val); + extern const struct rz_sysc_init_data rzg3e_sys_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; extern const struct rz_sysc_init_data rzv2h_sys_init_data; diff --git a/include/linux/soc/renesas/rz-sysc.h b/include/linux/soc/renesa= s/rz-sysc.h new file mode 100644 index 000000000000..e2864ebeadf7 --- /dev/null +++ b/include/linux/soc/renesas/rz-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SOC_RENESAS_RZ_SYSC_H__ +#define __LINUX_SOC_RENESAS_RZ_SYSC_H__ + +#include +#include +#include + +/** + * struct rz_sysc_signal_map - RZ SYSC signal mapping (to be used by consu= mmers) + * @regmap: SYSC regmap + * @offset: offset into the SYSC address space for accessing the signal + * @mask: mask into the register at offset for accessing the signal + */ +struct rz_sysc_signal_map { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + +#ifdef CONFIG_SYSC_RZ +extern struct rz_sysc_signal_map *rz_sysc_get_signal_map(struct device *de= v); +#else +static inline struct rz_sysc_signal_map *rz_sysc_get_signal_map(struct dev= ice *dev) +{ + return ERR_PTR(-EOPNOTSUPP); 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.09.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:09:58 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 03/12] soc: renesas: r9a08g045-sysc: Add USB PWRRDY signal Date: Wed, 21 May 2025 17:09:34 +0300 Message-ID: <20250521140943.3830195-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The USB PWRRDY is a SYSC signal that need to be controlled, in case of RZ/G3S SoC, before/after the power to the USB PHYs is turned on/off. Add the USB PWRRDY signal. Signed-off-by: Claudiu Beznea --- Changes in v3: - none, this patch is new and obtained from [1] [1] https://lore.kernel.org/all/20241126092050.1825607-3-claudiu.beznea.uj@= bp.renesas.com/ drivers/soc/renesas/r9a08g045-sysc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index d2c9e3b77f41..7e6b5edf9666 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -5,11 +5,21 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ =20 +#include #include #include =20 #include "rz-sysc.h" =20 +static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[= ] __initconst =3D { + { + .name =3D "usb-pwrrdy", + .offset =3D 0xd70, + .mask =3D BIT(0), + .refcnt_incr_val =3D 0 + } +}; + static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data _= _initconst =3D { .family =3D "RZ/G3S", .id =3D 0x85e0447, @@ -33,4 +43,6 @@ static const struct regmap_config rzg3s_sysc_regmap __ini= tconst =3D { const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, .regmap_cfg =3D &rzg3s_sysc_regmap, + .signals_init_data =3D rzg3s_sysc_signals_init_data, + .num_signals =3D ARRAY_SIZE(rzg3s_sysc_signals_init_data), }; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea , Conor Dooley Subject: [PATCH v3 04/12] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Date: Wed, 21 May 2025 17:09:35 +0300 Message-ID: <20250521140943.3830195-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S p= hy bindings") Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags - rebased on top of latest version of renesas,usb2-phy.yaml; Conor, Geert: I kept your tags; please let me know if you consider it otherwise Changes in v2: - none; this patch is new Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/= Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 2822dce8d9f4..12f8d5d8af55 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -108,6 +108,7 @@ allOf: contains: enum: - renesas,usb2-phy-r9a09g057 + - renesas,usb2-phy-r9a08g045 - renesas,rzg2l-usb2-phy then: properties: --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0449A26772A for ; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 05/12] dt-bindings: phy: renesas,usb2-phy: Add renesas,sysc-signals Date: Wed, 21 May 2025 17:09:36 +0300 Message-ID: <20250521140943.3830195-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system controller that need to be de-asserted/asserted when power is turned on/off. This signal, called PWRRDY, is controlled through a specific register in the system controller memory space. Add the renesas,sysc-signals DT property to describe the relation b/w the system controller and the USB PHY on the Renesas RZ/G3S. This property provides a phandle to the system controller, along with the offset within the system controller memory space that manages the signal and a bitmask that indicates the specific bits required to control the signal. Signed-off-by: Claudiu Beznea --- Changes in v3: - replace renesas,sysc-signal with renesas,sysc-signals for case where more than 1 signal should be described with this property - Geert: due to this I dropped you tag Changes in v2: - none; this patch is new .../bindings/phy/renesas,usb2-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/= Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 12f8d5d8af55..e1e773cba847 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -86,6 +86,16 @@ properties: =20 dr_mode: true =20 + renesas,sysc-signals: + description: System controller phandle, specifying the register + offset and bitmask associated with a specific system controller sign= al + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: system controller phandle + - description: register offset associated with a signal + - description: register bitmask associated with a signal + if: properties: compatible: @@ -117,6 +127,18 @@ allOf: required: - resets =20 + - if: + properties: + compatible: + contains: + const: renesas,usb2-phy-r9a08g045 + then: + required: + - renesas,sysc-signals + else: + properties: + renesas,sysc-signals: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA6621991B8 for ; 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Wed, 21 May 2025 07:10:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Christophe JAILLET , Claudiu Beznea Subject: [PATCH v3 06/12] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Date: Wed, 21 May 2025 17:09:37 +0300 Message-ID: <20250521140943.3830195-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christophe JAILLET If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initiali= ze the bus") Signed-off-by: Christophe JAILLET Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven [claudiu.beznea: removed "struct reset_control *rstc =3D data;" from rcar_gen3_reset_assert()] Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - none; this patch is new; re-spinned the Christophe's work at https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR= 01MB11332.jpnprd01.prod.outlook.com/ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas= /phy-rcar-gen3-usb2.c index 47beb94cd424..d61c171d454f 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -699,6 +699,11 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct d= evice_node *np) return candidate; } =20 +static void rcar_gen3_reset_assert(void *data) +{ + reset_control_assert(data); +} + static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) { struct device *dev =3D channel->dev; @@ -717,6 +722,11 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen= 3_chan *channel) if (ret) goto rpm_put; =20 + ret =3D devm_add_action_or_reset(dev, rcar_gen3_reset_assert, + channel->rstc); + if (ret) + goto rpm_put; + val =3D readl(channel->base + USB2_AHB_BUS_CTR); val &=3D ~USB2_AHB_BUS_CTR_MBL_MASK; val |=3D USB2_AHB_BUS_CTR_MBL_INCR4; @@ -860,7 +870,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_d= evice *pdev) if (channel->is_otg_channel) device_remove_file(&pdev->dev, &dev_attr_role); =20 - reset_control_assert(channel->rstc); pm_runtime_disable(&pdev->dev); }; =20 --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC6BB27B507 for ; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 07/12] phy: renesas: rcar-gen3-usb2: Add support for USB PWRRDY signal Date: Wed, 21 May 2025 17:09:38 +0300 Message-ID: <20250521140943.3830195-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. On power-on the USB PWRRDY signal need to be de-asserted before enabling clock and switching the module to normal state (though MSTOP support). The power-on configuration sequence must be: 1/ PWRRDY=3D0 2/ CLK_ON=3D1 3/ MSTOP=3D0 On power-off the configuration sequence should be: 1/ MSTOP=3D1 2/ CLK_ON=3D0 3/ PWRRDY=3D1 The CLK_ON and MSTOP functionalities are controlled by clock drivers. After long discussions with the internal HW team, it has been confirmed that the HW connection b/w USB PHY block, the USB channels, the system controller, clock, MSTOP, PWRRDY signal is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2= =94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK0_ON =E2=94=82 USB CH0 =E2= =94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90= =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK2_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82host control= ler registers =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82fu= nction controller registers=E2=94=82 =E2=94=82 =E2=94=82 PHY0 =E2=94=82=E2=97=84=E2=94=80=E2= =94=80=E2=94=A4=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 USB PHY =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTO= P{6, 5}_ON =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82USHPHY control=E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82 registers =E2=94=82 =E2=94=82 PHY1 =E2=94=82 =E2= =94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =98 =E2=94=82 =E2=94=82=E2=97=84=E2=94=80=E2=94=80=E2=94=A4 USB = CH1 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=8C=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK1_ON =E2=94=94=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=82 host controller registers = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=94= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MS= TOP.MSTOP7_ON =E2=94=82PWRRDY =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_CLK_ON_USB.CLK3_ON =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82SYSC=E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 where: - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X of different USB blocks, X in {0, 1, 2, 3} - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the MSTOP of different USB blocks, X in {4, 5, 6, 7} - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used by the USB CH0, USB CH1 - SYSC is the system controller block controlling the PWRRDY signal - USB CHx are individual USB block with host and function capabilities (USB CH0 have both host and function capabilities, USB CH1 has only host capabilities) The USBPHY control registers are controlled though the reset-rzg2l-usbphy-ctrl driver (drivers/reset/reset-rzg2l-usbphy-ctrl.c fil= e). The USB PHY ports are controlled by phy_rcar_gen3_usb2 driver. The USB PHY ports requests resets from the reset-rzg2l-usbphy-ctrl driver. The connection b/w the system controller and the USB PHY drivers is implemented through the renesas,sysc-signals device tree property. This property specifies the register offset and the bitmask required to control the signal. The system controller exports the syscon regmap, and the read/write access to the memory area of the PWRRDY signal is reference-counted, as the same system controller signal is provided to both phy_rcar_gen3_usb2 and reset-rzg2l-usbphy-ctrl drivers. This approach was chosen to avoid any violation of the configuration sequence b/w PWRRDY, CLK_ON and MSTOP bits specified above. Add support for PWRRDY in phy_rcar_gen3_usb2 driver. Signed-off-by: Claudiu Beznea --- Changes in v3: - uses struct rz_sysc_signal_map along with rz_sysc_get_signal_map() to handle the USB PWRRDY signal - dropped the check of pwrrdy in rcar_gen3_phy_usb2_set_pwrrdy() - improved the patch description Changes in v2: - none; this patch is new drivers/phy/renesas/phy-rcar-gen3-usb2.c | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas= /phy-rcar-gen3-usb2.c index d61c171d454f..ca50db84a90b 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -19,8 +19,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -126,6 +128,7 @@ struct rcar_gen3_chan { struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; struct reset_control *rstc; + struct rz_sysc_signal_map *pwrrdy; struct work_struct work; spinlock_t lock; /* protects access to hardware and driver data structure= . */ enum usb_dr_mode dr_mode; @@ -142,6 +145,7 @@ struct rcar_gen3_phy_drv_data { bool no_adp_ctrl; bool init_bus; bool utmi_ctrl; + bool pwrrdy; }; =20 /* @@ -608,6 +612,7 @@ static const struct rcar_gen3_phy_drv_data rz_g3s_phy_u= sb2_data =3D { .phy_usb2_ops =3D &rcar_gen3_phy_usb2_ops, .no_adp_ctrl =3D true, .init_bus =3D true, + .pwrrdy =3D true, }; =20 static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data =3D { @@ -738,6 +743,35 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen= 3_chan *channel) return ret; } =20 +static void rcar_gen3_phy_usb2_set_pwrrdy(struct rcar_gen3_chan *channel, = bool power_on) +{ + struct rz_sysc_signal_map *pwrrdy =3D channel->pwrrdy; + + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, !power_o= n); +} + +static void rcar_gen3_phy_usb2_pwrrdy_off(void *data) +{ + rcar_gen3_phy_usb2_set_pwrrdy(data, false); +} + +static int rcar_gen3_phy_usb2_init_pwrrdy(struct rcar_gen3_chan *channel) +{ + struct device *dev =3D channel->dev; + struct rz_sysc_signal_map *pwrrdy; + + pwrrdy =3D rz_sysc_get_signal_map(dev); + if (IS_ERR(pwrrdy)) + return PTR_ERR(pwrrdy); + + channel->pwrrdy =3D pwrrdy; + + /* Power it ON. */ + rcar_gen3_phy_usb2_set_pwrrdy(channel, true); + + return devm_add_action_or_reset(dev, rcar_gen3_phy_usb2_pwrrdy_off, chann= el); +} + static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { const struct rcar_gen3_phy_drv_data *phy_data; @@ -792,6 +826,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_de= vice *pdev) platform_set_drvdata(pdev, channel); channel->dev =3D dev; =20 + if (phy_data->pwrrdy) { + ret =3D rcar_gen3_phy_usb2_init_pwrrdy(channel); + if (ret) + goto error; + } + if (phy_data->init_bus) { ret =3D rcar_gen3_phy_usb2_init_bus(channel); if (ret) --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F1A418D643 for ; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 08/12] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY signal Date: Wed, 21 May 2025 17:09:39 +0300 Message-ID: <20250521140943.3830195-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. On power-on the USB PWRRDY signal need to be de-asserted before enabling clock and switching the module to normal state (though MSTOP support). The power-on configuration sequence must be: 1/ PWRRDY=3D0 2/ CLK_ON=3D1 3/ MSTOP=3D0 On power-off the configuration sequence should be: 1/ MSTOP=3D1 2/ CLK_ON=3D0 3/ PWRRDY=3D1 The CLK_ON and MSTOP functionalities are controlled by clock drivers. After long discussions with the internal HW team, it has been confirmed that the HW connection b/w USB PHY block, the USB channels, the system controller, clock, MSTOP, PWRRDY signal is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2= =94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK0_ON =E2=94=82 USB CH0 =E2= =94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90= =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK2_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82host control= ler registers =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82fu= nction controller registers=E2=94=82 =E2=94=82 =E2=94=82 PHY0 =E2=94=82=E2=97=84=E2=94=80=E2= =94=80=E2=94=A4=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 USB PHY =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTO= P{6, 5}_ON =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82USHPHY control=E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82 registers =E2=94=82 =E2=94=82 PHY1 =E2=94=82 =E2= =94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =98 =E2=94=82 =E2=94=82=E2=97=84=E2=94=80=E2=94=80=E2=94=A4 USB = CH1 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=8C=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK1_ON =E2=94=94=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=82 host controller registers = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=94= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MS= TOP.MSTOP7_ON =E2=94=82PWRRDY =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_CLK_ON_USB.CLK3_ON =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82SYSC=E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 where: - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X of different USB blocks, X in {0, 1, 2, 3} - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the MSTOP of different USB blocks, X in {4, 5, 6, 7} - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used by the USB CH0, USB CH1 - SYSC is the system controller block controlling the PWRRDY signal - USB CHx are individual USB block with host and function capabilities (USB CH0 have both host and function capabilities, USB CH1 has only host capabilities) The USBPHY control registers are controlled though the reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The USB PHY ports requests resets from the reset-rzg2l-usbphy-ctrl driver. The connection b/w the system controller and the USB PHY drivers is implemented through the renesas,sysc-signals device tree property. This property specifies the register offset and the bitmask required to control the signal. The system controller exports the syscon regmap, and the read/write access to the memory area of the PWRRDY signal is reference-counted, as the same system controller signal is provided to the PHY driver and the reset-rzg2l-usbphy-ctrl. This approach was chosen to avoid any violation of the configuration sequence b/w PWRRDY, CLK_ON and MSTOP bits specified above. Add support for PWRRDY in reset-rzg2l-usbphy-ctrl driver. Signed-off-by: Claudiu Beznea --- Changes in v3: - none; this patch is new drivers/reset/reset-rzg2l-usbphy-ctrl.c | 42 +++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 8a7f167e405e..016aae883b2e 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #define RESET 0x000 #define VBENCTL 0x03c @@ -35,6 +36,7 @@ struct rzg2l_usbphy_ctrl_priv { struct reset_control *rstc; void __iomem *base; struct platform_device *vdev; + struct rz_sysc_signal_map *pwrrdy; =20 spinlock_t lock; }; @@ -91,6 +93,8 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controll= er_dev *rcdev, return !!(readl(priv->base + RESET) & port_mask); } =20 +#define RZG2L_USBPHY_CTRL_PWRRDY 1 + static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, { /* Sentinel */ } @@ -110,6 +114,40 @@ static const struct regmap_config rzg2l_usb_regconf = =3D { .max_register =3D 1, }; =20 +static void rzg2l_usbphy_ctrl_set_pwrrdy(struct rzg2l_usbphy_ctrl_priv *pr= iv, + bool power_on) +{ + struct rz_sysc_signal_map *pwrrdy =3D priv->pwrrdy; + + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, !power_o= n); +} + +static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) +{ + rzg2l_usbphy_ctrl_set_pwrrdy(data, false); +} + +static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev, + struct rzg2l_usbphy_ctrl_priv *priv) +{ + struct rz_sysc_signal_map *pwrrdy; + const int *data; + + data =3D device_get_match_data(dev); + if (data !=3D (int *)RZG2L_USBPHY_CTRL_PWRRDY) + return 0; + + pwrrdy =3D rz_sysc_get_signal_map(dev); + if (IS_ERR(pwrrdy)) + return PTR_ERR(pwrrdy); + + priv->pwrrdy =3D pwrrdy; + + rzg2l_usbphy_ctrl_set_pwrrdy(priv, true); + + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, priv); +} + static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -132,6 +170,10 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_dev= ice *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 09/12] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Date: Wed, 21 May 2025 17:09:40 +0300 Message-ID: <20250521140943.3830195-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas USB PHY hardware block receives an input signal from the system controller. This signal must be controlled during power-on, power-off, and system suspend/resume sequences as follows: - during power-on/resume, it must be de-asserted before enabling clocks and modules - during power-off/suspend, it must be asserted after disabling clocks and modules Add the renesas,sysc-signals device tree property, which allows the reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system controller signal at the appropriate time. Along with it add a new compatible for the RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v3: - none; this patch is new .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 38 ++++++++++++++++--- 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-c= trl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctr= l.yaml index b0b20af15313..75134330f797 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,15 @@ description: =20 properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl + + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S =20 reg: maxItems: 1 @@ -48,6 +51,16 @@ properties: $ref: /schemas/regulator/regulator.yaml# unevaluatedProperties: false =20 + renesas,sysc-signals: + description: System controller phandle, specifying the register + offset and bitmask associated with a specific system controller sign= al + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: system controller phandle + - description: register offset associated with a signal + - description: register bitmask associated with a signal + required: - compatible - reg @@ -57,6 +70,19 @@ required: - '#reset-cells' - regulator-vbus =20 +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-usbphy-ctrl + then: + required: + - renesas,sysc-signals + else: + properties: + renesas,sysc-signals: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DE29280309 for ; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 10/12] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Date: Wed, 21 May 2025 17:09:41 +0300 Message-ID: <20250521140943.3830195-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY signal from the system controller. Add support for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v3: - none; this patch is new drivers/reset/reset-rzg2l-usbphy-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 016aae883b2e..98d6323e9f56 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -97,6 +97,10 @@ static int rzg2l_usbphy_ctrl_status(struct reset_control= ler_dev *rcdev, =20 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, + { + .compatible =3D "renesas,r9a08g045-usbphy-ctrl", + .data =3D (void *)RZG2L_USBPHY_CTRL_PWRRDY + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AD5627F194 for ; Wed, 21 May 2025 14:10:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747836630; cv=none; b=prg0tRxTEUF+Gt0rfd6UsAO4TEVlFld+WQqkV8Nr/5/Q6cfW5ZFx2HKvvx6kqRjr+ECLORlef8D5SXhNTQ/znDdcCaLe1AxiRgoiKlPgAa4lkaOZTd58mcS477dbja/YFtDyo6FVTD6v33O5h54tAe/yG76/vXlxWw27hFaTKBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747836630; c=relaxed/simple; bh=BSsTy3tbn/xKQinuO+XIPNVVjzoHKqygxo857+Pk8I0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qNjqQ0hdu+v1w0Um8mhyjBk8fjt+bs/R/Ko3Y9KmBBaLO6hV2ByUBwKLj3dU7WPGutAQENFsS1STiW6+4Ncgs4Mv7TbcAnKtu535ajb3OwVhzL/3veWRTPy1qNDg/u+fhdFYNtWAJ6RxNi79tsg3FzpzMwZsYeJr1Gxry4P1pTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=fpzYXsVS; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="fpzYXsVS" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-601d66f8cafso5499533a12.3 for ; Wed, 21 May 2025 07:10:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1747836627; x=1748441427; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5R0SBkCSnZ1ZgHRkf3W4h5B5fht7vGGoztaC7tLlMq0=; b=fpzYXsVS7sHayaezRGajAwjlC+6HqUzSUEHYeb8GLNjU+AcriBHc4AbixY/i6L3Jbs gG4kyGgxEvRFV6Z1rkPpPKhxIc4Hq6U9gDD+WNB626EhAwg/NjnbKn+PV1Z1Qg/Asc9u jX1bqXkvC4TqDcrtD3acHfdfqcEjzW15kxsKlwwI3z4dTAsTpmCEYViOXnWN++qumGxS heSTXGNWL3b0Q3BZsLQUWSmJtofKvk4vBRl9zwvqeLvtRyut56s3A/1kcMKuYH7bTn48 PiX5j/imcOxqKlzlBgoGUHnRZD470tC+dK/RqT/DvteytH1YInR9loFVa82PIWQPLsHF eRVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747836627; x=1748441427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5R0SBkCSnZ1ZgHRkf3W4h5B5fht7vGGoztaC7tLlMq0=; b=GI7O7jdX9zFzMmmWY29YfvCkZwh5r/xxjQHl++QEczpwpT/KyEvXqMzfT8mHlkdCOU 47AzUOkOrs2YX8MuNf+PUXZms6NubLptUEpwiUpsjdnLOQAseYcC4TGhaG5LmNJqYnyr bOqau7ifHDqXEUPXzvf8PXKAYtwQTTuwv/5ima94dybly4YXFWRJBGqp0E9RQUgmr1NP 2ll2EWaSyFvSHDcNsEVE7JdXni/c/GoLW6eRonrZZM1jLk+D+KZyYHF22eCrR5gC/auh NdGDTKvgMYzRjtPQnN8EtWbTgW8tf/HI5w6RybE9A1/NqclsdHAB7GMdnkksgRoPuOPr n+kw== X-Forwarded-Encrypted: i=1; AJvYcCV9tgLrCiocQO7nPaVQpeLsArUA5+HuzXEyDLjuOQ+ggxQOclFavj8MUKZzkKj4mgO8T/M127PTAyEC+dM=@vger.kernel.org X-Gm-Message-State: AOJu0Yxmg4nqjkuXqACHc8dOcKRLTmUZe2moW4G9m9tEHgB/7YPxgfKk gI241NcUWmK7wAa8N+07viOqqlsu0edN+66bftljdJohrpk54x2riGcAp6YTFd9yaxs= X-Gm-Gg: ASbGncvNpf+bmqhqAAtfQ41wFEV3Rix71APPD84afMc1eHjEqGlJ1vQ6LcI2tlpZ//q aDAs/RIETCCAR9AWnxi7izgf0c4wHtrRWVIiR3D3iFHnZxSRr7QwE2jNzN+UqxkKwHAHtSqRmdc nAB4oiSraz+tzWPVOCAWrtGlFaL93rybFNWCtoHukvPwtLWWE3G7Kv2kERqM2XcK8SDij7t72Dr 5LswvKDXAk4tIOz6h017w7zXKa21gaDRbbgiU4IA0atG662d89m392NxzQhXO/xn1C1fR66zMCh P0Gqy1NmmIwoBRmUWifttwlCJvaTKpSZPst1HvwRIVecS0ak/a5QvJT2huU8ZJtFyN34Fpapqxz G7Uc+ X-Google-Smtp-Source: AGHT+IHIkR9ssJIhuCx1mmiAIGd6OoO/KN3o16DijCKheyN/jOueJQVldCbsG3V2xpWCs2Emi9rUQg== X-Received: by 2002:a17:907:96a1:b0:ad2:1cba:cf85 with SMTP id a640c23a62f3a-ad536dce1b0mr1741373266b.39.1747836626692; Wed, 21 May 2025 07:10:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 11/12] arm64: dts: renesas: r9a08g045: Add USB support Date: Wed, 21 May 2025 17:09:42 +0300 Message-ID: <20250521140943.3830195-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Signed-off-by: Claudiu Beznea --- Changes in v3: - changed the nodes order to keep similar nodes toghether Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise=20 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 120 +++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 0364f89776e6..e329c55c3fad 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -681,6 +681,126 @@ eth1: ethernet@11c40000 { status =3D "disabled"; }; =20 + phyrst: usbphy-ctrl@11e00000 { + compatible =3D "renesas,r9a08g045-usbphy-ctrl"; + reg =3D <0 0x11e00000 0 0x10000>; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets =3D <&cpg R9A08G045_USB_PRESETN>; + power-domains =3D <&cpg>; + #reset-cells =3D <1>; + renesas,sysc-signals =3D <&sysc 0xd70 0x1>; + status =3D "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name =3D "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e10000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ohci1: usb@11e30000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e30000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci0: usb@11e10100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e10100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 2>; + phy-names =3D "usb"; + companion =3D <&ohci0>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci1: usb@11e30100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e30100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 2>; + phy-names =3D "usb"; + companion =3D <&ohci1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e10200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + renesas,sysc-signals =3D <&sysc 0xd70 0x1>; + status =3D "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e30200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + renesas,sysc-signals =3D <&sysc 0xd70 0x1>; + status =3D "disabled"; + }; + + hsusb: usb@11e20000 { + compatible =3D "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg =3D <0 0x11e20000 0 0x10000>; + interrupts =3D , + , + , + ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait =3D <7>; + phys =3D <&usb2_phy0 3>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + gic: interrupt-controller@12400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; --=20 2.43.0 From nobody Sun Dec 14 19:29:51 2025 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 026E518BBB9 for ; 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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d271916sm914552866b.69.2025.05.21.07.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 May 2025 07:10:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, kees@kernel.org, gustavoars@kernel.org, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-hardening@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v3 12/12] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Wed, 21 May 2025 17:09:43 +0300 Message-ID: <20250521140943.3830195-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> References: <20250521140943.3830195-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable USB support (host, device, USB PHYs). Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - this was patch 15/16 in v1: - dropped sysc enablement as it is now done in SoC dtsi file arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 5e044a4d0234..5586dd43c4d5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -92,6 +92,20 @@ &audio_clk2 { clock-frequency =3D <12288000>; }; =20 +&ehci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&hsusb { + dr_mode =3D "otg"; + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -132,6 +146,15 @@ power-monitor@44 { }; }; =20 +&ohci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + &pinctrl { audio_clock_pins: audio-clock { pins =3D "AUDIO_CLK1", "AUDIO_CLK2"; @@ -207,6 +230,27 @@ ssi3_pins: ssi3 { , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + peri { + pinmux =3D , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux =3D ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux =3D , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status =3D "okay"; }; =20 &scif0 { @@ -242,3 +286,16 @@ &ssi3 { pinctrl-0 =3D <&ssi3_pins>, <&audio_clock_pins>; status =3D "okay"; }; + +&usb2_phy0 { + pinctrl-0 =3D <&usb0_pins>; + pinctrl-names =3D "default"; + vbus-supply =3D <&usb0_vbus_otg>; + status =3D "okay"; +}; + +&usb2_phy1 { + pinctrl-0 =3D <&usb1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.43.0