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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id EB31D3F70B3; Wed, 21 May 2025 03:04:53 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan Subject: [PATCH 1/4 v3] crypto: octeontx2: add timeout for load_fvc completion poll Date: Wed, 21 May 2025 15:34:44 +0530 Message-ID: <20250521100447.94421-2-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521100447.94421-1-bbhushan2@marvell.com> References: <20250521100447.94421-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA5OSBTYWx0ZWRfX7sNeaOAB8OIF kpCiU4jwNXJj3InZUTUYx78kq/nA9SKJEO/nZKY8mPThv8U2w3vrF96lxZJDEZerRhYwU+NxlJa /U5kF4RuXSR1pbY1CFV+LhXDK0IBF3tYgrFIXN+RQs75dDCmaabuUfe01l/1OOuAiUcZqVua/5U PQKAqyBBgqC7CXtNSzljLzevXu2cnaoNpUW+b046h5JZlmxkWhNt6GDu56YQMKo8mf9IqUbZHPl FHAotrayhtV2qQvJYCdzeltyaTlyQjZpcST19qusemuMuJ2QUzR+K0dSkMCzlVLe6Dhv31t2Kz/ to/Nz3tGNURV+Bo7nWwZA2xiZM6EBwMNnakdd69718Y506jX14FgiKLr+EmKOF5ZcGrknrj03Fg ZWZldVGhIOuvTPl6/H4HVeErNogrZVB1asiy1pK5E2axBzJhbWt4f+a+W5pywwQz4BrgNsPK X-Proofpoint-GUID: Ikz-tyihjJA9pvvJikOBIuEtjXCttmSC X-Authority-Analysis: v=2.4 cv=T6OMT+KQ c=1 sm=1 tr=0 ts=682da54a cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=dP9LQboaRqI6G61vZ2MA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: Ikz-tyihjJA9pvvJikOBIuEtjXCttmSC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_03,2025-05-20_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Adds timeout to exit from possible infinite loop, which polls on CPT instruction(load_fvc) completion. Signed-off-by: Srujana Challa Signed-off-by: Bharat Bhushan --- .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 78367849c3d5..9095dea2748d 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1494,6 +1494,7 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) dma_addr_t rptr_baddr; struct pci_dev *pdev; u32 len, compl_rlen; + int timeout =3D 10000; int ret, etype; void *rptr; =20 @@ -1554,16 +1555,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) etype); otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); + timeout =3D 10000; =20 while (lfs->ops->cpt_get_compcode(result) =3D=3D - OTX2_CPT_COMPLETION_CODE_INIT) + OTX2_CPT_COMPLETION_CODE_INIT) { cpu_relax(); + udelay(1); + timeout--; + if (!timeout) { + ret =3D -ENODEV; + cptpf->is_eng_caps_discovered =3D false; + dev_warn(&pdev->dev, "Timeout on CPT load_fvc completion poll\n"); + goto error_no_response; + } + } =20 cptpf->eng_caps[etype].u =3D be64_to_cpup(rptr); } - dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); cptpf->is_eng_caps_discovered =3D true; =20 +error_no_response: + dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); free_result: kfree(result); lf_cleanup: --=20 2.34.1 From nobody Mon Feb 9 06:11:45 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 106D725C814; Wed, 21 May 2025 10:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747821925; cv=none; b=rn/CZm6uFjqRFJPbq2UIHgZjkFFuSM3KWhqY450uF1SHrW/JlxTbaRJKGKZnraK9V4ew8fEDjDh1fWwKe+WUY7YO5fi1/1xnVNeRJu/qh3c6IQmI6TRrxUWfVaM9rQgMd0/vdTaUTdNK/lO9QNyq+8zsxcbGjQMghZkSpsk91yk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747821925; c=relaxed/simple; bh=w09QJS2CHpPPPBShQSbx0kEh1cU4AjomvsaLibzzqZI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BihaGUJ67W7rfazLoSmIT+IqmYplvxSf0IDXMI//pu2pMwbBCTuKgcI+uzvwu0NBNUDrVyHAYBq4/SPnQVEP5/i8yIMZty6/kAXbSIWnrCecUQqFC8nGOU53CC6VVUUAjG1YWZUCgVIcVChkzF3OisovpFNbOoT4srJeMFzyhCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=TUN2K96J; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="TUN2K96J" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54L9qwLG010201; Wed, 21 May 2025 03:05:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=r 7h4I8UCAWaJQNlnW6T1gZDYgXALjPeTnXR+aNDIrRc=; b=TUN2K96J+ODsiLf2s Ef2ivX/q3WnPXqonS2CQj541LAKrEVUE1tj878cYNYNFtDCSM19abIWtsJt/y0Vn FcZVHaQVdbCsuk868E7sG7EMp0RSKPRq5YkeaKgSz3EVYlRXrGivpUPr7a3eD9Cr IXHAkvCSIzNn5/8Q6j2N2QoUjeo5KLxv4KuqJ8nulViNWAubcCmfWAPq8GLnI9US FV8w6rxEUcx0q2K05fnF3gP9PalnQvBbxd/jV670u9A7EK48GdVhivHdtBeZnThP G2PQ3HdlCl0kSmqzyYUXD40uyrglprkKfYTVi0Kpui9cwPbfL51eQRWJiPIRqV8j BTMZA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 46rwfghpgm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 May 2025 03:05:01 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 21 May 2025 03:05:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 21 May 2025 03:05:01 -0700 Received: from bharat-OptiPlex-Tower-Plus-7020.. (unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id ADCA53F70B3; Wed, 21 May 2025 03:04:57 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan Subject: [PATCH 2/4 v3] crypto: octeontx2: Fix address alignment issue on ucode loading Date: Wed, 21 May 2025 15:34:45 +0530 Message-ID: <20250521100447.94421-3-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521100447.94421-1-bbhushan2@marvell.com> References: <20250521100447.94421-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA5OSBTYWx0ZWRfX1n4IXN0WpHVf FAuEe/JFFMji8Em2DPPiJjlwMkzeVZtSgcV2xSU5m+/nNZcIvG6Amk0ZJ/HPNAFE7X0gQazL7Rl 2jwAi3/rv6iUp/2Qyc9RkLZTxBUUN5eIHZzl8+57hYLB/cCVWRpZISOHWHLnafLwNCfAwU/6L4U 1bC+MbmMNkJiOZ/g7zyll/7UQwnbzyhr/ObSnEgcWxlcvfpFUFkeXcIBfsK6dWIeXe5JWypDS02 LiunQWbzNytjzRXb0EkZAnpWOAmSKsjmMHgQ+HzbSO/rOsHao1I3j90ZS5oPJdDBsI16NyzOSZU RLkVsVpbj5lhriwLOGAPZ08jc4bHkewh8LsPfVN3CXTglBT33fPcy508m6ipdjGzgxsgWXftZdx U5lMZXVkiruG0xN0VX1O+Nqj0bcPgAiHkzgrTuFAOrg+AmJ6RyRa82q9cJ8bmetQjHLXXqcG X-Proofpoint-GUID: ifjEwj9PkHVDTON98cmujFQvIIOt3cDj X-Authority-Analysis: v=2.4 cv=T6OMT+KQ c=1 sm=1 tr=0 ts=682da54d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=ub5NSpVJfYrinLkKqRIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: ifjEwj9PkHVDTON98cmujFQvIIOt3cDj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_03,2025-05-20_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size()" Completion address should be 32-Byte alignment when loading microcode. Signed-off-by: Bharat Bhushan --- v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional =20 .../marvell/octeontx2/otx2_cptpf_ucode.c | 35 +++++++++++-------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 9095dea2748d..56645b3eb717 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1491,12 +1491,13 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) union otx2_cpt_opcode opcode; union otx2_cpt_res_s *result; union otx2_cpt_inst_s inst; + dma_addr_t result_baddr; dma_addr_t rptr_baddr; struct pci_dev *pdev; - u32 len, compl_rlen; int timeout =3D 10000; + void *base, *rptr; int ret, etype; - void *rptr; + u32 len; =20 /* * We don't get capabilities if it was already done @@ -1519,22 +1520,28 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) if (ret) goto delete_grps; =20 - compl_rlen =3D ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN); - len =3D compl_rlen + LOADFVC_RLEN; + /* Allocate extra memory for "rptr" and "result" pointer alignment */ + len =3D LOADFVC_RLEN + ARCH_DMA_MINALIGN + + sizeof(union otx2_cpt_res_s) + OTX2_CPT_RES_ADDR_ALIGN; =20 - result =3D kzalloc(len, GFP_KERNEL); - if (!result) { + base =3D kzalloc(len, GFP_KERNEL); + if (!base) { ret =3D -ENOMEM; goto lf_cleanup; } - rptr_baddr =3D dma_map_single(&pdev->dev, (void *)result, len, - DMA_BIDIRECTIONAL); + + rptr =3D PTR_ALIGN(base, ARCH_DMA_MINALIGN); + rptr_baddr =3D dma_map_single(&pdev->dev, rptr, len, DMA_BIDIRECTIONAL); if (dma_mapping_error(&pdev->dev, rptr_baddr)) { dev_err(&pdev->dev, "DMA mapping failed\n"); ret =3D -EFAULT; - goto free_result; + goto free_rptr; } - rptr =3D (u8 *)result + compl_rlen; + + result =3D (union otx2_cpt_res_s *)PTR_ALIGN(rptr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); + result_baddr =3D ALIGN(rptr_baddr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); =20 /* Fill in the command */ opcode.s.major =3D LOADFVC_MAJOR_OP; @@ -1546,14 +1553,14 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) /* 64-bit swap for microcode data reads, not needed for addresses */ cpu_to_be64s(&iq_cmd.cmd.u); iq_cmd.dptr =3D 0; - iq_cmd.rptr =3D rptr_baddr + compl_rlen; + iq_cmd.rptr =3D rptr_baddr; iq_cmd.cptr.u =3D 0; =20 for (etype =3D 1; etype < OTX2_CPT_MAX_ENG_TYPES; etype++) { result->s.compcode =3D OTX2_CPT_COMPLETION_CODE_INIT; iq_cmd.cptr.s.grp =3D otx2_cpt_get_eng_grp(&cptpf->eng_grps, etype); - otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); + otx2_cpt_fill_inst(&inst, &iq_cmd, result_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); timeout =3D 10000; =20 @@ -1576,8 +1583,8 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) =20 error_no_response: dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); -free_result: - kfree(result); +free_rptr: + kfree(base); lf_cleanup: otx2_cptlf_shutdown(lfs); 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 6D8B83F70B4; Wed, 21 May 2025 03:05:01 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 3/4 v3] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Date: Wed, 21 May 2025 15:34:46 +0530 Message-ID: <20250521100447.94421-4-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521100447.94421-1-bbhushan2@marvell.com> References: <20250521100447.94421-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA5OSBTYWx0ZWRfX2eXljIGpTQU8 SBgkmQg583o5UTVqz1X2NdOEM3hWr2a5dSPSiJhLdTeAWdvFsggRx+Gdw5EToXm1FVkppqveoql 5WqlK58QCWPOUDC+9f0O50PlpkcoSz1fZ2tZLxVDm5yqqde4y7+wCa2EObE7ft3zyu2qQEwcaPJ W3HcC2NjPTf14TwnITthrVbSyqacVM7yfEp4KXCH3cyE3aV2RUfyoFspOFXj4Eg7I8CAXnY8GKK 6HAECy9eOHUzKfYPTmPD4VpGX4Eb+A186jMBlWE2PeDsDsESjmSb7I4pcdSxSUdoOyNFGBehPNH pG+IPMPynCfgwLd/KhuxmcObrF7J8Rc76gDz+JbOGQqdBn1hgexLuB5o3wSQo59INFqfrxIrmrv bfyRUzjFiyUv6n6pH7YflfPUVn2+q104sel0BjLBZh5BDv8TxbvZLGCCi8paeLq9i2e0ur7S X-Proofpoint-GUID: 6luMCNxS9Ui_FW_QAdhP1pK5D5wLWkOY X-Authority-Analysis: v=2.4 cv=T6OMT+KQ c=1 sm=1 tr=0 ts=682da551 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=5ucEjCxuoSZ0TpCX4UYA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: 6luMCNxS9Ui_FW_QAdhP1pK5D5wLWkOY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_03,2025-05-20_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional =20 v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 63 ++++++++++++++----- 1 file changed, 48 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..204a31755710 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -34,6 +34,9 @@ #define SG_COMP_2 2 #define SG_COMP_1 1 =20 +#define OTX2_CPT_DPTR_RPTR_ALIGN 8 +#define OTX2_CPT_RES_ADDR_ALIGN 32 + union otx2_cpt_opcode { u16 flags; struct { @@ -417,10 +420,9 @@ static inline struct otx2_cpt_inst_info * otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - int align =3D OTX2_CPT_DMA_MINALIGN; struct otx2_cpt_inst_info *info; - u32 dlen, align_dlen, info_len; - u16 g_sz_bytes, s_sz_bytes; + u32 dlen, info_len; + u16 g_len, s_len; u32 total_mem_len; =20 if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || @@ -429,22 +431,51 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2= _cpt_req_info *req, return NULL; } =20 - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ =20 - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; - align_dlen =3D ALIGN(dlen, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D align_dlen + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + s_len =3D ((req->out_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + + dlen =3D g_len + s_len + SG_LIST_HDR_SIZE; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, ARCH_DMA_MINALIGN) + dlen; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (OTX2_CPT_RES_ADDR_ALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) return NULL; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); + info->out_buffer =3D info->in_buffer + SG_LIST_HDR_SIZE + g_len; =20 ((u16 *)info->in_buffer)[0] =3D req->out_cnt; ((u16 *)info->in_buffer)[1] =3D req->in_cnt; @@ -460,7 +491,7 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_c= pt_req_info *req, } =20 if (setup_sgio_components(pdev, req->out, req->out_cnt, - &info->in_buffer[8 + g_sz_bytes])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -476,8 +507,10 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_= cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + align_dlen; - info->comp_baddr =3D info->dptr_baddr + align_dlen; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + dlen), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + dlen), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1 From nobody Mon Feb 9 06:11:45 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E84B25B1EA; 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 75C763F70B3; Wed, 21 May 2025 03:05:05 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 4/4 v3] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Wed, 21 May 2025 15:34:47 +0530 Message-ID: <20250521100447.94421-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250521100447.94421-1-bbhushan2@marvell.com> References: <20250521100447.94421-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: T-ZA3YICQCQWRdu41o4EuZmPu5SxJows X-Proofpoint-GUID: T-ZA3YICQCQWRdu41o4EuZmPu5SxJows X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA5OSBTYWx0ZWRfX7OhwUDQvbuyg NrVfVVSm4k7LJqG300VL+m/XkMUN8nLkK7jvleRr0nQp10SoMsPqsLBu/kIlxAZ2YBwGiiTDP7h fFtIqacdY51m+pxGE2FS2Kx+pLB3AJo2EBIZsabHnVCeMWSfPKx2BvWXxav5AbXfocDrMWpL/SS 0HHbg6N3itSdgOKh8RbKutnOheoGUicSIsAqgc8RmI75rtiPsWEACFlkuseeAhKMifPwbOOeNa1 HsI6oFn4blWLFd3H234NE6ULea5k8aD+OMtJyXagf13lwSD7mD5K6pk+zn7aw4Alu8lJa7y2Neu 7zNAEYQOB7MCTKuyUCYrbQpQisLtgjQoR2wNnpspCjG5qHLplpe74Eb3yyv+1qh/N67yr8+eFhb u5gMOCPGddD6XxMr8370KyFioz50XeRfaswjZJocjQM8tIxv7k7+76FLjtkwQEXa0lv2g2gI X-Authority-Analysis: v=2.4 cv=U72SDfru c=1 sm=1 tr=0 ts=682da555 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_03,2025-05-20_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: #v6.8+ --- v2->v3: - Align DMA memory to ARCH_DMA_MINALIGN as that is mapped as bidirectional =20 v1->v2: - Fixed memory padding size calculation as per review comment .../marvell/octeontx2/otx2_cpt_reqmgr.h | 58 ++++++++++++++----- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index 204a31755710..8e95036e91d9 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,47 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen =3D 0, g_len, sg_len, info_len; - int align =3D OTX2_CPT_DMA_MINALIGN; + u32 dlen =3D 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; =20 - g_sz_bytes =3D ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ + + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len =3D ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len =3D g_len + s_len; =20 - g_len =3D ALIGN(g_sz_bytes, align); - sg_len =3D ALIGN(g_len + s_sz_bytes, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s); + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, ARCH_DMA_MINALIGN) + sg_len; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (OTX2_CPT_RES_ADDR_ALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +400,8 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, dlen +=3D req->in[i].size; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); + info->out_buffer =3D info->in_buffer + g_len; info->gthr_sz =3D req->in_cnt; info->sctr_sz =3D req->out_cnt; =20 @@ -387,7 +413,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, } =20 if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +430,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct ot= x2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + sg_len; - info->comp_baddr =3D info->dptr_baddr + sg_len; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1