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Tue, 20 May 2025 23:08:44 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 20 May 2025 23:08:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 20 May 2025 23:08:44 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 513B23F7077; Tue, 20 May 2025 23:08:40 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries Date: Wed, 21 May 2025 11:38:33 +0530 Message-ID: <20250521060834.19780-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250521060834.19780-1-gakula@marvell.com> References: <20250521060834.19780-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CG6dLKocc-atiIzC22CoTKe8DpYDQjE7 X-Proofpoint-GUID: CG6dLKocc-atiIzC22CoTKe8DpYDQjE7 X-Authority-Analysis: v=2.4 cv=TcyWtQQh c=1 sm=1 tr=0 ts=682d6dec cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=mpddl2msnD5X7IA2-cwA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA1OCBTYWx0ZWRfX62YLF9eQqu3U /kk0+ZAyecsgu+2qKX2iNTF0+LLgJ3wf77PDl7KNePzvOc61tZTuEyt4VV4Mabewq3Ux6211dnK DF0OO1h1jk6gnTB3QTxT8hIWSR2a9g2poec19cNM2002AdSFN9IZzCPBnUgyuSYXf8WcjoMccwC wUk21Ru1obFK9BSNqzBd9uRu4MStFMf3UvLMV4jAKCjSUcQJ9hR+8f5aaBG7rSYGkE8ZBvT5A6P 6xoVajL8rvW+r8zd7RE6lH7yr1btL39nqEUjtqzjZa8FTfGfXyDFDWPIYoROYnsh47SNFHVJlaV 1N072M7meQd84FGegrYlFrXWH5xO5fnEGU3XnMO9YOQYRWFraLADYKT2N44EX3XlOUKXExRJCZS m/ZCIxzhMup+KpOqI2Ju4U/cjGFqmpxlhprVZKVM9tkc2Zf8x4CniF4a8m5yWUXhdRuMPIe2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_01,2025-05-20_03,2025-03-28_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subbaraya Sundeep This patch enables the LMT line for a PF/VF by setting the LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure. Additionally, it simplifies the logic for calculating the LMTST table index by consistently using the maximum number of hw supported VFs (i.e., 256). Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table"). Signed-off-by: Subbaraya Sundeep Signed-off-by: Geetha sowjanya Reviewed-by: Michal Swiatkowski --- .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/driver= s/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c index 7fa98aeb3663..3838c04b78c2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c @@ -15,13 +15,17 @@ #define LMT_TBL_OP_WRITE 1 #define LMT_MAP_TABLE_SIZE (128 * 1024) #define LMT_MAPTBL_ENTRY_SIZE 16 +#define LMT_MAX_VFS 256 + +#define LMT_MAP_ENTRY_ENA BIT_ULL(20) +#define LMT_MAP_ENTRY_LINES GENMASK_ULL(18, 16) =20 /* Function to perform operations (read/write) on lmtst map table */ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val, int lmt_tbl_op) { void __iomem *lmt_map_base; - u64 tbl_base; + u64 tbl_base, cfg; =20 tbl_base =3D rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); =20 @@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 inde= x, u64 *val, *val =3D readq(lmt_map_base + index); } else { writeq((*val), (lmt_map_base + index)); + + cfg =3D FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1); + /* 2048 LMTLINES */ + cfg |=3D FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6); + + writeq(cfg, (lmt_map_base + (index + 8))); + /* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S * changes effective. Write 1 for flush and read is being used as a * barrier and sets up a data dependency. Write to 0 after a write @@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index= , u64 *val, #define LMT_MAP_TBL_W1_OFF 8 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc) { - return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) + + return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) + (pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE; } =20 --=20 2.25.1 From nobody Sun Feb 8 07:06:10 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F4B192B75; Wed, 21 May 2025 06:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747807740; cv=none; b=n/45wIoG+ty0eIhbzP6+swEsDHgf7DEhl/5o6MnWP9VdT5fdQ1RrVByu7DeTEMculc5ncHalIzwH9bv6rUojfCllfWMQGKc5qqZkcGVlLtXn1b5lkbYT2f/RHiwWJ3h9tJvQe1eyd5d4xMGATzbeSMtZwqVxkmW6kmITswwUHww= ARC-Message-Signature: i=1; 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Tue, 20 May 2025 23:08:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 20 May 2025 23:08:48 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 83A983F7077; Tue, 20 May 2025 23:08:44 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG Date: Wed, 21 May 2025 11:38:34 +0530 Message-ID: <20250521060834.19780-3-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250521060834.19780-1-gakula@marvell.com> References: <20250521060834.19780-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDA1OCBTYWx0ZWRfX5iDMfeAyeXyf tz0hiEY4sOg32mg6W8Y6skRmQv/l5GOxVBc08gZrMnmoX4+M/Hm2eUYZSOZil7XVzHUKyB5IQmP 2jJo018r1ReRm0zoIjyJqYqYqWBdYyVE7qMujuZ1fKWeSfCXV7WAkIDLfIDuSObWACGMmA5ABwQ ImO+o0S+5rTtLuBNJyMnbBK57T8QlfqhZUkDaeM7xZtYuxqEXaoX2D+KFZvzkaoUqUJZ6kpwoI6 JRc+FChSB3jnu48SVHsIF+Hkec2m+BUJz1sjYk4TCub1L25VHiGkBcnuFdqUiFZ/R/w/RY4fIeU IUtELUGaRvIchs2IYkxKkc1ldoCRdIIAb77eGT23hwNTZC/jXONVhHZHVfh9eWexQWP2qKZxICC JlJVtybCX5Gyt/tOyts73grNY67gw4BXvXYThaeoFl5XFklPswmULfD5X8j3D4NT8d4F80aa X-Proofpoint-GUID: NJbyK6bVPgwO4vYG_43HENxYFL2kEN27 X-Authority-Analysis: v=2.4 cv=T6OMT+KQ c=1 sm=1 tr=0 ts=682d6df1 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=pBlSUKV1qd5FT76UzXYA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: NJbyK6bVPgwO4vYG_43HENxYFL2kEN27 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_01,2025-05-20_03,2025-03-28_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current implementation maps the APR table using a fixed size, which can lead to incorrect mapping when the number of PFs and VFs varies. This patch corrects the mapping by calculating the APR table size dynamically based on the values configured in the APR_LMT_CFG register, ensuring accurate representation of APR entries in debugfs. Fixes: 0daa55d033b0 ("octeontx2-af: cn10k: debugfs for dumping LMTST map ta= ble"). Signed-off-by: Geetha sowjanya --- drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 9 ++++++--- .../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c | 11 ++++++++--- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/driver= s/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c index 3838c04b78c2..4a3370a40dd8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c @@ -13,7 +13,6 @@ /* RVU LMTST */ #define LMT_TBL_OP_READ 0 #define LMT_TBL_OP_WRITE 1 -#define LMT_MAP_TABLE_SIZE (128 * 1024) #define LMT_MAPTBL_ENTRY_SIZE 16 #define LMT_MAX_VFS 256 =20 @@ -26,10 +25,14 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 ind= ex, u64 *val, { void __iomem *lmt_map_base; u64 tbl_base, cfg; + int pfs, vfs; =20 tbl_base =3D rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); + cfg =3D rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); + vfs =3D 1 << (cfg & 0xF); + pfs =3D 1 << ((cfg >> 4) & 0x7); =20 - lmt_map_base =3D ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE); + lmt_map_base =3D ioremap_wc(tbl_base, pfs * vfs * LMT_MAPTBL_ENTRY_SIZE); if (!lmt_map_base) { dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); return -ENOMEM; @@ -80,7 +83,7 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc, =20 mutex_lock(&rvu->rsrc_lock); rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova); - pf =3D rvu_get_pf(pcifunc) & 0x1F; + pf =3D rvu_get_pf(pcifunc) & RVU_PFVF_PF_MASK; val =3D BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 | ((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF); rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index a1f9ec03c2ce..c827da626471 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -553,6 +553,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct f= ile *filp, u64 lmt_addr, val, tbl_base; int pf, vf, num_vfs, hw_vfs; void __iomem *lmt_map_base; + int apr_pfs, apr_vfs; int buf_size =3D 10240; size_t off =3D 0; int index =3D 0; @@ -568,8 +569,12 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct = file *filp, return -ENOMEM; =20 tbl_base =3D rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); + val =3D rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); + apr_vfs =3D 1 << (val & 0xF); + apr_pfs =3D 1 << ((val >> 4) & 0x7); =20 - lmt_map_base =3D ioremap_wc(tbl_base, 128 * 1024); + lmt_map_base =3D ioremap_wc(tbl_base, apr_pfs * apr_vfs * + LMT_MAPTBL_ENTRY_SIZE); if (!lmt_map_base) { dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); kfree(buf); @@ -591,7 +596,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct f= ile *filp, off +=3D scnprintf(&buf[off], buf_size - 1 - off, "PF%d \t\t\t", pf); =20 - index =3D pf * rvu->hw->total_vfs * LMT_MAPTBL_ENTRY_SIZE; + index =3D pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE; off +=3D scnprintf(&buf[off], buf_size - 1 - off, " 0x%llx\t\t", (tbl_base + index)); lmt_addr =3D readq(lmt_map_base + index); @@ -604,7 +609,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct f= ile *filp, /* Reading num of VFs per PF */ rvu_get_pf_numvfs(rvu, pf, &num_vfs, &hw_vfs); for (vf =3D 0; vf < num_vfs; vf++) { - index =3D (pf * rvu->hw->total_vfs * 16) + + index =3D (pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE) + ((vf + 1) * LMT_MAPTBL_ENTRY_SIZE); off +=3D scnprintf(&buf[off], buf_size - 1 - off, "PF%d:VF%d \t\t", pf, vf); --=20 2.25.1