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Wed, 21 May 2025 14:40:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9B66A4004D; Wed, 21 May 2025 14:39:43 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id DE06BCAA53E; Wed, 21 May 2025 14:38:53 +0200 (CEST) Received: from localhost (10.252.1.130) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 21 May 2025 14:38:53 +0200 From: Gabriel Fernandez Date: Wed, 21 May 2025 14:38:51 +0200 Subject: [PATCH v3 3/3] dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250521-upstream_rcc_mp21-v3-3-cac9d8f63d20@foss.st.com> References: <20250521-upstream_rcc_mp21-v3-0-cac9d8f63d20@foss.st.com> In-Reply-To: <20250521-upstream_rcc_mp21-v3-0-cac9d8f63d20@foss.st.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel CC: , , , , , Gabriel Fernandez X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_04,2025-05-20_03,2025-03-28_01 - drop minItems from access-controllers - remove rcc label from example - fixes typos - remove double '::' from 'See also::' Signed-off-by: Gabriel Fernandez Acked-by: Conor Dooley --- .../devicetree/bindings/clock/st,stm32mp25-rcc.yaml | 13 ++++++---= ---- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml = b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 88e52f10d1ecc68e818cd7d8cb1ca39dceb7a494..1e3b5d218bb01acb247d27bc690= 2be821cabd98c 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -11,9 +11,9 @@ maintainers: =20 description: | The RCC hardware block is both a reset and a clock controller. - RCC makes also power management (resume/supend). + RCC makes also power management (resume/suspend). =20 - See also:: + See also: include/dt-bindings/clock/st,stm32mp25-rcc.h include/dt-bindings/reset/st,stm32mp25-rcc.h =20 @@ -38,7 +38,7 @@ properties: - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or= ~ 16 MHz) - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz) - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz) - - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be ga= ted) + - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be g= ated) - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock @@ -108,15 +108,14 @@ properties: - description: CK_SCMI_ICN_APB2 Peripheral bridge 2 - description: CK_SCMI_ICN_APB3 Peripheral bridge 3 - description: CK_SCMI_ICN_APB4 Peripheral bridge 4 - - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub + - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug - description: CK_SCMI_TIMG1 Peripheral bridge for timer1 - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 - description: CK_SCMI_PLL3 PLL3 clock - description: clk_dsi_txbyte DSI byte clock =20 access-controllers: - minItems: 1 - maxItems: 2 + maxItems: 1 =20 required: - compatible @@ -131,7 +130,7 @@ examples: - | #include =20 - rcc: clock-controller@44200000 { + clock-controller@44200000 { compatible =3D "st,stm32mp25-rcc"; reg =3D <0x44200000 0x10000>; #clock-cells =3D <1>; --=20 2.25.1