From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BD1B1D8E07; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; cv=none; b=B9G5yWybTk4huDHNbVcviarC0eLxMjwTJtmpM38Yo292s8ek+uOC/V+4SDGx+UN8jo2z8u1DlCHgR1J7M2ZrbrK+nA8hrhAYKMAsPpi8fK4kfDABvo8jF0/rcfkoUms7Bc+MVX8pzXo6raiLk5FfSUaaNEGu5B4OgMpXp8Wj90E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; c=relaxed/simple; bh=byLh/bsiv/fh1hzyDOXgi4uR68X6jhJgLI5muBJNEqE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nui+VMx4tBMzANwg3OA7bGbw0Q7xMG4EARkXs4Md0lWMnFN6UiD8Br8WWmML5zNHs3F3lnneOVqnaj5+W1DdazlbqWgdkG2PK5v8Q8pcZWZNbqxNqUTLjNlf9rq2FI8dv0z6tAwwnsi+tL4CDdn7LYil3llj66nbB1JGZxlowus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m7eMC5vm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m7eMC5vm" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB36EC4CEEB; Wed, 21 May 2025 03:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747797597; bh=byLh/bsiv/fh1hzyDOXgi4uR68X6jhJgLI5muBJNEqE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=m7eMC5vmN1Vmf3n5thadvgyR6KUoa9sRoXHXFv+hySadnmPl4+/HU5w3W/UVIsxNV B1gVT3+Pqp2v0xPDhNIQhmKbuJc0cFJQLfjt/5dDqkvoLcNXfZ4HtJURLJ0+azFo2W 3gIiNtmXmn5PMpgriFh8jGsJkvd7EXPpyQtuSIsecUVSRR47p9cF4HRdRixOkuGQex okDu2IQRxqQjCXLKV6uONIyLKrDo+6CX2Z3VSuN8ySIacuCFvyG9YGSuWrC13CbZgW v2YmZYCKFXOwvvXBagM2yi4Pfl+tR1Msehmsz47w4jc8Nc/yc12X180GzKC6F1HsYq B2cRQJvrp885w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B89CCC3ABC9; Wed, 21 May 2025 03:19:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 21 May 2025 11:19:55 +0800 Subject: [PATCH v2 1/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-1-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=857; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=GTxtiAQGmCYOsgbEQ6EOKgzNKF5l16qDKM+F3b/U1zI=; b=5AEbk6W4rLldJjUDa5G1M6bOgcp0jNU95UuGFwcssijnUcagojYY7KsK0iDWewtysBHF+wIt3 RKOGBvOvBYWCmHTJRxbxt2FfTMb4njhfWQER3YvzACtEVLrwj6EEUs8 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S7. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.y= aml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index c36b6fe377ad..8a6981e9f873 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: oneOf: - - const: amlogic,pinctrl-a4 + - enum: + - amlogic,pinctrl-a4 + - amlogic,pinctrl-s7 - items: - enum: - amlogic,pinctrl-a5 --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BD721FF7B3; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; cv=none; b=oc7C8h6t2JWLaLi7u1CBqe/g8UrvFMSTpnXv2Ip75Q7AyeSVaBX+VIgbDxIYXuqRJ5EvrVtMXr3wCxBlIdUpPWvMWZCpIUYwibDEQHQyHmWq0Uqn2AZJlu5kv8zcsFN3m9vSxqmt+vbf1zD33LeTlrhy5lEfMRU8OjfloGjYwjw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; c=relaxed/simple; bh=SqXI1uvoCkhyqkrY5xjtQtfDKxNrvjB2D2HwRduTNGc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SY+LYzC7O5Lfu3G6zGHOqd2p9Hh6IyB8nHAP40sDz71VuYrpYHg0m/nn+mpqp2drv7tXEtTEPcD1eKcnSSJM7tAlNXOKG8V2pK6odAdlUrP4eXmc/HjZVnBBRYeJXDPLKVF6H4ZPdsz4Q99exIm9GYb2RkrM3DXFbfY4tUqGACA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cSopkJvE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cSopkJvE" Received: by smtp.kernel.org (Postfix) with ESMTPS id D3855C4CEED; Wed, 21 May 2025 03:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747797597; bh=SqXI1uvoCkhyqkrY5xjtQtfDKxNrvjB2D2HwRduTNGc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cSopkJvE0Kf9CTQCl+3k4tYWtdBkGRQCb9G6WmSgt1ZFsgrO/9PAl21runoubb0A9 9lBVWXSZBVFLLlvKHISL5XA2lvvDCqB4NIDN+JnjuWpvpjZ8NWllUFQR8yWi52JslA RU+wd62HTK65zSQ5C60CO1dsx8ojDkZ+QeBI7zHSMZXMfDN6ajRCHByw6/pEGBRND6 5B94q1az7YCSDzkbKFOdIuWR6BCdHsXtmXqGKeTap3KcCUKd50bS0ohWy7Saor/a4p 3iLFRth50SnEA2a0lHs+1vZekLRd8MPFklZcMr7NBUZnXiaf4sk9w9y1qyes9UHPzJ avyJc5SJoYd9A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D08C54E92; Wed, 21 May 2025 03:19:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 21 May 2025 11:19:56 +0800 Subject: [PATCH v2 2/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7D Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-2-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=1044; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=SRGfN0xHu7rPLyCZFtaZT28fxmetKbOy0Gk6C4ftPKQ=; b=xDc0h5Vw1oMx3S0SYBU1t9FdC5hI5owrChjc8tPYukG5Ui+agERsWO8ognjRHA8PZym76ynxy ieA1CvowSUVA6a1WC89YoBskbjrVOPY/oKmnWnNIP7k7mmi+w2gOcZu X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S7D SoC. Amlogic S7D SoCs uses the same pintrl controller as S7 SoCs. There is no need for an extra compatible line in the driver, but add S7D compatible line for documentation. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.y= aml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 8a6981e9f873..96a7c5646c13 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -22,6 +22,10 @@ properties: - enum: - amlogic,pinctrl-a5 - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-s7d + - const: amlogic,pinctrl-s7 =20 "#address-cells": const: 2 --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC661B0F20; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; cv=none; b=p41N0pu7Wbt/OgIZSaaNCuWO5OyvLwgYwZT+DvwClzFYHvUNeTpjllz1ojxygbifxIeOTA6/Dufmjq52IuaIsOiVIRIADdiU7IRoWWh7dG2NxSBqNwPLaUx9G8tM/FcZ31ifKt36mr/KoCiwsUu0W1GLp6C5wiGRldQLKaDsGcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; c=relaxed/simple; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e3Cp6hzOVeu0n4ilfIxQH+gxV1hQxfuYyIkjut8X8uLQrKlczBmOYgXq1Kr5pkIDtoWpsXxzhV49LEbbSCdAlymyzvf/goelpPGrXBv2QCMTdtAta23BM92geU3IuWUh5Nw3ocM81YxsPvhLjxMf9uF8pLB9iD+mW9apSjiqQoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P/mxn9y3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P/mxn9y3" Received: by smtp.kernel.org (Postfix) with ESMTPS id DBE2FC4CEF1; Wed, 21 May 2025 03:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747797597; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=P/mxn9y3r77ow1mNlUSj58ovqamNsESg8/Kevrn2cE2msAxBmALMWBXuaymV9ZwA/ QK9lRD7CVZPyQuyF/huvjxhJeXEmh7kuiFH3Te3AUNtPXKy6fPdYjKd/J+AWzs/0KM MGD+NJacFRwt8MLAbf4/RVJQnZBBDNGG6vQIJpsysctVyT1QEF8ZyZZyrkQet5ZyPb Ci9sYgFKXC4uCnl2H8avb/FLzcHgOcnxftg+uiCLxI/gZ42qW+7gKlMg/GblE8BNhL eKx1ApWyO/Lx6WgI6j/XrWYJivQpDCvcQETF951Oku+tr+x6ue5s2upvV0P6si31W5 hD/s9qm3UtDoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1DFEC54E90; Wed, 21 May 2025 03:19:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 21 May 2025 11:19:57 +0800 Subject: [PATCH v2 3/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-3-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=777; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=SGs48wURMjraERop2ENTKoLj76g7oJ3ublU0QekYvzE=; b=Qt5nX5BPUxyZHj1gFAIs7uDZ/upCK3i0jkdHqry6mRyIScoOtknKTKFy2qmuUdObrWo4G+b+E 4/UadHNq18uCcwbXtuXngUoIpK2bJz7DhYfBM/RAYjertkKpB3WUVBV X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S6 SoC. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.y= aml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 96a7c5646c13..61a4685f9748 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: - enum: --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC06BA36; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; cv=none; b=WQHUjBJ0vIGCjhM0wyCm9Ocboj0sAxb6rsRmsI+814uh4NUhKBhLAcB6Dk+3kX/LZ76mOKuM0XcS/AILmzY5m56yaNwqsi3nDeVAZVAz/aN35oOSVWEEUz4jHNoe1BcQu57n+f92KNvA6l41ggaxsYPH7Io2CCP0zqcqB33t0i8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; c=relaxed/simple; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=St7LnqoV9LaztUAmRzoZW30KNr6pJk4fwt1Hxkh9pFQobIDeNTdujnz6qZigYquWfUU6ZKkM9DSOpvsNWWEkPl4QivAHlfIsg81icnxWM0fL1DDlGX1uIEOO8cpXlsYHJ0NOyAOfaoJLaT+FZqeLFyksqwvTzHNiG9cvTCZjasA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U8U69ETY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U8U69ETY" Received: by smtp.kernel.org (Postfix) with ESMTPS id E8A88C4CEF3; Wed, 21 May 2025 03:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747797598; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=U8U69ETYhCgpd/7xhhjYmm8NwvdXgy+CAK9MhNtZD6qGE97BjA8XblYcuWq1XhReZ KaBPn47XEl368VuF4STArQwOSMgk4effgpJ3Qva433ElHV3esM6cyL85csvXQl3xcY 5gHioKfhrl/r1cn8H4uoaP3E3g1N9VEGl9XL/WlYcf/gexDDbJgQ86DcBOBGMK9yIs q81a9arOPqFxsnM7ykfccjngF761oSsD6ldvn/tuAdZTMrc0VrIDTwfX8f7uFJJu4a FIscGGuE+jv+AIlBZh6AjKEX36oCGklU2nX0nO3ZSs2Vo3kYXoABu/qwxPOqA6PSlE l7YL1PuWECqow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE33DC2D0CD; Wed, 21 May 2025 03:19:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 21 May 2025 11:19:58 +0800 Subject: [PATCH v2 4/8] pinctrl: meson: a4: remove special data processing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-4-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=1982; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=FRMEmxN5zjpQVQOxtUKSm3GQm/lC+q2P8YsijCrDdRM=; b=BnUKwq9rFXD1xM0UERW/kxg0uFOop/YPcCnUe/9W5BaSlFuIliZYLkIBEsUp33Ekw0SpcHRNL 6PVxLZTla9/B/3TM2VXV73w0ISjrM18REAbx66iqdQx8TP3YxfETe1G X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao According to the data specifications of Amlogic's existing SoCs, the function register offset and the bit offset are the same value among various chips. Therefore, general processing can be carried out without the need for private data modification. Drop special data processing. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 33 +++-----------------------= ---- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/m= eson/pinctrl-amlogic-a4.c index a76f266b4b94..90d4d10ca10b 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,15 +50,8 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; =20 -struct aml_reg_bit { - u32 bank_id; - u32 reg_offs[AML_NUM_REG]; - u32 bit_offs[AML_NUM_REG]; -}; - struct aml_pctl_data { unsigned int number; - struct aml_reg_bit rb_offs[]; }; =20 struct aml_pmx_func { @@ -843,31 +836,11 @@ static const struct gpio_chip aml_gpio_template =3D { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { - const struct aml_pctl_data *data =3D info->data; - const struct aml_reg_bit *aml_rb; - bool def_offs =3D true; int i; =20 - if (data) { - for (i =3D 0; i < data->number; i++) { - aml_rb =3D &data->rb_offs[i]; - if (bank->bank_id =3D=3D aml_rb->bank_id) { - def_offs =3D false; - break; - } - } - } - - if (def_offs) { - for (i =3D 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; - bank->pc.bit_offset[i] =3D 0; - } - } else { - for (i =3D 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] =3D aml_rb->reg_offs[i]; - bank->pc.bit_offset[i] =3D aml_rb->bit_offs[i]; - } + for (i =3D 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; + bank->pc.bit_offset[i] =3D 0; } } =20 --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 841AF22D9FB; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-5-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=5342; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=qYNWhkH55B8d6PXwynFbW7T5kFGFgc23N8HQ5eIP7KU=; b=QvYZPAPFGbFupNf3kMpAq0MdikmqUAzF9AkXLAjKTxDOrf3pOwraAOdhugAivF8DWRbC4FKSK FMX5FoBXxyfC1xgktF5YcL60skrUEzR9hMrVZYdwt3yuXnnp9Wnb9nu X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao In some Amlogic SoCs, to save register space or due to some abnormal arrangements, two sets of pins share one mux register. A group starting from pin0 is the main pin group, which acquires the register address through DTS and has management permissions, but the register bit offset is undetermined. Another GPIO group as a subordinate group. Some pins mux use share register and bit offset from bit0 . But this group do not have register management permissions. This submission implements this situation. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 101 +++++++++++++++++++++++++= +++- 1 file changed, 99 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/m= eson/pinctrl-amlogic-a4.c index 90d4d10ca10b..598c126ff62e 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,8 +50,23 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; =20 +/* + * partial bank(subordinate) pins mux config use other bank(main) mux regi= stgers + * m_bank_id: the main bank which pin_id from 0, but register bit not from= bit 0 + * m_bit_offs: bit offset the main bank mux register + * sid: start pin_id of subordinate bank + * eid: end pin_id of subordinate bank + */ +struct multi_mux { + unsigned int m_bank_id; + unsigned int m_bit_offs; + unsigned int sid; + unsigned int eid; +}; + struct aml_pctl_data { unsigned int number; + const struct multi_mux *p_mux; }; =20 struct aml_pmx_func { @@ -71,10 +86,12 @@ struct aml_gpio_bank { struct gpio_chip gpio_chip; struct aml_pio_control pc; u32 bank_id; + u32 mux_bit_offs; unsigned int pin_base; struct regmap *reg_mux; struct regmap *reg_gpio; struct regmap *reg_ds; + const struct multi_mux *p_mux; }; =20 struct aml_pinctrl { @@ -106,13 +123,46 @@ static const char *aml_bank_name[31] =3D { "GPIOCC", "TEST_N", "ANALOG" }; =20 +const struct multi_mux multi_mux_s7[] =3D { + { + .m_bank_id =3D AMLOGIC_GPIO_CC, + .m_bit_offs =3D 24, + .sid =3D (AMLOGIC_GPIO_X << 8) + 16, + .eid =3D (AMLOGIC_GPIO_X << 8) + 19, + }, +}; + +const struct aml_pctl_data s7_priv_data =3D { + .number =3D ARRAY_SIZE(multi_mux_s7), + .p_mux =3D multi_mux_s7, +}; + +const struct multi_mux multi_mux_s6[] =3D { + { + .m_bank_id =3D AMLOGIC_GPIO_CC, + .m_bit_offs =3D 24, + .sid =3D (AMLOGIC_GPIO_X << 8) + 16, + .eid =3D (AMLOGIC_GPIO_X << 8) + 19, + }, { + .m_bank_id =3D AMLOGIC_GPIO_F, + .m_bit_offs =3D 4, + .sid =3D (AMLOGIC_GPIO_D << 8) + 6, + .eid =3D (AMLOGIC_GPIO_D << 8) + 6, + }, +}; + +const struct aml_pctl_data s6_priv_data =3D { + .number =3D ARRAY_SIZE(multi_mux_s6), + .p_mux =3D multi_mux_s6, +}; + static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, unsigned int pin, unsigned int *reg, unsigned int *offset) { unsigned int shift; =20 - shift =3D (pin - range->pin_base) << 2; + shift =3D ((pin - range->pin_base) << 2) + *offset; *reg =3D (shift / 32) * 4; *offset =3D shift % 32; =20 @@ -124,9 +174,36 @@ static int aml_pctl_set_function(struct aml_pinctrl *i= nfo, int pin_id, int func) { struct aml_gpio_bank *bank =3D gpio_chip_to_bank(range->gc); + unsigned int shift; int reg; - int offset; + int i; + unsigned int offset =3D bank->mux_bit_offs; + const struct multi_mux *p_mux; + + /* peculiar mux reg set */ + if (bank->p_mux) { + p_mux =3D bank->p_mux; + if (pin_id >=3D p_mux->sid && pin_id <=3D p_mux->eid) { + bank =3D NULL; + for (i =3D 0; i < info->nbanks; i++) { + if (info->banks[i].bank_id =3D=3D p_mux->m_bank_id) { + bank =3D &info->banks[i]; + break; + } + } + + if (!bank || !bank->reg_mux) + return -EINVAL; + + shift =3D (pin_id - p_mux->sid) << 2; + reg =3D (shift / 32) * 4; + offset =3D shift % 32; + return regmap_update_bits(bank->reg_mux, reg, + 0xf << offset, (func & 0xf) << offset); + } + } =20 + /* normal mux reg set */ if (!bank->reg_mux) return 0; =20 @@ -836,12 +913,30 @@ static const struct gpio_chip aml_gpio_template =3D { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { + const struct aml_pctl_data *data =3D info->data; + const struct multi_mux *p_mux; int i; =20 for (i =3D 0; i < AML_NUM_REG; i++) { bank->pc.reg_offset[i] =3D aml_def_regoffs[i]; bank->pc.bit_offset[i] =3D 0; } + + bank->mux_bit_offs =3D 0; + + if (data) { + for (i =3D 0; i < data->number; i++) { + p_mux =3D &data->p_mux[i]; + if (bank->bank_id =3D=3D p_mux->m_bank_id) { + bank->mux_bit_offs =3D p_mux->m_bit_offs; + break; + } + if (p_mux->sid >> 8 =3D=3D bank->bank_id) { + bank->p_mux =3D p_mux; + break; + } + } + } } =20 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, @@ -1008,6 +1103,8 @@ static int aml_pctl_probe(struct platform_device *pde= v) =20 static const struct of_device_id aml_pctl_of_match[] =3D { { .compatible =3D "amlogic,pinctrl-a4", }, + { .compatible =3D "amlogic,pinctrl-s7", .data =3D &s7_priv_data, }, + { .compatible =3D "amlogic,pinctrl-s6", .data =3D &s6_priv_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 822D222D9F8; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; cv=none; b=CrzSg1Xuj7fOGXOeUGHaZ6GXY7Zv6OGAkeYwb96DRhLuKJOX5h3VX2MmL3pyz5BLU2NXkYsfQJvrFmIOd1Q3KaUwlsXTSJDIDdUF0PkwkGAMKWnizjGirWj8P+TroRkq2JgnEyHaHutgitlgwrdTLmQalNMKVUEr9avG+Z526hc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747797598; c=relaxed/simple; bh=Hj/dtiodyDNGd1NBE4jDypDZMQYKxKPm40P5Dg7K4HU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 21 May 2025 03:19:58 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 21 May 2025 11:20:00 +0800 Subject: [PATCH v2 6/8] dts: arm64: amlogic: add S7 pinctrl node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-6-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=3129; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=fjCfY1jseWaBwy2ltob7mgikXcrVQkc9RawMyG1Dk4I=; b=L8ZMYTQOjtVZCs8goewOzpjby9CPsZsGv82xLFuzqFPqLBLZj/98aRkcRGDtSQYSgW0uJTH1W cj9CsA/QQrAD2PJNJwrN99KKJqnKWl0ZiiENaoPWqKjilMX+MTVnKcV X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s7.dtsi index f0c172681bd1..260918b37b9a 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { cpus { @@ -94,6 +95,86 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s7"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x40 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + test_n: gpio@2c0 { + reg =3D <0 0x2c0 0 0x20>; + reg-names =3D "gpio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg =3D <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; --=20 2.37.1 From nobody Wed Dec 17 06:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A212522DFA2; Wed, 21 May 2025 03:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-7-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=3401; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=TkCzL2tpFVGFSar0wGinjtXWgNKBSbV+l775+YV5x9c=; b=ttM8jO5nGDymX1YFRUcxMmwbQSMx0Wqdxry5szVp8au4nIv8BJ5KrPKgSvBRsRK0f29NKillG l0SMQu2vIcVC6DuUPtVvrPHkiexCOvr33QLai7NDvwFf8tFXkrGXbwn X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7D. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 90 ++++++++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot= /dts/amlogic/amlogic-s7d.dtsi index e1099bc1535d..c4d260d5bb58 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { cpus { @@ -94,6 +95,95 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s7d", + "amlogic,pinctrl-s7"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x40 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250521-s6-s7-pinctrl-v2-8-0ce5e3728404@amlogic.com> References: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> In-Reply-To: <20250521-s6-s7-pinctrl-v2-0-0ce5e3728404@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747797595; l=3615; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=qrXyaWIhl6dY6RYbLmLL01WMo+S+QWiFeDMWvb8QD9A=; b=be2px7TJFHE12t97jPTpVsQBaIMxh//o3rr4yUfe+pD9PCQpkiDCcmv3ucVF+oPgziqUvDIMq bwcgD7WJak9AHWYjOvMozHXsy6dEaKGRLSlJq3VXaMIltnBeCIhAjNw X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S6. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 +++++++++++++++++++++++++= ++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s6.dtsi index a8c90245c42a..5f602f1170c0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { #address-cells =3D <2>; @@ -92,6 +93,102 @@ uart_b: serial@7a000 { clock-names =3D "xtal", "pclk", "baud"; status =3D "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,pinctrl-s6"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg =3D <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg =3D <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg =3D <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 9>; + }; + + gpiod: gpio@180 { + reg =3D <0 0x180 0 0x20>, <0 0x8 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 7>; + }; + + gpiof: gpio@1a0 { + reg =3D <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_F<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg =3D <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 3>; + }; + + gpioc: gpio@200 { + reg =3D <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg =3D <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioa: gpio@280 { + reg =3D <0 0x280 0 0x20>, <0 0x40 0 0x8>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 16>; + }; + + test_n: gpio@2c0 { + reg =3D <0 0x2c0 0 0x20>; + reg-names =3D "gpio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg =3D <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names =3D "gpio", "mux"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; --=20 2.37.1