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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 511E23F7061; Tue, 20 May 2025 06:07:48 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 2/4 v2] crypto: octeontx2: Fix address alignment issue on ucode loading Date: Tue, 20 May 2025 18:37:35 +0530 Message-ID: <20250520130737.4181994-3-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=b8uy4sGx c=1 sm=1 tr=0 ts=682c7ea9 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=ub5NSpVJfYrinLkKqRIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: olhpXK5So6qKuNjGuL2zlBSu_2HPqY99 X-Proofpoint-ORIG-GUID: olhpXK5So6qKuNjGuL2zlBSu_2HPqY99 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX0MLIo7fHjGfI hPTN8+93NS4GWBgASuoLMlJ7Kvh28PjQiEFoMaN48/pp9HioH4IYVga5vh4VVA3ARPiTYq5Lnwt w3a50UmRU9nml9BzQ+rrBbK3K1rtHZSo7LuO2AxmvctLorg6OiP8tA8g0nB8TnEak+WF3fJK+xS Y8j6cXKoPJaxN9vm6A68yry5hKb087TjNSpyo//U7TT+gDjEPujuWD76yGZ4avEk1x7CA5hlFcI 4aJT8Ej+/Hbl7D0iwpR0ohn+zHkL518krr3JShf8MHvkTc4baR8m93vHVGRQCDbu3tUVxmlfF/w fjFNBcI+kEETdnDadCb82PNlx/0nDn7ESZB522PD+y7Z3m0cm+NfXul+wRKg39Spv4atKaf+jxM phV5vGFRURdxNGSEtL049RU2vKkws5qNAO6S8VXHzgN6dv36BCbMLFyzJ4qx6ptdGfC7S8VR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size()" Completion address should be 32-Byte alignment when loading microcode. Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v1->v2: - No Change .../marvell/octeontx2/otx2_cptpf_ucode.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 9095dea2748d..3e8357c0ecb2 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1491,12 +1491,13 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) union otx2_cpt_opcode opcode; union otx2_cpt_res_s *result; union otx2_cpt_inst_s inst; + dma_addr_t result_baddr; dma_addr_t rptr_baddr; struct pci_dev *pdev; - u32 len, compl_rlen; int timeout =3D 10000; int ret, etype; void *rptr; + u32 len; =20 /* * We don't get capabilities if it was already done @@ -1519,22 +1520,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) if (ret) goto delete_grps; =20 - compl_rlen =3D ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN); - len =3D compl_rlen + LOADFVC_RLEN; + len =3D LOADFVC_RLEN + sizeof(union otx2_cpt_res_s) + + OTX2_CPT_RES_ADDR_ALIGN; =20 - result =3D kzalloc(len, GFP_KERNEL); - if (!result) { + rptr =3D kzalloc(len, GFP_KERNEL); + if (!rptr) { ret =3D -ENOMEM; goto lf_cleanup; } - rptr_baddr =3D dma_map_single(&pdev->dev, (void *)result, len, + + rptr_baddr =3D dma_map_single(&pdev->dev, rptr, len, DMA_BIDIRECTIONAL); if (dma_mapping_error(&pdev->dev, rptr_baddr)) { dev_err(&pdev->dev, "DMA mapping failed\n"); ret =3D -EFAULT; - goto free_result; + goto free_rptr; } - rptr =3D (u8 *)result + compl_rlen; + + result =3D (union otx2_cpt_res_s *)PTR_ALIGN(rptr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); + result_baddr =3D ALIGN(rptr_baddr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); =20 /* Fill in the command */ opcode.s.major =3D LOADFVC_MAJOR_OP; @@ -1546,14 +1552,14 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) /* 64-bit swap for microcode data reads, not needed for addresses */ cpu_to_be64s(&iq_cmd.cmd.u); iq_cmd.dptr =3D 0; - iq_cmd.rptr =3D rptr_baddr + compl_rlen; + iq_cmd.rptr =3D rptr_baddr; iq_cmd.cptr.u =3D 0; =20 for (etype =3D 1; etype < OTX2_CPT_MAX_ENG_TYPES; etype++) { result->s.compcode =3D OTX2_CPT_COMPLETION_CODE_INIT; iq_cmd.cptr.s.grp =3D otx2_cpt_get_eng_grp(&cptpf->eng_grps, etype); - otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); + otx2_cpt_fill_inst(&inst, &iq_cmd, result_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); timeout =3D 10000; =20 @@ -1576,8 +1582,8 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) =20 error_no_response: dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); -free_result: - kfree(result); +free_rptr: + kfree(rptr); lf_cleanup: otx2_cptlf_shutdown(lfs); delete_grps: --=20 2.34.1