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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 1F95D3F7061; Tue, 20 May 2025 06:07:43 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 1/4 v2] crypto: octeontx2: add timeout for load_fvc completion poll Date: Tue, 20 May 2025 18:37:34 +0530 Message-ID: <20250520130737.4181994-2-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX7WNo3O7QzqXi fmx7NW0n8TJwzZZwy+NNweC7oyTSPFIriHviAu2Xcs17vn+n3ED/YmnhacmFilSEoPRkzGb5Qx0 aVHWV2iwhnx5Q1e91e/MsFNXP1nJMZtx07rqHatLGA9zVGayirt7Fzg1FPBVeVz/sLc5db1OvYb x8lhcaY9jROFd2vou5PY4+Q88oFvYyhWayGJZN7IIhQEa4tw2Fw+W76cAfoBxVA327TafGKP8R+ mm+LZJnZar8PqrLF5YI45rj8v5mIxq0bSx70VWUHBe8eA8HkKiWk0cEJeBa+a3xsst8rWkyZduB OP1Huoz21wjzEpkch+6i7Kk7BDlogthK9wyhnO7hdi7BU8SEfWzL3qho6fzzBy7BklIbM0ya8u4 uJmD920o4dCGS8KbDrE72aFXeSSyi6vUBpHSyfJe8EBPwovHMFZlMHEY1Ttf6+2ZP2xW2nCf X-Proofpoint-ORIG-GUID: KGc0KakT1Kx4ITyKx8BNaovJEtDRJ1t2 X-Authority-Analysis: v=2.4 cv=BqCdwZX5 c=1 sm=1 tr=0 ts=682c7ea5 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=dP9LQboaRqI6G61vZ2MA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: KGc0KakT1Kx4ITyKx8BNaovJEtDRJ1t2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Adds timeout to exit from possible infinite loop, which polls on CPT instruction(load_fvc) completion. Signed-off-by: Srujana Challa Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v1->v2: - No Change .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 78367849c3d5..9095dea2748d 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1494,6 +1494,7 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) dma_addr_t rptr_baddr; struct pci_dev *pdev; u32 len, compl_rlen; + int timeout =3D 10000; int ret, etype; void *rptr; =20 @@ -1554,16 +1555,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) etype); otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); + timeout =3D 10000; =20 while (lfs->ops->cpt_get_compcode(result) =3D=3D - OTX2_CPT_COMPLETION_CODE_INIT) + OTX2_CPT_COMPLETION_CODE_INIT) { cpu_relax(); + udelay(1); + timeout--; + if (!timeout) { + ret =3D -ENODEV; + cptpf->is_eng_caps_discovered =3D false; + dev_warn(&pdev->dev, "Timeout on CPT load_fvc completion poll\n"); + goto error_no_response; + } + } =20 cptpf->eng_caps[etype].u =3D be64_to_cpup(rptr); } - dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); cptpf->is_eng_caps_discovered =3D true; =20 +error_no_response: + dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); free_result: kfree(result); lf_cleanup: --=20 2.34.1 From nobody Fri Dec 19 13:08:33 2025 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E035A101F2; Tue, 20 May 2025 13:08:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747746483; cv=none; b=oB6oJSDnzsUCritE2wOeEbwwCE5SM7X8j+L5/zKBoX3Ev8nDIv5M9xVroJebBNPRAhc2Jhd4YtYg+pQsgneaSOfppWHGI3s/Kbr2yOEKe4Fo6qRVwPdBSS1HEP9bWbXVum8lxgl7+nrX9p2Pfij60ofIqh/3fjzVWgEDH8vJlpE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747746483; c=relaxed/simple; bh=I52q+hoDuobCy/FE574vOeIZBD8bXnP6OQrciNhZ8HI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DRAvFRciowcisSRrnqXsmeMABFwnx+QuC6vb1rpZ+TiA5KnMBKtkEjAKO55B2hFldONvleoauvPmIX0/gCWkzsmNBnDG+IlKARlRJemkYsz99rPQvmZmXTIPIqvPAu/xl47lB7GOmK+siYBRjZxO36P2vA6Di2hAN770Fn0XpHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=RgkWp0Gd; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="RgkWp0Gd" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54KAHgCI005546; Tue, 20 May 2025 06:07:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=A SbBzYuT1HPa+UBLObZa/rHSQ7RZhJDOVONg8UkQXQI=; b=RgkWp0Gdzt+WhToNc CKhi+F6iSqBC+G9KtQ5XzAnoI+Robm2zs6blv7hzmV+8Y4kn9EmMfu7oQii+sXKG ngA5HaMj/6BjscQdcJKfqP6pW0l60pFPWnqNUfPlpst+EPMLHy+MhxSgyH+9qp9Q K35yT3x+C5x8BMXLtJgK5YihHLojE6p9bOH236YaKr3trnBaIHRbiD5s1FwHi15N oPCtEfTFoFdBeNKTM5h5Aj+FCwogQcoipMKDC8VZGrg9VY4xAWRqIFrUN+eSIsjX AG8rCYSK1oayYN+T9X/FOpX7R5RUfuNHDGKmNwRmYfsOjHTWKA5OIpHaGgIy5w7v yoM/A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 46q46fcvcp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 May 2025 06:07:53 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 20 May 2025 06:07:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 20 May 2025 06:07:51 -0700 Received: from bharat-OptiPlex-Tower-Plus-7020.. (unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 511E23F7061; Tue, 20 May 2025 06:07:48 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 2/4 v2] crypto: octeontx2: Fix address alignment issue on ucode loading Date: Tue, 20 May 2025 18:37:35 +0530 Message-ID: <20250520130737.4181994-3-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=b8uy4sGx c=1 sm=1 tr=0 ts=682c7ea9 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=ub5NSpVJfYrinLkKqRIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: olhpXK5So6qKuNjGuL2zlBSu_2HPqY99 X-Proofpoint-ORIG-GUID: olhpXK5So6qKuNjGuL2zlBSu_2HPqY99 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX0MLIo7fHjGfI hPTN8+93NS4GWBgASuoLMlJ7Kvh28PjQiEFoMaN48/pp9HioH4IYVga5vh4VVA3ARPiTYq5Lnwt w3a50UmRU9nml9BzQ+rrBbK3K1rtHZSo7LuO2AxmvctLorg6OiP8tA8g0nB8TnEak+WF3fJK+xS Y8j6cXKoPJaxN9vm6A68yry5hKb087TjNSpyo//U7TT+gDjEPujuWD76yGZ4avEk1x7CA5hlFcI 4aJT8Ej+/Hbl7D0iwpR0ohn+zHkL518krr3JShf8MHvkTc4baR8m93vHVGRQCDbu3tUVxmlfF/w fjFNBcI+kEETdnDadCb82PNlx/0nDn7ESZB522PD+y7Z3m0cm+NfXul+wRKg39Spv4atKaf+jxM phV5vGFRURdxNGSEtL049RU2vKkws5qNAO6S8VXHzgN6dv36BCbMLFyzJ4qx6ptdGfC7S8VR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size()" Completion address should be 32-Byte alignment when loading microcode. Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v1->v2: - No Change .../marvell/octeontx2/otx2_cptpf_ucode.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 9095dea2748d..3e8357c0ecb2 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1491,12 +1491,13 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) union otx2_cpt_opcode opcode; union otx2_cpt_res_s *result; union otx2_cpt_inst_s inst; + dma_addr_t result_baddr; dma_addr_t rptr_baddr; struct pci_dev *pdev; - u32 len, compl_rlen; int timeout =3D 10000; int ret, etype; void *rptr; + u32 len; =20 /* * We don't get capabilities if it was already done @@ -1519,22 +1520,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) if (ret) goto delete_grps; =20 - compl_rlen =3D ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN); - len =3D compl_rlen + LOADFVC_RLEN; + len =3D LOADFVC_RLEN + sizeof(union otx2_cpt_res_s) + + OTX2_CPT_RES_ADDR_ALIGN; =20 - result =3D kzalloc(len, GFP_KERNEL); - if (!result) { + rptr =3D kzalloc(len, GFP_KERNEL); + if (!rptr) { ret =3D -ENOMEM; goto lf_cleanup; } - rptr_baddr =3D dma_map_single(&pdev->dev, (void *)result, len, + + rptr_baddr =3D dma_map_single(&pdev->dev, rptr, len, DMA_BIDIRECTIONAL); if (dma_mapping_error(&pdev->dev, rptr_baddr)) { dev_err(&pdev->dev, "DMA mapping failed\n"); ret =3D -EFAULT; - goto free_result; + goto free_rptr; } - rptr =3D (u8 *)result + compl_rlen; + + result =3D (union otx2_cpt_res_s *)PTR_ALIGN(rptr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); + result_baddr =3D ALIGN(rptr_baddr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); =20 /* Fill in the command */ opcode.s.major =3D LOADFVC_MAJOR_OP; @@ -1546,14 +1552,14 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) /* 64-bit swap for microcode data reads, not needed for addresses */ cpu_to_be64s(&iq_cmd.cmd.u); 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 64E6F3F7061; Tue, 20 May 2025 06:07:52 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 3/4 v2] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Date: Tue, 20 May 2025 18:37:36 +0530 Message-ID: <20250520130737.4181994-4-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: l8g_urLdKfNUC3avzQVSHSb9VaW9hem2 X-Authority-Analysis: v=2.4 cv=HuR2G1TS c=1 sm=1 tr=0 ts=682c7eac cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=_7N3KsqXCoWpZ83F5FEA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: l8g_urLdKfNUC3avzQVSHSb9VaW9hem2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfXzcOStxtzQxJT NvBNIAqbdhNe0VeSi+rZY2VQxsOQCxe9tWZXC1XsrDzmWgizwylfg8L5TZmWNgwBor7DKmLXVFO Dr6AHMoKXGlkBowerka+9PrENC6RZJW6zrBHX/7FmX5nphRIdBnBTqhzinvxeCQYynRhl7bFHY3 crgQlnI0rfJ1TDOqA33tMzGsh34mvDUaZfwclakg5T811ALH9UJnIKizzKat5B8rqRCFLkeDEai U85KCFI3uz0KYOsoMtXhpDyPv+LOhgU3ZWPUWj9jqwIFmJniaGvk79XBYJ+Kk5TEQ5liatWWm0G 788M7UykAPuZR3+XnE2iONjLsxKECzj33SanK39QVsHqWjRH4BBB1HCDcIdV68ylOc5JS+kj3mf JFlCay/tXtjo0Hh7Pqfb4NDaEqYxp/7vdnv9GRh+W066rk6NAt9mzUQKin+ElDqZBENW8XXe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: #v6.5+ --- v1->v2: - Fixed memory padding size calculation as per review comment=20 .../marvell/octeontx2/otx2_cpt_reqmgr.h | 64 ++++++++++++++----- 1 file changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..bb4e067ae826 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -34,6 +34,9 @@ #define SG_COMP_2 2 #define SG_COMP_1 1 =20 +#define OTX2_CPT_DPTR_RPTR_ALIGN 8 +#define OTX2_CPT_RES_ADDR_ALIGN 32 + union otx2_cpt_opcode { u16 flags; struct { @@ -417,10 +420,9 @@ static inline struct otx2_cpt_inst_info * otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - int align =3D OTX2_CPT_DMA_MINALIGN; struct otx2_cpt_inst_info *info; - u32 dlen, align_dlen, info_len; - u16 g_sz_bytes, s_sz_bytes; + u32 dlen, info_len; + u16 g_len, s_len; u32 total_mem_len; =20 if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || @@ -429,22 +431,52 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2= _cpt_req_info *req, return NULL; } =20 - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ =20 - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; - align_dlen =3D ALIGN(dlen, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D align_dlen + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + s_len =3D ((req->out_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + + dlen =3D g_len + s_len + SG_LIST_HDR_SIZE; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + dlen; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (OTX2_CPT_RES_ADDR_ALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) return NULL; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer =3D info->in_buffer + SG_LIST_HDR_SIZE + g_len; =20 ((u16 *)info->in_buffer)[0] =3D req->out_cnt; ((u16 *)info->in_buffer)[1] =3D req->in_cnt; @@ -460,7 +492,7 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_c= pt_req_info *req, } =20 if (setup_sgio_components(pdev, req->out, req->out_cnt, - &info->in_buffer[8 + g_sz_bytes])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -476,8 +508,10 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_= cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + align_dlen; - info->comp_baddr =3D info->dptr_baddr + align_dlen; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + dlen), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + dlen), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1 From nobody Fri Dec 19 13:08:33 2025 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5293A22D78D; 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 741103F7065; Tue, 20 May 2025 06:07:56 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , CC: Bharat Bhushan , Subject: [PATCH 4/4 v2] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Tue, 20 May 2025 18:37:37 +0530 Message-ID: <20250520130737.4181994-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250520130737.4181994-1-bbhushan2@marvell.com> References: <20250520130737.4181994-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDEwNSBTYWx0ZWRfX4Qele+icYLbn bGwFnBW59MWjNUb1iyVH+awXF9oMoVopckc4kilRcpAXlvXbsyQWFg3Mmq2rmVHYg0Gy54vmRqm MD9lFOz0AgphQxX/MG10FrrOtyHQRumEnR+JTgXh/kJaTMx91lKd4h8QhMAd7/9J/aA1nmV0WQy 0xOmxvFbrZkEHWVHZTJsncFdvm0/yuansFrIQH6bCj+XQzi8YK6nhoe0ujZpyUONKGECSV+D9VR GT14nyAtdFYNpSbz3DDYdZnhMV5T+xHkVLVWUFYVVKmnCehRiLAs/Y9v/loNVWnn67m79H10WcR 7qTlfRqGYTo6Nxufo4k8FI7MLD8YoDII4VMnhrMBlaqHfwir/wRkmUUKbUXCRnRpiPIzim8olZY n/6yNHf4jwOzrcrVSZUbB4Vqj/A1Ha7rfAfkBXUf/2NbTUNfZccY1tCyv3xyKlUh89BHmEFV X-Proofpoint-ORIG-GUID: NVCHJ3yVRSytzNs950JmBf8zBc1HMC8y X-Authority-Analysis: v=2.4 cv=BqCdwZX5 c=1 sm=1 tr=0 ts=682c7eb1 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=VwQbUJbxAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: NVCHJ3yVRSytzNs950JmBf8zBc1HMC8y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_05,2025-05-16_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan Cc: #v6.8+ --- v1->v2: - Fixed memory padding size calculation as per review comment=20 .../marvell/octeontx2/otx2_cpt_reqmgr.h | 59 ++++++++++++++----- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index bb4e067ae826..766fa63fb075 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,47 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen =3D 0, g_len, sg_len, info_len; - int align =3D OTX2_CPT_DMA_MINALIGN; + u32 dlen =3D 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; =20 - g_sz_bytes =3D ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ =20 - g_len =3D ALIGN(g_sz_bytes, align); - sg_len =3D ALIGN(g_len + s_sz_bytes, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len =3D ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len =3D g_len + s_len; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + sg_len; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN); + total_mem_len +=3D (OTX2_CPT_RES_ADDR_ALIGN - 1) & + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1); + total_mem_len +=3D sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +400,9 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, dlen +=3D req->in[i].size; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer =3D info->in_buffer + g_len; info->gthr_sz =3D req->in_cnt; info->sctr_sz =3D req->out_cnt; =20 @@ -387,7 +414,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, } =20 if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +431,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct ot= x2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + sg_len; - info->comp_baddr =3D info->dptr_baddr + sg_len; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1