From nobody Tue Oct 7 20:20:12 2025 Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A1B1E0DCB; Tue, 20 May 2025 02:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747709314; cv=none; b=apSesBFJ8MGuedQHRoir2sz/SDTRS/n1b7vdmydiip4lpDptj8992p1p6nMjeV6qWJO+jFE3ApTmXzxZTSiDctnMZ3leAbfp8ezefwcjGUhBLtW7UAO58zBv+2VO485fdGXnoVHyMlNtenh5PqF+cc/tVeDleYggS4ZwOSx9CKM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747709314; c=relaxed/simple; bh=vqGigXA8EmHjZv5xyB30aWNaNpthSwxwCcCPPSpr5jA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=lSBm8wFMYYaqGBP63lHnhXEZHm6jv/4gPPS4GZv21yOvmhc1Ma0hjHNv/caGg3Fc70RtsQlMGa2JgLZIYxc0/r+47SgY+5vxRQZmFBYFRHHLGBfpaZeAEd3Gn/R2netEuruVuD7hsR4OGcFrLFXQJcpzYkwqz6XUkvjecMK3gIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com; spf=pass smtp.mailfrom=airkyi.com; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b=mkM7xDda; arc=none smtp.client-ip=54.207.22.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=airkyi.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b="mkM7xDda" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=airkyi.com; s=altu2504; t=1747709275; bh=975XiWevg8IyB7+oWu6bLHHS0g5LCqgBcM0TSyV2q3I=; h=From:To:Subject:Date:Message-Id; b=mkM7xDdaH0y6I6R4g02anci2qkHgfa9eyRV2I05TN6eA+3ATjXyIYUA/cULtHj9En odewUybff2ZpMQMDWaOPjp181x84xSh8NwFidYG+GYn8/Yus39tJ9NnSv53if0XNTk h4+3BPAV397Un1dSHhu63IUfatmuNGJo7dnJAd3w= X-QQ-mid: zesmtpgz1t1747709273t11c1660b X-QQ-Originating-IP: j08/Knoc5sKowREV0R+oKB6ClVB4MQa1mQa6PVd9N1Y= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 20 May 2025 10:47:51 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12805088329180934383 From: Chaoyi Chen To: Sandy Huang , Heiko Stuebner , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Chaoyi Chen , Dragan Simic , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/2] arm64: dts: rockchip: Improve coding style for rk3399 cdn_dp Date: Tue, 20 May 2025 10:47:17 +0800 Message-Id: <20250520024718.142-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250520024718.142-1-kernel@airkyi.com> References: <20250520024718.142-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:airkyi.com:qybglogicsvrsz:qybglogicsvrsz4a-0 X-QQ-XMAILINFO: N2uXtyrSU4Fu6EA0u/l5EunOWvgacxe3CqKiCCUnZUkKMFDiM8Jo5TXe jne0o5DuF7ToyCNudnq3e1TzRvK51jkykvuKimQz4waQKMPBn4f5p+dW/dsKAK6Zb38nVay o00xIywXmVegfBap4fAo/5IBL99/bmz6blLeEAbc2vlp5WV7Q36XCkV2Tn0e4L4Ox2HAK78 ngwK+E2mL7/rDPzKKqXEZ0xBHB8tmDp/k6e2auoCQTJCmcbBEDahcvfaHrAZPlNpgmpRtF2 VfFrWBXjPRTmIK18fs6MjYX+mH6VaJpwljMygx/IwpvSZaKDfL7mRIWoJtb1j2JbsCHppHG fuHgvmzlDRaJQNXiFbo7BObbb6vDKEnFnITF6119J1Lhr7A2PEdGWirI8S8U5Nf89VCpVlQ y+YwvMJ4xrhK86zdCLQpB3nJTSSg71CwpFMmm2ELTPmfiM1cD0zHSWYC8aJYV3pIN0ETs2C h+QbxHN/B9OfHexaJFV2Vbg8y8C2gG+LbI7+pCF6LCRa3OdnsFTWktNigy0F5ZHrDCp9UNc NCBHhirAznsTWtfq7mLToH9XRq8VuQc6hpY4ziKiCfHGkGPdjXw078zF7CKH7owOGgAS31t Q1db3Yjy8xLnPesr7WE64NML35113ZlDgKcU0j3FMsJV1CCLNTrn74RgXYheAQbvUf68wtw /zZj8+yM89hu+vK1K5sXycW/0XXnnHWtKFUVmL9KiA3GPagk605Mru1NO6m5o3reggZWqpK 7rfey/I8T64DV+DScif7LEJdW+R4xdhIMObRb/fltjuG5EPHr7bSFxx85jzMiwYr9klT7fR IoK7YSUPtPeVWGk9HIHWKrI0NgGxkq5w3ECjuNjNXJlT4QMuCEdrlnYiG2hXQQX8gLrLldc nYfrFc5iOcKQbYi/zS+FR/iEcKh0x8HowjbvhazYumeuTaYKFqJlhsmRtP7q/HDiBsujgWZ dt8tshEI2+sDviBt5BmDOtuzV9VIvp26R1i1l4Q1f5ooPtJieCfiks2GVxTC6ut5EWLsZeJ vST5sswg== X-QQ-XMRINFO: Mp0Kj//9VHAxr69bL5MkOOs= X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chaoyi Chen Let's make the ports nodes of cdn_dp in the same style as the other display interface, and match the style of ports's yaml. Signed-off-by: Chaoyi Chen --- (no changes since v1) arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3399-base.dtsi index 9d5f5b083e3c..e340b6df7445 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi @@ -618,7 +618,11 @@ cdn_dp: dp@fec00000 { status =3D "disabled"; ports { - dp_in: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp_in: port@0 { + reg =3D <0>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -632,6 +636,10 @@ dp_in_vopl: endpoint@1 { remote-endpoint =3D <&vopl_out_dp>; }; }; + + dp_out: port@1 { + reg =3D <1>; + }; }; }; -- 2.49.0 From nobody Tue Oct 7 20:20:12 2025 Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C26257AD1; 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charset="utf-8" From: Chaoyi Chen Convert cdn-dp-rockchip.txt to yaml. Add new "port@1" property which represents the CDN DP output to keep the same style as the other display interfaces. This patch also changes the constraints for "phys" and "extcon". For the original binding, only one phy and the corresponding extcon can be specified. In the new binding, one or two phys can be specified. Since the RK3399 has two DP-USB PHYs, specifying one allows output via the corresponding PHY, while specifying two lets the driver choose one PHY for output. This rule also applies to extcon, which provides the cable state for the corresponding PHY. Signed-off-by: Chaoyi Chen Reviewed-by: Krzysztof Kozlowski --- Changes in v5: - Fix constraints on extcon and phys - Add commit about changes to extcon and phys - Add "#sound-dai-cells" to required properties Changes in v4: - Add commit about port@1 node Changes in v3: - Add more description about phy/extcon - Fix some coding style Changes in v2: - Rename binding file name to match compatible - Add more description about grf/phy/extcon - Fix coding style .../display/rockchip/cdn-dp-rockchip.txt | 74 -------- .../rockchip/rockchip,rk3399-cdn-dp.yaml | 168 ++++++++++++++++++ 2 files changed, 168 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-= dp-rockchip.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/rock= chip,rk3399-cdn-dp.yaml diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rock= chip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockch= ip.txt deleted file mode 100644 index 8df7d2e393d6..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip RK3399 specific extensions to the cdn Display Port -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D - -Required properties: -- compatible: must be "rockchip,rk3399-cdn-dp" - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - -- clock-names: from common clock binding: - Required elements: "core-clk" "pclk" "spdif" "grf" - -- resets : a list of phandle + reset specifier pairs -- reset-names : string of reset names - Required elements: "apb", "core", "dptx", "spdif" -- power-domains : power-domain property defined with a phandle - to respective power domain. -- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> -- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: contain a port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - contained 2 endpoints, connecting to the output of vop. - -- phys: from general PHY binding: the phandle for the PHY device. - -- extcon: extcon specifier for the Power Delivery - -- #sound-dai-cells =3D it must be 1 if your system is using 2 DAIs: I2S, S= PDIF - ---------------------------------------------------------------------------= ----- - -Example: - cdn_dp: dp@fec00000 { - compatible =3D "rockchip,rk3399-cdn-dp"; - reg =3D <0x0 0xfec00000 0x0 0x100000>; - interrupts =3D ; - clocks =3D <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names =3D "core-clk", "pclk", "spdif", "grf"; - assigned-clocks =3D <&cru SCLK_DP_CORE>; - assigned-clock-rates =3D <100000000>; - power-domains =3D <&power RK3399_PD_HDCP>; - phys =3D <&tcphy0_dp>, <&tcphy1_dp>; - resets =3D <&cru SRST_DPTX_SPDIF_REC>; - reset-names =3D "spdif"; - extcon =3D <&fusb0>, <&fusb1>; - rockchip,grf =3D <&grf>; - #address-cells =3D <1>; - #size-cells =3D <0>; - #sound-dai-cells =3D <1>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - dp_in: port { - #address-cells =3D <1>; - #size-cells =3D <0>; - dp_in_vopb: endpoint@0 { - reg =3D <0>; - remote-endpoint =3D <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg =3D <1>; - remote-endpoint =3D <&vopl_out_dp>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk= 3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockc= hip,rk3399-cdn-dp.yaml new file mode 100644 index 000000000000..5649e008f14a --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cd= n-dp.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 specific extensions to the CDN Display Port + +maintainers: + - Andy Yan + - Heiko Stuebner + - Sandy Huang + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + items: + - const: rockchip,rk3399-cdn-dp + + reg: + maxItems: 1 + + clocks: + items: + - description: DP core work clock + - description: APB clock + - description: SPDIF interface clock + - description: GRF clock + + clock-names: + items: + - const: core-clk + - const: pclk + - const: spdif + - const: grf + + extcon: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + items: + - description: Extcon device providing the cable state for DP PHY de= vice 0 + - description: Extcon device providing the cable state for DP PHY de= vice 1 + description: + List of phandle to the extcon device providing the cable state for t= he DP PHY. + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + items: + - description: DP output to the DP PHY device 0 + - description: DP output to the DP PHY deivce 1 + description: | + List of phandle to the PHY device for DP output. + RK3399 have two DP-USB PHY, specifying one PHY which want to use, + or specify two PHYs here to let the driver determine which PHY to us= e. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input of the CDN DP + properties: + endpoint@0: + description: Connection to the VOPB + endpoint@1: + description: Connection to the VOPL + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output of the CDN DP + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: spdif + - const: dptx + - const: apb + - const: core + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to GRF register to control HPD. + + "#sound-dai-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - ports + - resets + - reset-names + - rockchip,grf + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + dp@fec00000 { + compatible =3D "rockchip,rk3399-cdn-dp"; + reg =3D <0x0 0xfec00000 0x0 0x100000>; + assigned-clocks =3D <&cru SCLK_DP_CORE>; + assigned-clock-rates =3D <100000000>; + interrupts =3D ; + clocks =3D <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCL= K_SPDIF_REC_DPTX>, + <&cru PCLK_VIO_GRF>; + clock-names =3D "core-clk", "pclk", "spdif", "grf"; + power-domains =3D <&power RK3399_PD_HDCP>; + phys =3D <&tcphy0_dp>, <&tcphy1_dp>; + resets =3D <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX= >, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names =3D "spdif", "dptx", "apb", "core"; + rockchip,grf =3D <&grf>; + #sound-dai-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dp_in_vopb: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&vopl_out_dp>; + }; + }; + + dp_out: port@1 { + reg =3D <1>; + }; + }; + }; + }; -- 2.49.0