From nobody Fri Dec 19 12:49:37 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E034D25D20D; Tue, 20 May 2025 07:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747727159; cv=pass; b=M7SyPoBI8j8RmevtWKKb1i7Vr3bfvHDPaHWmXmRVs6Hi1QB398tZStxGaVoTfeqcq8rzV0kKw/sP3wIIEvM3+byILCcYvm1lzFLB7ASnM0uNAeayAP8GaKyPXJQ6xo5ubZ6eQU5QmuvandqcjM7xVnlb6NypPnBqhXuSXvkWflE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747727159; c=relaxed/simple; bh=pLwzsBe2tnNURu/fP8i0rjxlWvAGKHu4p607gZJ96rQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IvIPezJXXFRKE8CoeqZoOYvK27HHzwH2a2UO2Q4gGLV+oTbMxqCBjjcGkfb3JMChoKjT0No22Iichk9JXk8CcFSXl9G8jNf5vnEF7xCXD+Q/tXMz2SdNj4Kqg7Y3+YpkLbi8azs2ldnTQqP48mN8lEDtyP5/V0OW8+3KoLbmPDs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=jBFKI/hz; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="jBFKI/hz" ARC-Seal: i=1; a=rsa-sha256; t=1747727128; cv=none; d=zohomail.com; s=zohoarc; b=WSeNHzHPd1NxwlZxDBSkbW96NEvPWwFkzeLgZkdr9CY6yfkUuf71S5RAS+kqmZyBZYKINY1bxOFinOSyiDjHv2XwkAuQmdqZjmTHUzontlnVuJhsDx2xN790HDfM513tZ/QNzZONFM39zqZqXhATolz0E5xcGZleSzRf4m6Avj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1747727128; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Db7Skhg/xwreCbQKCCU7E+b0hX+qOQBSw8fvrdik/cI=; b=IfOkEb8BQn96xyjRWtX6UcflIwQWkSSubGnGaJu1OcaIuz8UKZggxDjaiOUayei7Lr3V3yYJj4TT7FdVQqnSxIXlVP20FsA6l2L6C6GdQ1S+mS71dNMwJbT4mvGsdIkVBS+cxNJWq4hUtyrFS0A0PzHb+Crp25SQhqHUrrS6UJU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1747727128; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Db7Skhg/xwreCbQKCCU7E+b0hX+qOQBSw8fvrdik/cI=; b=jBFKI/hzx+1T4I5Qi5MSyMbBZpu4AiUM5omvItr3TwAmSz4io/hMiIpbjJIXacBV XqtMq0m2oGtxMBL+evuldY8U2c4pEytu4lwGqHb4sRA6wrRQvJGJ6fSp12cmBJN8+Zy qc7QtDTM2JMBEaJylxTqIzy+UKUO0uGHUlQTM+B8= Received: by mx.zohomail.com with SMTPS id 1747727127268345.8844111115384; Tue, 20 May 2025 00:45:27 -0700 (PDT) From: Junhui Liu Date: Tue, 20 May 2025 15:44:23 +0800 Subject: [PATCH v4 1/2] dt-bindings: mailbox: add Sophgo CV18XX series SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250520-cv18xx-mbox-v4-1-fd4f1c676d6e@pigmoral.tech> References: <20250520-cv18xx-mbox-v4-0-fd4f1c676d6e@pigmoral.tech> In-Reply-To: <20250520-cv18xx-mbox-v4-0-fd4f1c676d6e@pigmoral.tech> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Yuntao Dai , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747727085; l=2318; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=2oupmZshQu2kbQRqv0KR1mJRGrvbQPR0Vh3LnRnuXuk=; b=a4ZmprI0ntF3PvXBAZh57SBb+S6t43gdFDIF2OOlz0SgEvm9sNsrnfgwXn3EjSKmymWvXO8+h Fkdgm1piFv8AL6kimHknkgJv6vXL6JQ/NUZZKf8LcFC7A1T3S8U2shy X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External From: Yuntao Dai Introduce the mailbox module for CV18XX series SoC, which is responsible for interchanging messages between asymmetric processors. Signed-off-by: Yuntao Dai Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml | 60 ++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailb= ox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..24e126bd3a2025ba0cd28912fe0= 1239b6d758232 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800/SG2000 mailbox controller + +maintainers: + - Yuntao Dai + - Junhui Liu + +description: + Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each + shipping an 8-byte FIFO. Any processor can write to an arbitrary channel + and raise interrupts to receivers. Sending messages to itself is also + supported. + +properties: + compatible: + const: sophgo,cv1800b-mailbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 2 + description: | + <&phandle channel target> + phandle : Label name of mailbox controller + channel : 0-7, Channel index + target : 0-3, Target processor ID + + Sophgo CV1800/SG2000 SoCs include the following processors, numbered= as: + <0> Cortex-A53 (Only available on CV181X/SG200X) + <1> C906B + <2> C906L + <3> 8051 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@1900000 { + compatible =3D "sophgo,cv1800b-mailbox"; + reg =3D <0x01900000 0x1000>; + interrupts =3D <101 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells =3D <2>; + }; --=20 2.49.0 From nobody Fri Dec 19 12:49:37 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F005225E808; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250520-cv18xx-mbox-v4-2-fd4f1c676d6e@pigmoral.tech> References: <20250520-cv18xx-mbox-v4-0-fd4f1c676d6e@pigmoral.tech> In-Reply-To: <20250520-cv18xx-mbox-v4-0-fd4f1c676d6e@pigmoral.tech> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Yuntao Dai , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747727085; l=8014; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=a0cR+fhvbwMEYXPvZAtsXSXc4eeCzygWnJG9I9aL5Ak=; b=R9SPTMpzh7smVi5B4VdXQuujLsleWoLh+ro2ewg04+zA+vmsEWAuEz4mYk7CLWr7ceGptRvo+ UfMIFlel6I+Cg3fjipboHqHzup//iXTPYAxM/0+zY7uz41bjAgc5Ozr X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External From: Yuntao Dai Add mailbox controller driver for CV18XX SoCs, which provides 8 channels and each channel has an 8-byte FIFO. Signed-off-by: Yuntao Dai Signed-off-by: Junhui Liu --- drivers/mailbox/Kconfig | 10 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/cv1800-mailbox.c | 220 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 232 insertions(+) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ed52db272f4d059ff60d608f40e3845411bc63f7..fd3f28d705bc00166028c372d33= 98f2e225aa8a7 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -36,6 +36,16 @@ config ARM_MHU_V3 that provides different means of transports: supported extensions will be discovered and possibly managed at probe-time. =20 +config CV1800_MBOX + tristate "cv1800 mailbox" + depends on ARCH_SOPHGO || COMPILE_TEST + help + Mailbox driver implementation for Sophgo CV18XX SoCs. This driver + can be used to send message between different processors in SoC. Any + processer can write data in a channel, and set co-responding register + to raise interrupt to notice another processor, and it is allowed to + send data to itself. + config EXYNOS_MBOX tristate "Exynos Mailbox" depends on ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 9a1542b55539c673af874c5c37fbb3d438fd05d3..13a3448b327115add5ebb8c4f11= 6e68dedd755cb 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) +=3D arm_mhuv2.o =20 obj-$(CONFIG_ARM_MHU_V3) +=3D arm_mhuv3.o =20 +obj-$(CONFIG_CV1800_MBOX) +=3D cv1800-mailbox.o + obj-$(CONFIG_EXYNOS_MBOX) +=3D exynos-mailbox.o =20 obj-$(CONFIG_IMX_MBOX) +=3D imx-mailbox.o diff --git a/drivers/mailbox/cv1800-mailbox.c b/drivers/mailbox/cv1800-mail= box.c new file mode 100644 index 0000000000000000000000000000000000000000..4761191acf782654c1724df2c9c= c619e1d7c985c --- /dev/null +++ b/drivers/mailbox/cv1800-mailbox.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Yuntao Dai + * Copyright (C) 2025 Junhui Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RECV_CPU 1 + +#define MAILBOX_MAX_CHAN 8 +#define MAILBOX_MSG_LEN 8 + +#define MBOX_EN_REG(cpu) (cpu << 2) +#define MBOX_DONE_REG(cpu) ((cpu << 2) + 2) +#define MBOX_SET_CLR_REG(cpu) (0x10 + (cpu << 4)) +#define MBOX_SET_INT_REG(cpu) (0x18 + (cpu << 4)) +#define MBOX_SET_REG 0x60 + +#define MAILBOX_CONTEXT_OFFSET 0x0400 +#define MAILBOX_CONTEXT_SIZE 0x0040 + +#define MBOX_CONTEXT_BASE_INDEX(base, index) \ + ((u64 __iomem *)(base + MAILBOX_CONTEXT_OFFSET) + index) + +/** + * struct cv1800_mbox_chan_priv - cv1800 mailbox channel private data + * @idx: index of channel + * @cpu: send to which processor + */ +struct cv1800_mbox_chan_priv { + int idx; + int cpu; +}; + +struct cv1800_mbox { + struct mbox_controller mbox; + struct cv1800_mbox_chan_priv priv[MAILBOX_MAX_CHAN]; + struct mbox_chan chans[MAILBOX_MAX_CHAN]; + u64 __iomem *content[MAILBOX_MAX_CHAN]; + void __iomem *mbox_base; + int recvid; +}; + +static irqreturn_t cv1800_mbox_isr(int irq, void *dev_id) +{ + struct cv1800_mbox *mbox =3D (struct cv1800_mbox *)dev_id; + size_t i; + u64 msg; + int ret =3D IRQ_NONE; + + for (i =3D 0; i < MAILBOX_MAX_CHAN; i++) { + if (mbox->content[i] && mbox->chans[i].cl) { + memcpy_fromio(&msg, mbox->content[i], MAILBOX_MSG_LEN); + mbox->content[i] =3D NULL; + mbox_chan_received_data(&mbox->chans[i], (void *)&msg); + ret =3D IRQ_HANDLED; + } + } + + return ret; +} + +static irqreturn_t cv1800_mbox_irq(int irq, void *dev_id) +{ + struct cv1800_mbox *mbox =3D (struct cv1800_mbox *)dev_id; + u8 set, valid; + size_t i; + int ret =3D IRQ_NONE; + + set =3D readb(mbox->mbox_base + MBOX_SET_INT_REG(RECV_CPU)); + + if (!set) + return ret; + + for (i =3D 0; i < MAILBOX_MAX_CHAN; i++) { + valid =3D set & BIT(i); + if (valid) { + mbox->content[i] =3D + MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, i); + writeb(valid, mbox->mbox_base + + MBOX_SET_CLR_REG(RECV_CPU)); + writeb(~valid, mbox->mbox_base + MBOX_EN_REG(RECV_CPU)); + ret =3D IRQ_WAKE_THREAD; + } + } + + return ret; +} + +static int cv1800_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct cv1800_mbox_chan_priv *priv =3D + (struct cv1800_mbox_chan_priv *)chan->con_priv; + struct cv1800_mbox *mbox =3D dev_get_drvdata(chan->mbox->dev); + int idx =3D priv->idx; + int cpu =3D priv->cpu; + u8 en, valid; + + memcpy_toio(MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, idx), + data, MAILBOX_MSG_LEN); + + valid =3D BIT(idx); + writeb(valid, mbox->mbox_base + MBOX_SET_CLR_REG(cpu)); + en =3D readb(mbox->mbox_base + MBOX_EN_REG(cpu)); + writeb(en | valid, mbox->mbox_base + MBOX_EN_REG(cpu)); + writeb(valid, mbox->mbox_base + MBOX_SET_REG); + + return 0; +} + +static bool cv1800_last_tx_done(struct mbox_chan *chan) +{ + struct cv1800_mbox_chan_priv *priv =3D + (struct cv1800_mbox_chan_priv *)chan->con_priv; + struct cv1800_mbox *mbox =3D dev_get_drvdata(chan->mbox->dev); + u8 en; + + en =3D readb(mbox->mbox_base + MBOX_EN_REG(priv->cpu)); + + return !(en & BIT(priv->idx)); +} + +static const struct mbox_chan_ops cv1800_mbox_chan_ops =3D { + .send_data =3D cv1800_mbox_send_data, + .last_tx_done =3D cv1800_last_tx_done, +}; + +static struct mbox_chan *cv1800_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *spec) +{ + struct cv1800_mbox_chan_priv *priv; + + int idx =3D spec->args[0]; + int cpu =3D spec->args[1]; + + if (idx >=3D mbox->num_chans) + return ERR_PTR(-EINVAL); + + priv =3D mbox->chans[idx].con_priv; + priv->cpu =3D cpu; + + return &mbox->chans[idx]; +} + +static const struct of_device_id cv1800_mbox_of_match[] =3D { + { .compatible =3D "sophgo,cv1800b-mailbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, cv1800_mbox_of_match); + +static int cv1800_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cv1800_mbox *mb; + int irq, idx, err; + + mb =3D devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); + if (!mb) + return -ENOMEM; + + mb->mbox_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mb->mbox_base)) + return dev_err_probe(dev, PTR_ERR(mb->mbox_base), + "Failed to map resource\n"); + + mb->mbox.dev =3D dev; + mb->mbox.chans =3D mb->chans; + mb->mbox.txdone_poll =3D true; + mb->mbox.ops =3D &cv1800_mbox_chan_ops; + mb->mbox.num_chans =3D MAILBOX_MAX_CHAN; + mb->mbox.of_xlate =3D cv1800_mbox_xlate; + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + err =3D devm_request_threaded_irq(dev, irq, cv1800_mbox_irq, + cv1800_mbox_isr, IRQF_ONESHOT, + dev_name(&pdev->dev), mb); + if (err < 0) + return dev_err_probe(dev, err, "Failed to register irq\n"); + + for (idx =3D 0; idx < MAILBOX_MAX_CHAN; idx++) { + mb->priv[idx].idx =3D idx; + mb->mbox.chans[idx].con_priv =3D &mb->priv[idx]; + } + + platform_set_drvdata(pdev, mb); + + err =3D devm_mbox_controller_register(dev, &mb->mbox); + if (err) + return dev_err_probe(dev, err, "Failed to register mailbox\n"); + + return 0; +} + +static struct platform_driver cv1800_mbox_driver =3D { + .driver =3D { + .name =3D "cv1800-mbox", + .of_match_table =3D cv1800_mbox_of_match, + }, + .probe =3D cv1800_mbox_probe, +}; + +module_platform_driver(cv1800_mbox_driver); + +MODULE_DESCRIPTION("cv1800 mailbox driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0