From nobody Fri Dec 19 14:25:47 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1131528C5DA; Mon, 19 May 2025 16:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670736; cv=none; b=rf6yxfX6BWquseQ/QjcFk+yMoJn2IvNz9KNmjvGmMeUZJWMUWxxRi+VpOt6lapAl1sITtrfuKIAebyZWG88HM7yPHZGOW46RLKuZT3QAeHSBHXM+sCuQC3g2kmap5hITh1bDgg0OFLxNekqeMWvh8NDSvkJ54O5Uw86Tug5BG4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670736; c=relaxed/simple; bh=utww61uElrub22E1MtpRbKG8U//tpCzjiYPFEae5sdY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=liv+dedAFB5nZlzVial7BcGa6uji/YvZlS50dW4Gn8GC64LqCTYEk0LD23eSytxPQGQ/+ZdgVEJeRUjyjQtcspoMmzVn16QZBEPRwCSjkLjAZ+E6ZFaMkgJ7ZYIDTfcEZGU60ERl6ADlR/IAjTWRvVE76PvcX4eCX/QL1FmrlLk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hchNlW0r; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hchNlW0r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=oo uxVGY9XhCCHgWc5NChF1kCY5VbzSOry8izreFrBRM=; b=hchNlW0rfDP0lWU9+9 o4ruyDnnNyJCfloNN6GehWGo93BY/ouon5u03oY4ElbZU+vMZ7s2uToixTsdEMHG ja3+kDv7DwTSEjIpJs8rdq+tss/4YNJ0CkGTuzD8/nXGarI12BM3/I6aTlhatKqY 6w74SO3vtfEQd9n68VRoCC0hg= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHWSeiVitokozvCQ--.46206S3; Tue, 20 May 2025 00:04:52 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, krzk+dt@kernel.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6 Date: Tue, 20 May 2025 00:04:46 +0800 Message-Id: <20250519160448.209461-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519160448.209461-1-18255117159@163.com> References: <20250519160448.209461-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHWSeiVitokozvCQ--.46206S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7uw4DuF1xZF1Dtw1rGFWkCrg_yoW8XF18pa y8CFyxtrW8Gr17W3ykXw1fAw4jqas3AayjkF98K3srtanxA3ZYyw43KFn8XF1xArWxZFW8 XF4Y9F15Cw1DAr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piyrWcUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOgFSo2grT8qd+AAAsp Content-Type: text/plain; charset="utf-8" Update the device tree binding documentation for PCI to include PCIe Gen5 and Gen6 support in the `max-link-speed` property. The original documentation limited the value to 1~4 (Gen1~Gen4), but the kernel now supports up to Gen6. This change ensures the documentation aligns with the actual code implementation. Signed-off-by: Hans Zhang <18255117159@163.com> --- Documentation/devicetree/bindings/pci/pci.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/= devicetree/bindings/pci/pci.txt index 6a8f2874a24d..5ffd690e3fc7 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -22,8 +22,9 @@ driver implementation may support the following propertie= s: If present this property specifies PCI gen for link capability. Host drivers could add this as a strategy to avoid unnecessary operation for unsupported link speed, for instance, trying to do training for - unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' - for gen2, and '1' for gen1. Any other values are invalid. + unsupported link speed, etc. Must be '6' for gen6, '5' for gen5, '4' f= or + gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are + invalid. - reset-gpios: If present this property specifies PERST# GPIO. Host drivers can parse = the GPIO and apply fundamental reset to endpoints. --=20 2.25.1 From nobody Fri Dec 19 14:25:47 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4002728C5A6; Mon, 19 May 2025 16:05:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670733; cv=none; b=kiThrlYkN0Drm9INR509tGnV/solXDbTO5NulFeKD2elBcJb88nah25sVR0ZR7Ivr8VkYLFTZOuQ2m42nkyuvF3GM1YxQwZrSSujmDu0k0yh9xYA6W9r8ST230bR1XJgnhXArZSdZp9raimRb26Yw37zmSENary5ag4qRnDCfA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670733; c=relaxed/simple; bh=noxDf8ZxNrVndhCt9us9NgISd7alcUElHnhr7+XT1yw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Bxp+kPy9RCuZ7yTdsfBOyG8/2pCi/F5H4IRKnRelbtlstU0OnNuAU3ikmUvKMSxCnnyQfnnCNwVdQXFwKWn13RKtj4oiPPp5PzhVb5Y8+BQswE4jbnpCQNNVumILUPjwpWnudUDBfDAiugYiR940s0Zw+5u47ISE9kN1KB0qHeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=IuNvrJY+; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IuNvrJY+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ay UWXvS06kXSWZnFDAYmWnkUal2jYaVwirTfcPuo9Lk=; b=IuNvrJY+ylitbtsoPL 8BJIrKyfm0zzCfVmp0yke1AewPrb+wmXxrp6w8aLGmwkfw5lbYrz1OL4wLiOak+T 9PxEkq6HNTQorRD6bWeA5KfQaJ6QvdWNJsbKflgj0qgRQUYEdhlTfs7+4/uOzS/A GPJzdywXcnGNRlcV1Op6B4Bsc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHWSeiVitokozvCQ--.46206S4; Tue, 20 May 2025 00:04:52 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, krzk+dt@kernel.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 2/3] dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6 Date: Tue, 20 May 2025 00:04:47 +0800 Message-Id: <20250519160448.209461-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519160448.209461-1-18255117159@163.com> References: <20250519160448.209461-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHWSeiVitokozvCQ--.46206S4 X-Coremail-Antispam: 1Uf129KBjvdXoWruFWUCrWkCw13Jw18CryxuFg_yoWDKFc_uF 1xXa1qvr48JFyYgw4YyF4xt3W5Za12krs7Cw1kJF1qya40yrWq9F98t3s8Ar1fCay3ZF1a 9F93JrWDXrsrGjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRKa9aPUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwRSo2grUi5pvQABsE Content-Type: text/plain; charset="utf-8" Update the PCI Endpoint (EP) device tree binding documentation to include PCIe Gen5 and Gen6 support for the `max-link-speed` property. Similar to the Host Controller binding, the original EP binding limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns the EP binding with the kernel's PCIe 6.0 capabilities. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentat= ion/devicetree/bindings/pci/pci-ep.yaml index f75000e3093d..68aaad70b112 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -33,7 +33,7 @@ properties: =20 max-link-speed: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 1, 2, 3, 4 ] + enum: [ 1, 2, 3, 4, 5, 6] =20 num-lanes: description: maximum number of lanes --=20 2.25.1 From nobody Fri Dec 19 14:25:47 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C63F528C5CA; Mon, 19 May 2025 16:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670736; cv=none; b=ZueXbzwGtHbrxycSGhCja5EUFqnwvwK485KEFJUL/y7emJvtGF+XsMSj/TjeZGoTaX8bedRkHFGm/RwgDsaD6sOX8l+liy7glF1lGqvJG5HXOJV0otscuKbToWXXvhah21mLmOFcL8sb0XlSyproUePvOoSnX6FUcfMqkTk+iyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747670736; c=relaxed/simple; bh=UamZjfyN6na3p67Dkavvu/KY840DiztSpAhsgs34BpE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p/in6YiAkIZk+c2pP6yOhzgjbKpOPn88CotD6uCAZZbxozknTqJC7uVF7DpPrLXD4C2XGXYReiIrxLdM/rxdPxZ1Q0bWurnKkE8OX+fW3yGpMmcU+307udqJ0zw2CCOrTcUJCcuUMhBs7fgcupr7xP010LZFsaThSwmPwchi4tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=XH/baRnp; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="XH/baRnp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ij u8xELG4+fnR3215qcICf+KmnT2kIbCVpbjooreXLw=; b=XH/baRnpZkoCFnUWlI 8PdkaQFL2V/4NL010Kv9mP+kS7L9tWiD9zon/IGFbi2vFhromKdjzouFPXBemLel 6fbPRXYIQjeqk79VmduLST9cOJzdtEaO2yDwYTX7iFD+Ay+S2STALDoC1QQLSOw6 4c02GN5P1jtwdXWGlpED4V3ms= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHWSeiVitokozvCQ--.46206S5; Tue, 20 May 2025 00:04:53 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, krzk+dt@kernel.org, manivannan.sadhasivam@linaro.org, conor+dt@kernel.org Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6 Date: Tue, 20 May 2025 00:04:48 +0800 Message-Id: <20250519160448.209461-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519160448.209461-1-18255117159@163.com> References: <20250519160448.209461-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHWSeiVitokozvCQ--.46206S5 X-Coremail-Antispam: 1Uf129KBjvdXoWrtw43uFWDZw4fKFyUGrWDXFb_yoWfAwbE9F 17XrWfGr4Fkry5Gw1YyrWavrn0v34rW3WUXFyFy3WfAa4UuFyDZFnxuF45Za93A3W3JF1U GFyDGr1UKr1DKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRifOzJUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhhSo2grT8qeFwAAsc Content-Type: text/plain; charset="utf-8" The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4), but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support. This patch updates the validation in `of_pci_get_max_link_speed` to allow values up to 6, ensuring compatibility with newer PCIe generations. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/of.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index ab7a8252bf41..379d90913937 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node) u32 max_link_speed; =20 if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || - max_link_speed =3D=3D 0 || max_link_speed > 4) + max_link_speed =3D=3D 0 || max_link_speed > 6) return -EINVAL; =20 return max_link_speed; --=20 2.25.1