From nobody Fri Dec 19 15:50:30 2025 Received: from smtpcmd03117.aruba.it (smtpcmd03117.aruba.it [62.149.158.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 133751C700D for ; Mon, 19 May 2025 13:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.158.117 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747660333; cv=none; b=EEmN8lhDoaVa966yt22QeYNwMgmmguUVQyoIt+QBvPuwhXXIckLnRJh/3mYGyR2n4+Bz2tMjhj3WuVILnGZf5b8zVBAMQul+6seksVmNDY/kFrw/rN3KgNRSZoD299uCZtxWXvTjSddJmuWDFBGSpauqm9/WyWHKL7ikIodeVgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747660333; c=relaxed/simple; bh=STOexT3aeaNgS0jX6aWr+6om6VU5pRTy84ucbTxf4PI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J4tFxaQhOGChGIJsssndI+oW6fVa0mKIt2WJF5XEIPDHXexc75v0CAiD3ZCSBRjcxVJ6ebwXR/1a7YtOFJpJfjT9BEeYOTA0q1/mEel9BpeUKu+axSNf+QCnw5l/5R5y5JOSuTNi8UD5yUKCsgxR2WhY6YHm2M6AbRBKmUuO44w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=enneenne.com; spf=pass smtp.mailfrom=enneenne.com; dkim=temperror (0-bit key) header.d=aruba.it header.i=@aruba.it header.b=H06pDR4w; arc=none smtp.client-ip=62.149.158.117 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=enneenne.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=enneenne.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=aruba.it header.i=@aruba.it header.b="H06pDR4w" Received: from polimar.homenet.telecomitalia.it ([79.0.204.227]) by Aruba SMTP with ESMTPSA id H0EluBSummHkSH0Emu8qz3; Mon, 19 May 2025 15:09:00 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1747660140; bh=STOexT3aeaNgS0jX6aWr+6om6VU5pRTy84ucbTxf4PI=; h=From:To:Subject:Date:MIME-Version; b=H06pDR4wPPLRP/LbUc9Rjv+rNc5evEgU35POt+QJuUbmqsIDjqxi4fTngG3EokHU4 2WOg/3CnRJhFjUknjMlPgz3yqWQ0DfUp5+ouRzKCsDwOhY6pIcC3JjR44fU/OZpWrx HykwWtx1gxrDlzgSHgGnO2i1oDc8XwZ5hMYVLqpUKf+fYKR6zs/9UA/TEsC9/SCX61 cMsPgyDK7FqpK6jPZwdoRo3ftufm7ibPlHQxLdh+T++Y6nbNLqXnZ6FTd/ch/ugy/Z yjAmCxYrbd84hEDvKkgfBcZx+Z1ls3Sra9rB+sdkXKJ1P7eqIKDVqwRJsGv5KbJWAy iw0IG008k9riQ== From: Rodolfo Giometti To: linux-kernel@vger.kernel.org Cc: Maxime Coquelin , Alexandre Torgue , Eric Fourmont , Yann GAUTIER , Rodolfo Giometti Subject: [V1 1/2] arm stm32mp131.dtsi: add "encoding_mode" nvmem definition Date: Mon, 19 May 2025 13:08:58 +0000 Message-Id: <20250519130859.3389704-2-giometti@enneenne.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519130859.3389704-1-giometti@enneenne.com> References: <20250519130859.3389704-1-giometti@enneenne.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfMh/Fpk+pwBEkLTfzO4y4TYc9xaEfBudgO7tsUE0KkBxzid2iibSSSWCC/vQ7vakhsCbCw+9PNUaoJaD6+xay9nl/QAcuPtszO9sB8jayo0P0p87WSTR d2/i5HCoS0x0p1B/U8E0V+iM0d4LSTMNH9DzIU6nCW6UBgz/vmCRahhK3F0mtCQpOtKbpCLy1eR1kelAN7f14CjeOvZfbTTJqmVVECrwwCcAml4KbKNund29 FWQqVHeOAQtXh7cIH8c9ikgF/opK/9qRMZL5BQqGlnHFbSqbC/H2dsyuu9yumnoEyq9J46SJ6XwcG/hXA1Vpw5KCI+S+qD3MFLqUMqlow4DIFC/e6luDWPgW LHq2P9DgotXjP5V5wZFPyKbWtZkLYp92EMa/vYC/tfpa6N1wAFEywtLJfNvwwiVxmFmafiGF Content-Type: text/plain; charset="utf-8" This patch adds the definition for the nvmem location "encoding_mode" related to the "cpu0" node. Signed-off-by: Rodolfo Giometti --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index e555717c0048..52bf497e26bb 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -24,6 +24,9 @@ cpu0: cpu@0 { clocks =3D <&scmi_perf 0>; clock-names =3D "cpu"; #cooling-cells =3D <2>; + + nvmem-cells =3D <&encoding_mode_otp>; + nvmem-cell-names =3D "encoding_mode"; }; }; =20 @@ -1167,6 +1170,10 @@ part_number_otp: part-number-otp@4 { reg =3D <0x4 0x2>; bits =3D <0 12>; }; + encoding_mode_otp: encoding-mode-otp@4 { + reg =3D <0x0 0x1>; + bits =3D <0 9>; + }; vrefint: vrefin-cal@52 { reg =3D <0x52 0x2>; }; --=20 2.25.1 From nobody Fri Dec 19 15:50:30 2025 Received: from smtpcmd03117.aruba.it (smtpcmd03117.aruba.it [62.149.158.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA46F27978B for ; Mon, 19 May 2025 13:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.158.117 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747660333; cv=none; b=qEq1eoJnWhoKv3AzVtSi1Xj7vaTLARtrks2OxU82U0kE7KYcv+8ipMhHmDPlTn8lD9cFXJ+fN2E1G2ij2dbQKFpAUSoXioVkilJBSnzCwI9oQW9MDs/8o2d642iHQcFwDQOg42jOy+D7rtwBIVuwbDvlXXFGqTPVA7f14/ZbKHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747660333; c=relaxed/simple; bh=lsLYg3RnmictSZ5P2uA+SU1RQfsDxhSdm2R2EC3CQcQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DN0w3ZnA7VPAWPqMd8Ej5NBc7JrFi/R0s3SAOl0xFzf6UcR4spZxEt8IMKTxGMvDlfD3qyx4c3tYHskR9mKUv2ayM2Nqm3LT+osfFxSMjrIXDoGJFQZ+4yOjADApxMPX1yVt3k7QFpRlgn43I6pJutJuObEgAYJjEY0GHTI6wJ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=enneenne.com; spf=pass smtp.mailfrom=enneenne.com; dkim=temperror (0-bit key) header.d=aruba.it header.i=@aruba.it header.b=GPAGyXmi; arc=none smtp.client-ip=62.149.158.117 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=enneenne.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=enneenne.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=aruba.it header.i=@aruba.it header.b="GPAGyXmi" Received: from polimar.homenet.telecomitalia.it ([79.0.204.227]) by Aruba SMTP with ESMTPSA id H0EluBSummHkSH0Emu8qzG; Mon, 19 May 2025 15:09:00 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1747660140; bh=lsLYg3RnmictSZ5P2uA+SU1RQfsDxhSdm2R2EC3CQcQ=; h=From:To:Subject:Date:MIME-Version; b=GPAGyXmidFOQjXFy1ac7G3g65mzMWomIVmeDmRqR2mlwLKFa86FP3ou4K5f850JKw RZkGQtPzfV3E1nLdzGO+z8eOlMML10tHLd82RcgZB/NuXfDCMoUCTJrzTRQ9BlRgBj 6/EQPQvUZZZlhh5QwEhPLDNyBRYtSTJj4opbhZA1KirtzEQ1vSzzZxqZ3ONC6Cd/De UAWR6eHFfOIX2Z4rJlbBxxft5aKaLrPFeyBujMc7JkD3xRWQ0pRZr2N7OcWbim72Jc NGuKDEFKtAc9rTro/rXtgdMXjYS7OOtGaSvFesfcuhafhVZUsa7mTH0y5S2j7fZ6Me EPWbjPwoq4wpw== From: Rodolfo Giometti To: linux-kernel@vger.kernel.org Cc: Maxime Coquelin , Alexandre Torgue , Eric Fourmont , Yann GAUTIER , Rodolfo Giometti Subject: [V1 2/2] drivers soc: add support for ST stm32mp13xx family Date: Mon, 19 May 2025 13:08:59 +0000 Message-Id: <20250519130859.3389704-3-giometti@enneenne.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519130859.3389704-1-giometti@enneenne.com> References: <20250519130859.3389704-1-giometti@enneenne.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfMh/Fpk+pwBEkLTfzO4y4TYc9xaEfBudgO7tsUE0KkBxzid2iibSSSWCC/vQ7vakhsCbCw+9PNUaoJaD6+xay9nl/QAcuPtszO9sB8jayo0P0p87WSTR d2/i5HCoS0x0p1B/U8E0V+iM0d4LSTMNH9DzIU6nCW6UBgz/vmCRahhK3F0mtCQpOtKbpCLy1eR1kelAN7f14CjeOvZfbTTJqmVVECrwwCcAml4KbKNund29 FWQqVHeOAQtXh7cIH8c9ikgF/opK/9qRMZL5BQqGlnHFbSqbC/H2dsyuu9yumnoEyq9J46SJ6XwcG/hXA1Vpw5KCI+S+qD3MFLqUMqlow4DIFC/e6luDWPgW LHq2P9DgotXjP5V5wZFPyKbWtZkLYp92EMa/vYC/tfpa6N1wAFEywtLJfNvwwiVxmFmafiGF Content-Type: text/plain; charset="utf-8" This patch adds SoC support for the ST stm32mp13xx family. It also adds the special attribute "secure" which returns the CPU's secure mode status. Signed-off-by: Rodolfo Giometti --- drivers/soc/st/Makefile | 1 + drivers/soc/st/soc-stm32mp13.c | 253 +++++++++++++++++++++++++++++++++ 2 files changed, 254 insertions(+) create mode 100644 drivers/soc/st/soc-stm32mp13.c diff --git a/drivers/soc/st/Makefile b/drivers/soc/st/Makefile index 6c71607f6c89..c84bf510928d 100644 --- a/drivers/soc/st/Makefile +++ b/drivers/soc/st/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_STM32_PM_DOMAINS) +=3D stm32_pm_domain.o obj-$(CONFIG_STM32_RISAB) +=3D stm32_risab.o obj-$(CONFIG_STM32_RISAF) +=3D stm32_risaf.o +obj-$(CONFIG_MACH_STM32MP13) +=3D soc-stm32mp13.o diff --git a/drivers/soc/st/soc-stm32mp13.c b/drivers/soc/st/soc-stm32mp13.c new file mode 100644 index 000000000000..cf45dbeb926a --- /dev/null +++ b/drivers/soc/st/soc-stm32mp13.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 Rodolfo Giometti + */ + +#include +#include +#include +#include +#include +#include + +#define STM32MP131A 0x6C9 +#define STM32MP131C 0x6C8 +#define STM32MP131D 0xEC9 +#define STM32MP131F 0xEC8 +#define STM32MP133A 0x0C1 +#define STM32MP133C 0x0C0 +#define STM32MP133D 0x8C1 +#define STM32MP133F 0x8C0 +#define STM32MP135A 0x001 +#define STM32MP135C 0x000 +#define STM32MP135D 0x801 +#define STM32MP135F 0x800 + +#define BSEC_RPN 0x204 +#define BSEC_UID 0x234 +#define SYSCFG_IDC 0x380 + +/* + * SoC attributes + */ + +static ssize_t +secure_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + u16 val; + char *str; + int ret; + struct device *cpu_dev; + + cpu_dev =3D get_cpu_device(0); + if (!cpu_dev) { + dev_err(dev, "failed to get cpu0 device\n"); + return -ENODEV; + } + ret =3D nvmem_cell_read_u16(cpu_dev, "encoding_mode", &val); + if (ret) + return ret; + + switch (val) { + case 0b0000010111: + str =3D "open"; + break; + case 0b0000111111: + str =3D "closed"; + break; + case 0b0101111111: + str =3D "closed boundary-scan-disabled]"; + break; + case 0b1111111111: + str =3D "closed JTAG-disabled"; + break; + default: + str =3D "unknown"; + } + + return sprintf(buf, "%s\n", str); +} +static DEVICE_ATTR_RO(secure); + +static struct attribute *stm32mp13_soc_attrs[] =3D { + &dev_attr_secure.attr, + NULL +}; +ATTRIBUTE_GROUPS(stm32mp13_soc); + +/* + * Driver init functions + */ + +static int __init stm32mp13_soc_get_rpn_uid(u32 *rpn, u32 uid[3]) +{ + struct device_node *np; + void __iomem *regs; + static const struct of_device_id devids[] =3D { + { .compatible =3D "st,stm32mp13-bsec" }, + { }, + }; + + np =3D of_find_matching_node(NULL, devids); + if (!np) + return -ENODEV; + + regs =3D of_iomap(np, 0); + of_node_put(np); + + if (!regs) { + pr_warn("Could not map BSEC iomem range"); + return -ENXIO; + } + + *rpn =3D readl(regs + BSEC_RPN) & 0x0fff; + uid[0] =3D readl(regs + BSEC_UID + 0); + uid[1] =3D readl(regs + BSEC_UID + 4); + uid[2] =3D readl(regs + BSEC_UID + 8); + + iounmap(regs); + + return 0; +} + +static int __init stm32mp13_soc_get_idc(u32 *idc) +{ + struct device_node *np; + void __iomem *regs; + static const struct of_device_id devids[] =3D { + { .compatible =3D "st,stm32mp157-syscfg" }, + { }, + }; + + np =3D of_find_matching_node(NULL, devids); + if (!np) + return -ENODEV; + + regs =3D of_iomap(np, 0); + of_node_put(np); + + if (!regs) { + pr_warn("Could not map BSEC iomem range"); + return -ENXIO; + } + + *idc =3D readl(regs + SYSCFG_IDC); + + iounmap(regs); + + return 0; +} + +static int __init stm32mp13_soc_device_init(void) +{ + u32 part_number, rev, chipid[3]; + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; + struct device_node *root; + const char *soc_id; + int ret; + + soc_dev_attr =3D kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + soc_dev_attr->family =3D "STM STM32MP13xx"; + + root =3D of_find_node_by_path("/"); + ret =3D of_property_read_string(root, "model", &soc_dev_attr->machine); + if (ret) + of_property_read_string_index(root, "compatible", 0, + &soc_dev_attr->machine); + of_node_put(root); + if (ret) + goto free_soc; + + /* Get chip info */ + ret =3D stm32mp13_soc_get_rpn_uid(&part_number, chipid); + if (ret) { + pr_err("failed to get chip part number: %d\n", ret); + goto free_soc; + } + switch (part_number) { + case STM32MP131A: + soc_id =3D "131a"; + break; + case STM32MP131C: + soc_id =3D "131c"; + break; + case STM32MP131D: + soc_id =3D "131d"; + break; + case STM32MP131F: + soc_id =3D "131f"; + break; + case STM32MP133A: + soc_id =3D "133a"; + break; + case STM32MP133C: + soc_id =3D "133c"; + break; + case STM32MP133D: + soc_id =3D "133d"; + break; + case STM32MP133F: + soc_id =3D "133f"; + break; + case STM32MP135A: + soc_id =3D "135a"; + break; + case STM32MP135C: + soc_id =3D "135c"; + break; + case STM32MP135D: + soc_id =3D "135d"; + break; + case STM32MP135F: + soc_id =3D "135f"; + break; + default: + soc_id =3D "unknown"; + } + soc_dev_attr->soc_id =3D soc_id; + + ret =3D stm32mp13_soc_get_idc(&rev); + if (ret) + goto free_soc; + soc_dev_attr->revision =3D kasprintf(GFP_KERNEL, "%X", rev >> 16); + if (!soc_dev_attr->revision) { + ret =3D -ENOMEM; + goto free_soc; + } + + soc_dev_attr->serial_number =3D kasprintf(GFP_KERNEL, "%08X%08X%08X", + chipid[0], chipid[1], chipid[2]); + if (!soc_dev_attr->serial_number) { + ret =3D -ENOMEM; + goto free_rev; + } + + /* Add custom attributes group */ + soc_dev_attr->custom_attr_group =3D stm32mp13_soc_groups[0]; + + /* Register the SOC device */ + soc_dev =3D soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + ret =3D PTR_ERR(soc_dev); + goto free_serial_number; + } + + pr_info("SoC Machine: %s\n", soc_dev_attr->machine); + pr_info("SoC family: %s\n", soc_dev_attr->family); + pr_info("SoC ID: %s, Revision: %s\n", + soc_dev_attr->soc_id, soc_dev_attr->revision); + + return 0; + +free_serial_number: + kfree(soc_dev_attr->serial_number); +free_rev: + kfree(soc_dev_attr->revision); +free_soc: + kfree(soc_dev_attr); + return ret; +} +device_initcall(stm32mp13_soc_device_init); --=20 2.25.1