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Mon, 19 May 2025 02:09:34 -0700 From: Wayne Chang To: , , , , , CC: , , , Subject: [PATCH V2 1/2] phy: tegra: xusb: Decouple CYA_TRK_CODE_UPDATE_ON_IDLE from trk_hw_mode Date: Mon, 19 May 2025 17:09:28 +0800 Message-ID: <20250519090929.3132456-2-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250519090929.3132456-1-waynec@nvidia.com> References: <20250519090929.3132456-1-waynec@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|IA1PR12MB6433:EE_ X-MS-Office365-Filtering-Correlation-Id: eb8ce671-e4c9-404f-08a9-08dd96b4eb87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TchmRSUM0SUWzYjx0c8ygi+ztBTsQVpz00mLL7qrJRYCqEmuFIAmcJ7BFAiT?= =?us-ascii?Q?USSx17JIrRZw0t9IRoIs9/uhcWz6SAzJJl2MKk/YF7xB/Xh/qj5Q5TGWEAO3?= =?us-ascii?Q?vtk+mP6W7BmJ+MOfk6M7efqB42zsKJIHw/ojpVuuYtjvoWfeGoroNwfxnhM9?= =?us-ascii?Q?CnevhHBs99IfjSX47CrSuL8okkbWmFZVl+b2UijFfVwyLJbKEA/mq2yiVAhZ?= =?us-ascii?Q?ODY0/jMwFRBFAdgapwFw0QeX5jQBBVRoXApKVwDnL2Uy0nOeeyCPpeBG/6wz?= =?us-ascii?Q?BAv1pa7O6P1x0zEZr5aDyLNTTMYUyeKvhrRUZK5jY5eEM54tsOwpxC5/1Q16?= =?us-ascii?Q?jyIwQVReaFvwv6ko6es4RL0NWOF3MIBF9WE53GIfdRcMKMr+PTK2Pj2DkDPm?= =?us-ascii?Q?M0SAD3+GktE7x4oKYrerYP4XF4z47YcMg7wXnFDS0yn/qJu71zS18cESon4X?= =?us-ascii?Q?iErSX9zf3O9wwm4Tps3yTfGrudsGuPEB+FJsSY/Hfq4nVRVs9dulY58ghuST?= =?us-ascii?Q?21+b3N4+i3wCrd+EhNK0aNGWY0uuWQqXr/s8D5zFhH1malMoIe/nw/2RHCcv?= =?us-ascii?Q?UOZxxlstLHcR5duQiUENehvzt1QdPm9TMfDSYj9fDpAesq21Q4gIaGsVVkEn?= =?us-ascii?Q?2llhIQGuRuMLt0LkMhnjqS4vA7LubdHp+NP8WyA1C1SlrlL3n/xvR7AguJ4J?= =?us-ascii?Q?9RycN81roRJFd81QAquAEwfcMP5coQ9rXCcce9dLfBr4L/8snIVs9cxj6tNX?= =?us-ascii?Q?aDegr3tUsCEq6LLDXX7VOae++QeqaLMQDseCxgOKBjZhAJDs4k4aW6tz5GdA?= =?us-ascii?Q?0EeEvM98UL9Vmkl1N9YTspOaJ8CS7FyrWKmTGZtDg1ePVSNqsXv0qHkijshS?= =?us-ascii?Q?KVyBajLFos6ohS4OvMvt5G6hEweRdvnzxVmg0vXpKwRqtnugY2XVTG9X9tAb?= =?us-ascii?Q?CCAFa0vDQT3m9kk6tRtf3RpWaOcmdLbymX6a3Trm5ybHXkubWqq0tM4Yy0VU?= =?us-ascii?Q?7xsOYT3u4QxYH0lo0LJQxz/JoCdQU8brjQOcJh7ySPuKi6lKS0GGNqH6QBau?= =?us-ascii?Q?RFIVc1t+4WOLGBj6UFeu17ntul7FgCAiYFzQtDlsoHwRRcpRsXrV+xrF3QlU?= =?us-ascii?Q?a8OGOZEcV9VmDG3wybVe8vzAh7ZL+hDtUNSDXM1kDNvtuWiFTc9wzwZUANar?= =?us-ascii?Q?OUdrd6qwgd20PVAMv+Cvargl/uy9XFBS0wnxT/BbmosxchDDTr/eDJtW3fyN?= =?us-ascii?Q?gANiGLzgtbA9rcH2tAkWOpSk3uP5bP02nSge4Ux5XsVJxNlkIh6Mnxib4qF2?= =?us-ascii?Q?pTLamvgrlL7E1/gl6Bi0pDjBQw2170rxDB0fnCwCerzJPBm6Zr+9iL3JzlJ/?= =?us-ascii?Q?6r9+olryGKGvEoZ7nfWJbiVwyKDhyE2tRhcjZG2HpKUareVB5MN5y1jWBMtL?= =?us-ascii?Q?EbVeK6lUnoiEhqlzOJxYBy4Ao0ExCdNJi7Qgjo5TXpy0VGUSWyYqgKpzlsoJ?= =?us-ascii?Q?CiBc3Zv6Yvmtu8YDkdLeQayy4JUG5Eqb8605?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2025 09:09:54.4951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb8ce671-e4c9-404f-08a9-08dd96b4eb87 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6433 Content-Type: text/plain; charset="utf-8" The logic that drives the pad calibration values resides in the controller reset domain and so the calibration values are only being captured when the controller is out of reset. However, by clearing the CYA_TRK_CODE_UPDATE_ON_IDLE bit, the calibration values can be set while the controller is in reset. The CYA_TRK_CODE_UPDATE_ON_IDLE bit was previously cleared based on the trk_hw_mode flag, but this dependency is not necessary. Instead, introduce a new flag, trk_update_on_idle, to independently control this bit. Fixes: d8163a32ca95 ("phy: tegra: xusb: Add Tegra234 support") Cc: stable@vger.kernel.org Signed-off-by: Wayne Chang --- V1->V2: Rebased the commit drivers/phy/tegra/xusb-tegra186.c | 14 ++++++++------ drivers/phy/tegra/xusb.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-teg= ra186.c index 23a23f2d64e5..683692f0ec3c 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -648,14 +648,15 @@ static void tegra186_utmi_bias_pad_power_on(struct te= gra_xusb_padctl *padctl) udelay(100); } =20 - if (padctl->soc->trk_hw_mode) { - value =3D padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); - value |=3D USB2_TRK_HW_MODE; + value =3D padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + if (padctl->soc->trk_update_on_idle) value &=3D ~CYA_TRK_CODE_UPDATE_ON_IDLE; - padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); - } else { + if (padctl->soc->trk_hw_mode) + value |=3D USB2_TRK_HW_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + + if (!padctl->soc->trk_hw_mode) clk_disable_unprepare(priv->usb2_trk_clk); - } } =20 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *pad= ctl) @@ -1711,6 +1712,7 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padc= tl_soc =3D { .supports_gen2 =3D true, .poll_trk_completed =3D true, .trk_hw_mode =3D true, + .trk_update_on_idle =3D true, .supports_lp_cfg_en =3D true, }; EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 6e45d194c689..d2b5f9565132 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -434,6 +434,7 @@ struct tegra_xusb_padctl_soc { bool need_fake_usb3_port; bool poll_trk_completed; bool trk_hw_mode; + bool trk_update_on_idle; bool supports_lp_cfg_en; }; =20 --=20 2.25.1