From nobody Fri Dec 19 15:47:51 2025 Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C86E1E1C3A; Mon, 19 May 2025 07:55:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747641362; cv=none; b=BqcnYVXBHpZRnsM5VCRstzM6OO9OpZo/3R5wLrcWX5uRJ0UkStncqoa8B7JmBIxHSaV9X9+z8FqJ9Ck7nK+vf7hzlcxF0lCZL60CmONnace/UDHc4+rgZGVknuATkC9RVapoJp1h5PztC9xIGfgch0+iV95L2xfeP+S756ZYUds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747641362; c=relaxed/simple; bh=w2zdlmvSlZ3GigXquGzHuzC+WZlwaeRcdQGUvUyy/9A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r7xIOgGHSMBAvWdzpx2vPZd9nuAgwoYPNAXqq25syjNnrZKVpy3/mldUCA4CQTTpwrfqX9cJnC12JzaBwFg1ivknrm2wLp40yZcanRxNOlyqzm25Y+7QI/8Qu9edHA+w83TErnkPqAaIPpNEVJud9mXo9vXbNy7JedniaoccqP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chainsx.cn; spf=pass smtp.mailfrom=chainsx.cn; arc=none smtp.client-ip=54.204.34.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chainsx.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chainsx.cn X-QQ-mid: esmtpsz16t1747641306te62f64f6 X-QQ-Originating-IP: KUSRsfj2034q0KpgVunyHgpIxpYlaY5rKNO7LaI+oTw= Received: from localhost.localdomain ( [182.245.65.132]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 19 May 2025 15:55:04 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 7114426328788078209 EX-QQ-RecipientCnt: 16 From: Hsun Lai To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: i@chainsx.cn, heiko@sntech.de, andrew@lunn.ch, inindev@gmail.com, quentin.schulz@cherry.de, jonas@kwiboo.se, sfr@canb.auug.org.au, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski@linaro.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 1/2] dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC Date: Mon, 19 May 2025 15:54:31 +0800 Message-Id: <20250519075432.2239713-2-i@chainsx.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250519075432.2239713-1-i@chainsx.cn> References: <20250519075432.2239713-1-i@chainsx.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:chainsx.cn:qybglogicsvrsz:qybglogicsvrsz3a-0 X-QQ-XMAILINFO: NkHKfw09D6j8EPyvTXWfHCJ17T4RuvGSQB6XV42nnTaXO2/1MLd+6+1O emkHoILwa4rMHByVq5cB1N5kE/AFcpCgkimO0u68obBr0q/nW5D71bOX9Gs5J7rHckcXiQH nY22W0GHgDcBPXHlnOforDghwmRGf54uwEODcrCk7mWvZldseBbOr8hQNOwafkrLCSmw7Ml vKU/KzdMEaHI+OiqVQFbBhqNLMULTOXMnKL3HLgYZ+y3dW2N0jRfNNLVbo/8nL/Ub/tduxj JLeHYxkojXIGKtZA7OzP0WqXKyE3RrhxAzAUcstkq6XPuqoTW7bE2PFUIpNm8tdXZJ9mbby GLROwtF3XE8krHHKgZUun4V2Oc5etxGxCaXy1+LPIn5nYxN8JOw9ymx4tKHOAPsyX2TogHu ZO6u2/wisW5Efs3tas9dY8i2mnRJZTF9XnKuR8+Zb+dT8M/SjDMepa4KTHZyh2oJaTwsvPN 4yFQRwCPoccE9ONSgJ0ExWRTwcypJ2nL9xYN6z/dnjE1veSTsYqZz3ns6Z9zzgZwix0XFkS PlCCg5X8o4QdCAvX4WJTt1Cc/NRQmlM7x76E4P8mUhB8zzuIt9QJaw7ZWsUivoxI38S7QC+ OKP+mO3k6nFDt6tT9T7teo6NoJHax3mdeMwgNfRML44z2qbejg7EGEPIEcJLBa5Sv4xamRy vByrxPf/44+FyC12kR42Phxv/MAZ7tHDE91ffUZvQDb3KMxosF4tvxnaCQ7lh/MuJVHsy9Y 43uG9HlX3Toa4uBOKiNLaCb0TyonC6iozoZAbKAXd62LvD1j9X5FZ9nlEJFtt5j7MJHX9tH WpMjmgDTpzC6G5FnWOCNN3WZOAe97p+9a+QBy+dZh+LGVYg3a75/FMe+j/kIKkrQCOpOQ65 Ah5D+Uj+mlnW3oluZ2ATSvCNwq40+/AJqXFxTtEQgV9X04RSzCFhBBE9EgZOJAkC5QNd/7M 6tvsIUoxSsEnV90aUaXfq+7phdVgO2FfhXZb9OQFoJZCam6thRvm9cAb9l2Iq3Ey4wzsULJ vC/lBSBCjmjhk7BnwK X-QQ-XMRINFO: OWPUhxQsoeAVDbp3OJHYyFg= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" This documents Firefly ROC-RK3588S-PC which is a SBC based on RK3588S SoC. Link: https://wiki.t-firefly.com/en/Station-M3/index.html Signed-off-by: Hsun Lai Reviewed-by: Quentin Schulz --- (no changes since v1) Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 115c3ca43..701d68aca 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -258,6 +258,11 @@ properties: - const: firefly,rk3566-roc-pc - const: rockchip,rk3566 =20 + - description: Firefly Station M3 + items: + - const: firefly,rk3588s-roc-pc + - const: rockchip,rk3588s + - description: Firefly Station P2 items: - const: firefly,rk3568-roc-pc --=20 2.34.1 From nobody Fri Dec 19 15:47:51 2025 Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18B5C257ACF; Mon, 19 May 2025 07:55:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747641364; cv=none; b=Eb1NgOJQAxF3yjSOX9OpbDHD3Wk04pGh3m0TFWW8o1+7y+5GOuIcgGGYpUxwN2V4hohv65Gvug6QQ/4J6MXHBRaVBMtHNc/6KE6czU4w5Dh/PFXSokGNSaU/gL14OQL8u1aUYhabBHyp1296Kvp2fsQUAs06D7eMqcXMAzqfIMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747641364; c=relaxed/simple; bh=HtDEka9zO2/rcsVY1Epk/GE8h5/MjJIMvd3d6zaiOHw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HHlqS+e2N8DYNqH1PCuBgA793QfWRY+/XXuYxmrk/hppuunPCbIZy2cah8ropC6Ro+kdhzjSQIQBsA6RQZ9RwCqmOooIIvt9Xlleu6/e8qcqnQM+7qGfo5ofKKgeN6eNwZi9Tutj0vCt6g96nLIpG1lOS6Qot7vcwsTp5K0Cgls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chainsx.cn; spf=pass smtp.mailfrom=chainsx.cn; arc=none smtp.client-ip=15.184.224.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chainsx.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chainsx.cn X-QQ-mid: esmtpsz16t1747641309ta842caa7 X-QQ-Originating-IP: FbTDM1j7PR343IHrSMO0ESclHpSvBXWaQcb9GoRUD88= Received: from localhost.localdomain ( [182.245.65.132]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 19 May 2025 15:55:07 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8137395762992140986 EX-QQ-RecipientCnt: 16 From: Hsun Lai To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: i@chainsx.cn, heiko@sntech.de, andrew@lunn.ch, inindev@gmail.com, quentin.schulz@cherry.de, jonas@kwiboo.se, sfr@canb.auug.org.au, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski@linaro.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 2/2] arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC Date: Mon, 19 May 2025 15:54:32 +0800 Message-Id: <20250519075432.2239713-3-i@chainsx.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250519075432.2239713-1-i@chainsx.cn> References: <20250519075432.2239713-1-i@chainsx.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:chainsx.cn:qybglogicsvrsz:qybglogicsvrsz3a-0 X-QQ-XMAILINFO: NhvpCzAv3WKA+TqP3g/GvoNBJygTv4o8xjQAe6L5Ia9V5qv8VslyPrE8 s/L4hUPY+w9iKKwYkksYoMYpLP628BfkOwKcIAUlShCzX0q+FVmhGeog6vR08+/oRlEuHxc E9ceiaLs4wGLTrkBKUYE6WP+NwrA0GuMP9SiI3XhWBo6b7cda6ZXw3iD04Js1s4x2tL35D+ qXctY9iga/aIv4BnhIjsAb0KULas5VoIi/9npkkKZE6VJ09dAs4PVTnxUQKfZxoktKxoMtI tZGafyu2J+U6ZUBAn0y4zHTFElvS42gT1Kc84xq4jSUgVbsv0a57CbbyF17S4J185yPEuQT lZxqgF/k8i5s3/RdmMSOFk+o64MUTjP5hdK4GRyHjA1B4YOd2ApiHtNfVzx5SsLTh9EbOMf stDtXFY83k/PUXjECqBwXW0DuBFmwaIZwZsfUBziMrgw/nvrcYJ2vzmhAZGjOAreZCBgVyQ 6pEI39KDtenZ1cBOs5w+7mi4FfEfhtSKpJnPdHUUAFu2YIOUQM+UQvZJodTMNW1bA353INA 4nMjT6m3ooWaHiRyVYXHabBnFa7//9dTl3xtxxFcpysXhyf5hGZPAMgHTF0Lc1edbfWOuXZ /SysZFNKKUg3VcrjwhW22GO3QklUdIjTNN9HQKJvT2FMCy4o81FvNjm7k0+DtZJ4wwLiVS6 Zr3xhRINOk6yTmah0d76hmxYL+Vh4KOe5ScJ2TRqODkFPoek176QUm/F22kAdvoGOejYyMf E9u8j+zCcXhufPMM4cHprn8nMNad3jO6zJB72f/EHAGyDw3EY5OVuFHLW3mzy/Dwrh6twiJ oHWoYm3HO+68UxnZlsWV/UsfyjMhEQkeIugjpLXytFLfohbsMMGbyp4iqq9iy4K6T8UFtP6 7h1NTLeRdosnFdJkEdUKJC0IHrhwLyk0RqBAP1cBaV3VLE/nfKkhJKs8FuP8LZb9WRnUrJW qZXAH3aseVtdx4sxVjrR4lHbo1SY2ncr/guR+SiSYuStOiQuQwzz99Hd1lWDPMUiGLEbNvt sbrTZclWFXvOtJ4Nl6uqsHYMEUU8kTyyMdmACJvw== X-QQ-XMRINFO: NS+P29fieYNw95Bth2bWPxk= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" The Firefly ROC-RK3588S-PC is a SBC based on the Rockchip RK3588s SoC. Link: https://wiki.t-firefly.com/en/Station-M3/index.html The device contains the following hardware that is tested/working: - 32 or 64GB eMMC - SDMMC card slot - Realtek USB WiFi 5/BT - NVME 2242 socket - 4 or 8GB of RAM - RTL8211 GbE - USB 3.0 port - USB 2.0 port - HDMI port Signed-off-by: Hsun Lai --- Changes in v4: - Update the name of the regulator - Remove the i2s5_8ch node Changes in v3: - Update the name of leds - Add more cpu nodes - Update mdio compatible - Fix the order in the node - Add the default serial port(uart2) Changes in v2: - Fix rgmii delays Changes in v1: - Add support for Firefly ROC-RK3588S-PC arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-roc-pc.dts | 922 ++++++++++++++++++ 2 files changed, 923 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index e63c3f5eb..dd6ae546d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5c.dtb =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/b= oot/dts/rockchip/rk3588s-roc-pc.dts new file mode 100644 index 000000000..be619a3f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model =3D "Firefly Station M3"; + compatible =3D "firefly,rk3588s-roc-pc", "rockchip,rk3588s"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + }; + + analog-sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + simple-audio-card,name =3D "rockchip,es8388"; + simple-audio-card,bitclock-master =3D <&masterdai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&masterdai>; + simple-audio-card,hp-det-gpios =3D <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,pin-switches =3D "Headphones"; + simple-audio-card,routing =3D + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai =3D <&es8388>; + system-clock-frequency =3D <12288000>; + }; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + fan: fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <60 100 140 160 185 220 255>; + fan-supply =3D <&vcc12v_dcin>; + pwms =3D <&pwm11 0 50000 1>; + #cooling-cells =3D <2>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_pins>; + + led-0 { + default-state =3D "on"; + function =3D LED_FUNCTION_POWER; + gpios =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + led-2 { + default-state =3D "off"; + gpios =3D <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: regulator-vcc5v0-usbdcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usbdcin>; + }; + + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie20"; + enable-active-high; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + gpio =3D <&gpio1 RK_PD7 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vbus5v0_typec_pwr_en: regulator-vbus5v0-typec-pwr-en { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&typec5v_pwren>; + regulator-name =3D "vbus5v0_typec_pwr_en"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&hdmi0 { + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2m0_xfer>; + status =3D "okay"; + + usbc0: usb-typec@22 { + compatible =3D "fcs,fusb302"; + reg =3D <0x22>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbc0_int>; + vbus-supply =3D <&vbus5v0_typec_pwr_en>; + + usb_con: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + op-sink-microwatt =3D <1000000>; + power-role =3D "dual"; + sink-pdos =3D + ; + source-pdos =3D + ; + try-power-role =3D "sink"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint =3D <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg =3D <1>; + + dp_altmode_mux: endpoint { + remote-endpoint =3D <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + }; +}; + + +&i2c3 { + status =3D "okay"; + + es8388: audio-codec@10 { + compatible =3D "everest,es8388", "everest,es8328"; + reg =3D <0x10>; + clocks =3D <&cru I2S1_8CH_MCLKOUT>; + AVDD-supply =3D <&vcc_3v3_s0>; + DVDD-supply =3D <&vcc_1v8_s0>; + HPVDD-supply =3D <&vcc_3v3_s0>; + PVDD-supply =3D <&vcc_3v3_s0>; + assigned-clocks =3D <&cru I2S1_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie20>; + status =3D "okay"; +}; + +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211 { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins =3D <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm11 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm11m3_pins>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency =3D <1000000>; + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name =3D "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name =3D "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name =3D "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name =3D "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { + regulator-name =3D "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name =3D "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name =3D "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name =3D "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name =3D "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name =3D "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name =3D "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name =3D "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name =3D "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name =3D "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name =3D "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name =3D "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name =3D "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name =3D "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name =3D "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name =3D "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + + +&tsadc { + status =3D "okay"; +}; + +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy3_host { + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&uart7 { + pinctrl-0 =3D <&uart7m2_xfer>; + status =3D "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios =3D <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios =3D <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dp_altmode_mux>; + }; + }; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + extcon =3D <&u2phy0>; + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; --=20 2.34.1