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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Simon Horman , Faizal Rahim , Aleksandr Loktionov , Chwee-Lin Choong Subject: [PATCH iwl-next v3 3/7] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK Date: Mon, 19 May 2025 03:19:07 -0400 Message-Id: <20250519071911.2748406-4-faizal.abdul.rahim@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250519071911.2748406-1-faizal.abdul.rahim@intel.com> References: <20250519071911.2748406-1-faizal.abdul.rahim@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Faizal Rahim Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros. This prepares the code for adding a new TXDCTL priority field in an upcoming patch. Verified that the macro values remain unchanged before and after refactoring. Reviewed-by: Simon Horman Signed-off-by: Faizal Rahim Tested-by: Mor Bar-Gabay --- drivers/net/ethernet/intel/igc/igc.h | 15 ++++++++++----- drivers/net/ethernet/intel/igc/igc_main.c | 6 ++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index db1e2db1619e..daab06fc3f80 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx= _desc *rx_desc) /* Receive Software Flush */ #define IGC_RXDCTL_SWFLUSH 0x04000000 =20 -#define IGC_TXDCTL_PTHRESH 8 -#define IGC_TXDCTL_HTHRESH 1 -#define IGC_TXDCTL_WTHRESH 16 +#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) +#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) +#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) +#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) +#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) +#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) +#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) +#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) /* Ena specific Tx Queue */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, = 1) /* Transmit Software Flush */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 +#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) =20 #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 4f1a8bc006c6..f3a312c9413b 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *= adapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); =20 - txdctl |=3D IGC_TXDCTL_PTHRESH; - txdctl |=3D IGC_TXDCTL_HTHRESH << 8; - txdctl |=3D IGC_TXDCTL_WTHRESH << 16; + txdctl |=3D IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | + IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE; =20 - txdctl |=3D IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); } =20 --=20 2.34.1