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a=ed25519-sha256; t=1747647743; l=1353; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=uFH7gvcXfq8PXUbSnW4zFmBHt5LxnpwhDzcE1X+yWFo=; b=lXyiRKWe2dUM/NoKi98YA2ST4iD+GyJH/JWFyhdLHqiaIoNSFdOEcmMxv7oVHUvW2lVe0h7ZL UYVeLSPwgrlBOdS2f0m/xziM1YsPsEV3QKXX1cYho1bhDVgeJ3/rrYA X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: NEjYbnRUvtmOXEtvzMb73vXw4IuVrOWE X-Proofpoint-ORIG-GUID: NEjYbnRUvtmOXEtvzMb73vXw4IuVrOWE X-Authority-Analysis: v=2.4 cv=DdAXqutW c=1 sm=1 tr=0 ts=682afd0c cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=3phiJa3m8EW-4BHYHVwA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE5MDA5MSBTYWx0ZWRfX89uTI7uAwsc4 pncC4UGMlUwtPte8YDD6LXuW7kKMu2LIu0by8qzXs7LoGxquoEoEHnRe4DLv2AlUS++WFqB30jO 2QZREwlyeDdyw0lPWSWCcnHEwV1XMNo6cYyNfjZUQxMdA6u6ynZU010BcwX622UVHm2L5PpQiqn jjHb6gIq4dGI7x1uw4oX8RbTeclF783hsIFcklqCFZa3Yq3p4FW5QJNjukVIROdGswWqJ73PiUO lV8rhMNmBAnYskCMOh36r2jY+A4i+qIMUwrWJs8wvBkZNwO0mwuTf2TstPXoZpCtCmFfP1+2Sre zFDzK0++zGlWfk5nP/LRLxIZsQPQy+ShTKvLHDK6jJgsJTX1E65vlUkuighnunTL6TuimOwp/J7 y6Rjs0UiMMMrGImrD0iu5llBbNtPmnjeH9ywAPFC7GIsQ6KnFcb/TUn1xTatTx3orS2VBO05 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-19_04,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 phishscore=0 adultscore=0 mlxscore=0 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505190091 If the link is not up till the pwrctl drivers enable power to endpoints then cur_bus_speed will not be updated with correct speed. As part of rescan, pci_pwrctrl_notify() will be called when new devices are added and as part of it update the link bus speed. Suggested-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pwrctrl/core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index 9cc7e2b7f2b5608ee67c838b6500b2ae4a07ad52..034f0a5d7868fe956e3fc6a9b7e= d485bb69caa04 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -10,16 +10,21 @@ #include #include #include +#include "../pci.h" =20 static int pci_pwrctrl_notify(struct notifier_block *nb, unsigned long act= ion, void *data) { struct pci_pwrctrl *pwrctrl =3D container_of(nb, struct pci_pwrctrl, nb); struct device *dev =3D data; + struct pci_bus *bus =3D to_pci_dev(dev)->bus; =20 if (dev_fwnode(dev) !=3D dev_fwnode(pwrctrl->dev)) return NOTIFY_DONE; =20 + if (bus->self) + pcie_update_link_speed((struct pci_bus *)bus); + switch (action) { case BUS_NOTIFY_ADD_DEVICE: /* --=20 2.34.1 From nobody Fri Dec 19 15:52:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CC9627054F for ; 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a=ed25519-sha256; t=1747647743; l=4129; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=x0K9OeLFsl2BOA7hHSAfMIHOVP+bgVA6z5/oLYSV7cM=; b=hlXh3zqujL1wiLOQN/Kx308qPCf3/2bpuedRxHJErXBNzLyLD75gSBrgDdI32RFQT1req0ZTZ DFCDxSNTsC/B0J+RdROE7tmUukDSd4Zr+1UT97h29tM6Teigs25q2Kt X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: BECO0hoUth5U2RtoctYGERtEPK-F0X4Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE5MDA5MSBTYWx0ZWRfX/AMCneqkZtEh uNY+wuHqtllqvPARzDR6Kf0dzt1NdZQdmjKtJ6NRsPAjLVyNhmdEEQ8uThT5VfyfYal2SwZ0D8w SzG8gSoNFlNKFmdh6XPT8Nxz4IarmctbEQIpQhnKozAKfk8Nx0NYeFQhbpODRdgqsXBffDKammJ nqtv4UkRuSAlvwl56YCAHGuTbfHsm6eKS04MpeJxeXQaYkefvUB09t+05sFczsrYcBWv/7A5eFR YEwMp0de+GVrK2hrkIGRfVtaT9guh03ldqg7MLsAo0wPjo79THag9DogLcrSVd3vHCDcX2pcvJV BGOAhtgzPHQXXi9eonEiNY5BtvdzuqoJ0Cf/70tdQRW1j5h7UMpjBZmylY9nPyuh6MOAw76xKe6 tyFaFi1ljjdkueh107ZOGqU3PJk03JL1sa9WRHZB/oa3UsiXVSR/74kELrc6Z7yuobnlZZw/ X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=682afd20 cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=AH_oHoLqry_2ofrPVhgA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-ORIG-GUID: BECO0hoUth5U2RtoctYGERtEPK-F0X4Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-19_04,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 phishscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505190091 If the driver wants to move to higher data rate/speed than the current data rate then the controller driver may need to change certain votes so that link may come up at requested data rate/speed like QCOM PCIe controllers need to change their RPMh (Resource Power Manager-hardened) state. Once link retraining is done controller drivers needs to adjust their votes based on the final data rate. Some controllers also may need to update their bandwidth voting like ICC bw votings etc. So, add pre_scale_bus_bw() & post_scale_bus_bw() op to call before & after the link re-train. There is no explicit locking mechanisms as these are called by a single client endpoint driver. In case of PCIe switch, if there is a request to change target speed for a downstream port then no need to call these function ops as these are outside the scope of the controller drivers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/bwctrl.c | 15 +++++++++++++++ include/linux/pci.h | 14 ++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c index d8d2aa85a22928b99c5bba1d2bcc5647c0edeeb6..3525bc0cd10f1dd7794abbe84cc= b10e2c53a10af 100644 --- a/drivers/pci/pcie/bwctrl.c +++ b/drivers/pci/pcie/bwctrl.c @@ -161,6 +161,8 @@ static int pcie_bwctrl_change_speed(struct pci_dev *por= t, u16 target_speed, bool int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_r= eq, bool use_lt) { + struct pci_host_bridge *host =3D pci_find_host_bridge(port->bus); + bool is_rootbus =3D pci_is_root_bus(port->bus); struct pci_bus *bus =3D port->subordinate; u16 target_speed; int ret; @@ -173,6 +175,16 @@ int pcie_set_target_speed(struct pci_dev *port, enum p= ci_bus_speed speed_req, =20 target_speed =3D pcie_bwctrl_select_speed(port, speed_req); =20 + /* + * The host bridge driver may need to be scaled for targeted speed + * otherwise link might not come up at requested speed. + */ + if (is_rootbus && host->pre_scale_bus_bw) { + ret =3D host->pre_scale_bus_bw(host, port, target_speed); + if (ret) + return ret; + } + scoped_guard(rwsem_read, &pcie_bwctrl_setspeed_rwsem) { struct pcie_bwctrl_data *data =3D port->link_bwctrl; =20 @@ -197,6 +209,9 @@ int pcie_set_target_speed(struct pci_dev *port, enum pc= i_bus_speed speed_req, !list_empty(&bus->devices)) ret =3D -EAGAIN; =20 + if (bus && is_rootbus && host->post_scale_bus_bw) + host->post_scale_bus_bw(host, port, pci_bus_speed2lnkctl2(bus->cur_bus_s= peed)); + return ret; } =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 51e2bd6405cda5acc33d268bbe1d491b145e083f..7eb0856ba0ed20bd1336683b68a= dd124c7483902 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -601,6 +601,20 @@ struct pci_host_bridge { void (*release_fn)(struct pci_host_bridge *); int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *de= v); + /* + * Callback to the host bridge drivers to update ICC bw votes, clock freq= uencies etc + * for the link re-train to come up in targeted speed. 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So return the enabled aspm states as part of pcie_aspm_enabled(). Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/aspm.c | 4 +++- include/linux/pci.h | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 29fcb0689a918f9cb123691e1680de5a1af2c115..94324fc0d3e650cd3ca2c0bb8c1= 895ca7e647b9d 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1555,8 +1555,10 @@ module_param_call(policy, pcie_aspm_set_policy, pcie= _aspm_get_policy, * is deallocated only when the last child of the bridge (i.e., @pdev or a * sibling) is removed, and the caller should be holding a reference to * @pdev, so this should be safe. + * + * Return: Enabled ASPM states */ -bool pcie_aspm_enabled(struct pci_dev *pdev) +int pcie_aspm_enabled(struct pci_dev *pdev) { struct pcie_link_state *link =3D pcie_aspm_get_link(pdev); =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 7eb0856ba0ed20bd1336683b68add124c7483902..ce9d0812a61c2337ba533ef2463= 93a0101e617ee 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1849,7 +1849,7 @@ int pci_enable_link_state(struct pci_dev *pdev, int s= tate); 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This flag is being properly when aspm is controlled by sysfs. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/aspm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 94324fc0d3e650cd3ca2c0bb8c1895ca7e647b9d..0f858ef86111b43328bc7db01e6= 493ce67178458 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1453,6 +1453,7 @@ static int __pci_enable_link_state(struct pci_dev *pd= ev, int state, bool locked) down_read(&pci_bus_sem); mutex_lock(&aspm_lock); link->aspm_default =3D pci_calc_aspm_enable_mask(state); + link->aspm_disable &=3D ~state; pcie_config_aspm_link(link, policy_to_aspm_state(link)); =20 link->clkpm_default =3D (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0; --=20 2.34.1 From nobody Fri Dec 19 15:52:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B64C0272E5E for ; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 61 +++++++++++++++++++-----------= ---- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index dc98ae63362db0422384b1879a2b9a7dc564d091..bd984cde8d3bd688b2ac32566b0= e9cdbc70905c0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1294,6 +1294,40 @@ static void qcom_pcie_host_post_init(struct dw_pcie_= rp *pp) pcie->cfg->ops->host_post_init(pcie); } =20 +static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int wi= dth) +{ + struct dw_pcie *pci =3D pcie->pci; + unsigned long freq_kbps; + struct dev_pm_opp *opp; + int ret =3D 0, freq_mbps; + + if (pcie->icc_mem) { + ret =3D icc_set_bw(pcie->icc_mem, 0, + width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect pa= th: %d\n", + ret); + } + } else if (pcie->use_pm_opp) { + freq_mbps =3D pcie_dev_speed_mbps(pcie_link_speed[speed]); + if (freq_mbps < 0) + return -EINVAL; + + freq_kbps =3D freq_mbps * KILO; + opp =3D dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, + true); + if (!IS_ERR(opp)) { + ret =3D dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", + freq_kbps * width, ret); + dev_pm_opp_put(opp); + } + } + + return ret; +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, @@ -1478,9 +1512,6 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie= *pcie) { u32 offset, status, width, speed; struct dw_pcie *pci =3D pcie->pci; - unsigned long freq_kbps; - struct dev_pm_opp *opp; - int ret, freq_mbps; =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1492,29 +1523,7 @@ static void qcom_pcie_icc_opp_update(struct qcom_pci= e *pcie) speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 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So as part of pre_bw_scale() disable ASPM and as part of post_scale_bus_bw() enable ASPM back. As the driver needs to enable the ASPM states that are enabled by the system, save PCI ASPM states before disabling them and in post_scale_bus_bw() use the saved ASPM states to enable back the ASPM. Update ICC & OPP votes based on the requested speed so that RPMh votes get updated based on the speed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 63 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 63 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index bd984cde8d3bd688b2ac32566b0e9cdbc70905c0..491324d44785535b84460d46872= 7b8c356ca1040 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -276,10 +276,16 @@ struct qcom_pcie { struct dentry *debugfs; bool suspended; bool use_pm_opp; + int aspm_state; /* Store ASPM state used in pre & post scale bus bw */ }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) =20 +static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridg= e, + struct pci_dev *pdev, int current_speed); +static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int current_speed); + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -1263,6 +1269,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_assert_reset; } =20 + pp->bridge->pre_scale_bus_bw =3D qcom_pcie_host_pre_scale_bus_bw; + pp->bridge->post_scale_bus_bw =3D qcom_pcie_host_post_scale_bus_bw; return 0; =20 err_assert_reset: @@ -1328,6 +1336,61 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *p= cie, int speed, int width) return ret; } =20 +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 offset, status, width; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + return qcom_pcie_set_icc_opp(pcie, speed, width); +} + +static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridg= e, + struct pci_dev *pdev, int current_speed) +{ + struct dw_pcie_rp *pp =3D bridge->bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + struct pci_dev *child; + + /* Get function 0 of downstream device */ + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) + if (PCI_FUNC(child->devfn) =3D=3D 0) + break; + + pci_enable_link_state_locked(child, pcie->aspm_state); + + qcom_pcie_scale_bw(pp, current_speed); +} + +static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge, + struct pci_dev *pdev, int target_speed) +{ + struct dw_pcie_rp *pp =3D bridge->bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + struct pci_dev *child; + + /* Get function 0 of downstream device */ + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) + if (PCI_FUNC(child->devfn) =3D=3D 0) + break; + /* + * QCOM controllers doesn't support link re-train with ASPM enabled. + * Disable ASPM as part of pre_bus_bw() and enable them back as + * part of post_bus_bw(). + */ + pcie->aspm_state =3D pcie_aspm_enabled(child); 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The location of this group of registers is indicated by the MISCOFF register. Each capability has a capability ID to determine which functionality is supported and each capability will point to the next capability supported. Add a basic function to read those capabilities offsets. Signed-off-by: Vivek Pernamitta Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 4 ++++ drivers/bus/mhi/host/init.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95a5573a2ec776ca712e11a1ed0b52..eedac801b80021e44f7c65d33cd= 50760e06c02f2 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 /* Command Ring Element macros */ /* No operation command */ diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index 13e7a55f54ff45b83b3f18b97e2cdd83d4836fe3..a7137a040bdce1c58c98fe9c234= 0aae4cc4387d1 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -467,6 +467,35 @@ int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) return ret; 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MHI bandwidth scaling is advertised by devices that contain the bandwidth scaling capability registers. If enabled, the device aggregates bandwidth requirements and sends them to the host through dedicated mhi event ring. After the host performs the bandwidth switch, it sends an acknowledgment by ringing a doorbell. if the host supports bandwidth scaling events, then it must set BW_CFG.ENABLED bit, set BW_CFG.DB_CHAN_ID to the channel ID to the doorbell that will be used by the host to communicate the bandwidth scaling status and BW_CFG.ER_INDEX to the index for the event ring to which the device should send bandwidth scaling request in the bandwidth scaling capability register. As part of mmio init check if the bw scale capability is present or not, if present advertise host supports bw scale by setting all the required fields. MHI layer will only forward the bw scaling request to the controller driver since MHI doesn't have any idea about transport layer used by the controller, it is responsibility of the controller driver to do actual bw scaling and then pass status to the MHI. MHI will response back to the device based up on the status of the bw scale received. Add a new get_misc_doorbell() to get doorbell for misc capabilities to use the doorbell with mhi events like MHI BW scale etc. Use workqueue & mutex for the bw scale events as the pci_set_target_speed() which will called by the mhi controller driver can sleep. Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 16 +++++++ drivers/bus/mhi/host/init.c | 61 ++++++++++++++++++++++++- drivers/bus/mhi/host/internal.h | 7 ++- drivers/bus/mhi/host/main.c | 98 +++++++++++++++++++++++++++++++++++++= +++- drivers/bus/mhi/host/pm.c | 10 ++++- include/linux/mhi.h | 13 ++++++ 6 files changed, 199 insertions(+), 6 deletions(-) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index eedac801b80021e44f7c65d33cd50760e06c02f2..0a02acee709af7a2a6abddcb954= 7ef56564ce453 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -208,6 +208,22 @@ #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \ MHI_PKT_TYPE_COALESCING)) =20 +/* MHI Bandwidth scaling offsets */ +#define MHI_BW_SCALE_CFG_OFFSET 0x4 +#define MHI_BW_SCALE_CAP_ID (3) + +#define MHI_BW_SCALE_ENABLE(bw_scale_db, er_index) cpu_to_le32(FIELD_PREP(= GENMASK(31, 25), \ + bw_scale_db) | \ + FIELD_PREP(GENMASK(23, 19), er_index) | \ + BIT(24)) + +#define MHI_TRE_GET_EV_BW_REQ_SEQ(tre) FIELD_GET(GENMASK(15, 8), (MHI_TRE_= GET_DWORD(tre, 0))) +#define MHI_BW_SCALE_DB_ID(er_index) FIELD_PREP(GENMASK(31, 25), er_index) + +#define MHI_BW_SCALE_RESULT(status, seq) cpu_to_le32(FIELD_PREP(GENMASK(11= , 8), status) | \ + FIELD_PREP(GENMASK(7, 0), seq)) +#define MHI_BW_SCALE_NACK 0xF + enum mhi_pkt_type { MHI_PKT_TYPE_INVALID =3D 0x0, MHI_PKT_TYPE_NOOP_CMD =3D 0x1, diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index a7137a040bdce1c58c98fe9c2340aae4cc4387d1..9fe6020f7868ec8bd114d0d96ed= c9d17624cbac5 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -496,10 +496,53 @@ static int mhi_find_capability(struct mhi_controller = *mhi_cntrl, u32 capability, return -ENXIO; } =20 +static int mhi_get_er_index(struct mhi_controller *mhi_cntrl, + enum mhi_er_data_type type) +{ + struct mhi_event *mhi_event =3D mhi_cntrl->mhi_event; + int i; + + /* Find event ring for requested type */ + for (i =3D 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->data_type =3D=3D type) + return mhi_event->er_index; + } + + return -ENOENT; +} + +static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl, + int bw_scale_db) +{ + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + int ret, er_index, val; + u32 bw_cfg_offset; + + ret =3D mhi_find_capability(mhi_cntrl, MHI_BW_SCALE_CAP_ID, &bw_cfg_offse= t); + if (ret) + return ret; + + er_index =3D mhi_get_er_index(mhi_cntrl, MHI_ER_BW_SCALE); + if (er_index < 0) + return er_index; + + bw_cfg_offset +=3D MHI_BW_SCALE_CFG_OFFSET; + + /* Advertise host support */ + val =3D MHI_BW_SCALE_ENABLE(bw_scale_db, er_index); + + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, val); + + dev_dbg(dev, "Bandwidth scaling setup complete with event ring: %d\n", + er_index); + + return 0; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val; - int i, ret; + int i, ret, doorbell =3D 0; struct mhi_chan *mhi_chan; struct mhi_event *mhi_event; void __iomem *base =3D mhi_cntrl->regs; @@ -633,6 +676,16 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) return ret; } =20 + if (mhi_cntrl->get_misc_doorbell) + doorbell =3D mhi_cntrl->get_misc_doorbell(mhi_cntrl, MHI_ER_BW_SCALE); + + if (doorbell > 0) { + ret =3D mhi_init_bw_scale(mhi_cntrl, doorbell); + if (!ret) + mhi_cntrl->bw_scale_db =3D base + val + (8 * doorbell); + else + dev_warn(dev, "Failed to setup bandwidth scaling: %d\n", ret); + } return 0; } =20 @@ -778,6 +831,9 @@ static int parse_ev_cfg(struct mhi_controller *mhi_cntr= l, case MHI_ER_CTRL: mhi_event->process_event =3D mhi_process_ctrl_ev_ring; break; + case MHI_ER_BW_SCALE: + mhi_event->process_event =3D mhi_process_bw_scale_ev_ring; + break; default: dev_err(dev, "Event Ring type not supported\n"); goto error_ev_cfg; @@ -1012,9 +1068,12 @@ int mhi_register_controller(struct mhi_controller *m= hi_cntrl, =20 mhi_event->mhi_cntrl =3D mhi_cntrl; spin_lock_init(&mhi_event->lock); + mutex_init(&mhi_event->mutex); if (mhi_event->data_type =3D=3D MHI_ER_CTRL) tasklet_init(&mhi_event->task, mhi_ctrl_ev_task, (ulong)mhi_event); + else if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + INIT_WORK(&mhi_event->work, mhi_process_ev_work); else tasklet_init(&mhi_event->task, mhi_ev_task, (ulong)mhi_event); diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/interna= l.h index ce566f7d2e9240c64044407aa4124ad3cdb98003..cf64adaecad2aeec8569da5276e= c60dd7e97e5e0 100644 --- a/drivers/bus/mhi/host/internal.h +++ b/drivers/bus/mhi/host/internal.h @@ -248,6 +248,8 @@ struct mhi_event { struct mhi_ring ring; struct db_cfg db_cfg; struct tasklet_struct task; + struct work_struct work; + struct mutex mutex; /* lock for synchronization */ spinlock_t lock; int (*process_event)(struct mhi_controller *mhi_cntrl, struct mhi_event *mhi_event, @@ -410,7 +412,8 @@ int mhi_process_data_event_ring(struct mhi_controller *= mhi_cntrl, struct mhi_event *mhi_event, u32 event_quota); int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, struct mhi_event *mhi_event, u32 event_quota); - +int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota); /* ISR handlers */ irqreturn_t mhi_irq_handler(int irq_number, void *dev); irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); @@ -426,5 +429,5 @@ void mhi_unmap_single_no_bb(struct mhi_controller *mhi_= cntrl, struct mhi_buf_info *buf_info); void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info); - +void mhi_process_ev_work(struct work_struct *work); #endif /* _MHI_INT_H */ diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 9bb0df43ceef1e54e8817422516aab1def6fdc4a..f87e9550b59227947fc7268c579= 9eea274c66b98 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -472,7 +472,10 @@ irqreturn_t mhi_irq_handler(int irq_number, void *dev) if (mhi_dev) mhi_notify(mhi_dev, MHI_CB_PENDING_DATA); } else { - tasklet_schedule(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + queue_work(mhi_cntrl->hiprio_wq, &mhi_event->work); + else + tasklet_schedule(&mhi_event->task); } =20 return IRQ_HANDLED; @@ -1049,6 +1052,99 @@ int mhi_process_data_event_ring(struct mhi_controlle= r *mhi_cntrl, return count; } =20 +int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota) +{ + struct mhi_event_ctxt *er_ctxt =3D &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_even= t->er_index]; + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + struct mhi_ring *ev_ring =3D &mhi_event->ring; + dma_addr_t ptr =3D le64_to_cpu(er_ctxt->rp); + u32 response =3D MHI_BW_SCALE_NACK; + struct mhi_ring_element *dev_rp; + struct mhi_link_info link_info; + int ret =3D -EINVAL; + + if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { + ret =3D -EIO; + goto exit_bw_scale; + } + + if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee)) + goto exit_bw_scale; + + if (!is_valid_ring_ptr(ev_ring, ptr)) { + dev_err(dev, + "Event ring rp points outside of the event ring\n"); + ret =3D -EIO; + goto exit_bw_scale; + } + + dev_rp =3D mhi_to_virtual(ev_ring, ptr); + + /* If rp points to base, we need to wrap it around */ + if (dev_rp =3D=3D ev_ring->base) + dev_rp =3D ev_ring->base + ev_ring->len; + dev_rp--; + + /* Fast forward to currently processed element and recycle er */ + ev_ring->rp =3D dev_rp; + ev_ring->wp =3D dev_rp - 1; + if (ev_ring->wp < ev_ring->base) + ev_ring->wp =3D ev_ring->base + ev_ring->len - ev_ring->el_size; + mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); + + if (WARN_ON(MHI_TRE_GET_EV_TYPE(dev_rp) !=3D MHI_PKT_TYPE_BW_REQ_EVENT)) { + dev_err(dev, "!BW SCALE REQ event\n"); + goto exit_bw_scale; + } + + link_info.target_link_speed =3D MHI_TRE_GET_EV_LINKSPEED(dev_rp); + link_info.target_link_width =3D MHI_TRE_GET_EV_LINKWIDTH(dev_rp); + link_info.sequence_num =3D MHI_TRE_GET_EV_BW_REQ_SEQ(dev_rp); + + dev_dbg(dev, "Received BW_REQ with seq:%d link speed:0x%x width:0x%x\n", + link_info.sequence_num, + link_info.target_link_speed, + link_info.target_link_width); + + /* Bring host and device out of suspended states */ + ret =3D mhi_device_get_sync(mhi_cntrl->mhi_dev); + if (ret) + goto exit_bw_scale; + + mhi_cntrl->runtime_get(mhi_cntrl); + + ret =3D mhi_cntrl->bw_scale(mhi_cntrl, &link_info); + if (!ret) + response =3D 0; + + response =3D MHI_BW_SCALE_RESULT(response, link_info.sequence_num); + + write_lock_bh(&mhi_cntrl->pm_lock); + mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, response); + write_unlock_bh(&mhi_cntrl->pm_lock); + + mhi_cntrl->runtime_put(mhi_cntrl); + mhi_device_put(mhi_cntrl->mhi_dev); + +exit_bw_scale: + return ret; +} + +void mhi_process_ev_work(struct work_struct *work) +{ + struct mhi_event *mhi_event =3D container_of(work, struct mhi_event, + work); + + struct mhi_controller *mhi_cntrl =3D mhi_event->mhi_cntrl; + + if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) + return; + + guard(mutex)(&mhi_event->mutex); + mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); +} + void mhi_ev_task(unsigned long data) { struct mhi_event *mhi_event =3D (struct mhi_event *)data; diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index 2fb27e6f8f88ebc701dad56dd60844d8470dd418..8b518da4995d83a299f419908b3= 753e6b78c8803 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -523,7 +523,10 @@ static void mhi_pm_disable_transition(struct mhi_contr= oller *mhi_cntrl, if (mhi_event->offload_ev) continue; disable_irq(mhi_cntrl->irq[mhi_event->irq]); - tasklet_kill(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + cancel_work_sync(&mhi_event->work); + else + tasklet_kill(&mhi_event->task); } =20 /* Release lock and wait for all pending threads to complete */ @@ -670,7 +673,10 @@ static void mhi_pm_sys_error_transition(struct mhi_con= troller *mhi_cntrl) for (i =3D 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { if (mhi_event->offload_ev) continue; - tasklet_kill(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + cancel_work_sync(&mhi_event->work); + else + tasklet_kill(&mhi_event->task); } =20 /* Release lock and wait for all pending threads to complete */ diff --git a/include/linux/mhi.h b/include/linux/mhi.h index dd372b0123a6da5107b807ff8fe940c567eb2030..2041bbb2e2396eb2e19e6bc0a5e= 981aa2917ebdd 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -102,10 +102,12 @@ struct image_info { * struct mhi_link_info - BW requirement * target_link_speed - Link speed as defined by TLS bits in LinkControl reg * target_link_width - Link width as defined by NLW bits in LinkStatus reg + * sequence_num - used by device to track bw requests sent to host */ struct mhi_link_info { unsigned int target_link_speed; unsigned int target_link_width; + int sequence_num; }; =20 /** @@ -183,10 +185,12 @@ enum mhi_ch_ee_mask { * enum mhi_er_data_type - Event ring data types * @MHI_ER_DATA: Only client data over this ring * @MHI_ER_CTRL: MHI control data and client data + * @MHI_ER_BW_SCALE: MHI controller bandwidth scale functionality */ enum mhi_er_data_type { MHI_ER_DATA, MHI_ER_CTRL, + MHI_ER_BW_SCALE, }; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pci.c | 12 ++++++++++++ include/linux/pci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e77d5b53c0cec9c7cdd043ac44329d1b285cae83..363565fd71bc184bb07e4f21e90= 09ce382e6075b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6035,6 +6035,18 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) } EXPORT_SYMBOL(pcie_link_speed_mbps); =20 +/** + * pci_lnkctl2_bus_speed - convert lnkctl2 speed to pci_bus_speed + * @speed: LNKCAP2 SLS value + * + * Return: pci_bus_speed + */ +enum pci_bus_speed pci_lnkctl2_bus_speed(int speed) +{ + return pcie_link_speed[speed]; +} +EXPORT_SYMBOL(pci_lnkctl2_bus_speed); + /** * pcie_bandwidth_available - determine minimum link settings of a PCIe * device and its bandwidth limitation diff --git a/include/linux/pci.h b/include/linux/pci.h index ce9d0812a61c2337ba533ef246393a0101e617ee..48c3f5b1f6f86b652355fc9edbc= f834d64fddd11 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1655,6 +1655,7 @@ int pci_cfg_space_size(struct pci_dev *dev); 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This feature is only enabled for QCA6390. Bandwidth scaling is initiated by the endpoint firmware based upon the bandwidth requirements, if there is high bandwidth data endpoint requests for higher data rates or if there is less bandwidth they request for lower data rates to reduce power. Endpoint initiates this through MHI protocol. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04546-QCAHSPSWPL_V1_V2_SILICONZ_I= OE-1 Signed-off-by: Miaoqing Pan Signed-off-by: Krishna Chaitanya Chundru --- drivers/net/wireless/ath/ath11k/mhi.c | 41 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/a= th/ath11k/mhi.c index fc77eac83e953148b96cad096d26b32222157b24..8057031d654d794f9e882a975f9= 9083c193e492c 100644 --- a/drivers/net/wireless/ath/ath11k/mhi.c +++ b/drivers/net/wireless/ath/ath11k/mhi.c @@ -20,6 +20,7 @@ #define MHI_TIMEOUT_DEFAULT_MS 20000 #define RDDM_DUMP_SIZE 0x420000 #define MHI_CB_INVALID 0xff +#define MHI_BW_SCALE_CHAN_DB 126 =20 static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] =3D { { @@ -73,6 +74,17 @@ static struct mhi_event_config ath11k_mhi_events_qca6390= [] =3D { .client_managed =3D false, .offload_channel =3D false, }, + { + .num_elements =3D 8, + .irq_moderation_ms =3D 0, + .irq =3D 1, + .mode =3D MHI_DB_BRST_DISABLE, + .data_type =3D MHI_ER_BW_SCALE, + .priority =3D 2, + .hardware_event =3D false, + .client_managed =3D false, + .offload_channel =3D false, + }, }; =20 static const struct mhi_controller_config ath11k_mhi_config_qca6390 =3D { @@ -313,6 +325,33 @@ static void ath11k_mhi_op_write_reg(struct mhi_control= ler *mhi_cntrl, writel(val, addr); } =20 +static int ath11k_mhi_op_get_misc_doorbell(struct mhi_controller *mhi_cntr= l, + enum mhi_er_data_type type) +{ + if (type =3D=3D MHI_ER_BW_SCALE) + return MHI_BW_SCALE_CHAN_DB; + + return -EINVAL; +} + +static int ath11k_mhi_op_bw_scale(struct mhi_controller *mhi_cntrl, + struct mhi_link_info *link_info) +{ + enum pci_bus_speed speed =3D pci_lnkctl2_bus_speed(link_info->target_link= _speed); + struct ath11k_base *ab =3D dev_get_drvdata(mhi_cntrl->cntrl_dev); + struct pci_dev *pci_dev =3D to_pci_dev(ab->dev); + struct pci_dev *pdev; + + if (!pci_dev) + return -EINVAL; + + pdev =3D pci_upstream_bridge(pci_dev); + if (!pdev) + return -ENODEV; + + return pcie_set_target_speed(pdev, speed, true); +} + static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) { struct device_node *np; @@ -389,6 +428,8 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci) mhi_ctrl->status_cb =3D ath11k_mhi_op_status_cb; mhi_ctrl->read_reg =3D ath11k_mhi_op_read_reg; mhi_ctrl->write_reg =3D ath11k_mhi_op_write_reg; + mhi_ctrl->bw_scale =3D ath11k_mhi_op_bw_scale; + mhi_ctrl->get_misc_doorbell =3D ath11k_mhi_op_get_misc_doorbell; =20 switch (ab->hw_rev) { case ATH11K_HW_QCN9074_HW10: --=20 2.34.1