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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703f6f1sm1919378e87.248.2025.05.19.09.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 09:04:28 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 19 May 2025 19:04:10 +0300 Subject: [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250519-dpu-drop-features-v4-8-6c5e88e31383@oss.qualcomm.com> References: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> In-Reply-To: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12512; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=DenAajGfDlpCx9eZxx/Wm6vZSrwqGZ6us7Lzpqfm7Rg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ4Z2WFWu+Nd7YQXeqou7zPj0OGasu5L7xXt5fG7ZTefSj TbXrTd2MhqzMDByMciKKbL4FLRMjdmUHPZhx9R6mEGsTCBTGLg4BWAitus4GHq46r3VY4q5Pt/c L/XN6V6ph9bq4m9ONvvkOptPX5jwuNp0wvoHeuc9rJo9CoXTr35ZPa15mc8fJ4tP+n1fVoXGvG0 /U8w1Wzvr1yLDE/87mcq7Oqr1jq7aYX8xM3rz9QI3851nNR5frut8LBzv0+w5wc5zjmvLBd13in 4/clL9hBufL5SK2R1zyZE7jOXEdKOcmY+vlO1VCf3YfnFSQPHpa+WGgj2n++/JmLIzd0rsKU98K vpxw9LTb7aUNuTYpck+fruy8a6vUEtBmuA6hmzNtwxTi2r83s15KdrVYP1ZorH+ANOu9Q897aym tKg99KribLir+/LSY8FHVmenHbvqsFFxewdz0R/miq1RAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=dIimmPZb c=1 sm=1 tr=0 ts=682b568f cx=c_pps a=WJcna6AvsNCxL/DJwPP1KA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KCnXgIHxdjs5WteQjqoA:9 a=QEXdDO2ut3YA:10 a=_Y9Zt4tPzoBS9L09Snn2:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: mcWnV22Gx9dP7Yp6byt5lNezWJA7BjQi X-Proofpoint-GUID: mcWnV22Gx9dP7Yp6byt5lNezWJA7BjQi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE5MDE1MCBTYWx0ZWRfX0MhbhCLRoTPM dvxkq7OYDJRDhmIV+WT2kV98QXDAPtsDh/cV5QSvLXgh6rIWAE36zkkJCW3FXNoseiwV9nYwVAI neWWNEUHWzqTKptdRlj7ktFRM5JRGJs0nyn27yHo+yLMepX3moRVHNeNbSE6LCcYSrkNZNl5BXu sZQzdZFcmiKWGD5A+8k8XAUmzeqbArYdpPTE6ewck5iJNUR5xav22/72LoiWpjWC6VE6CROlgo2 Hwvy2ZFX6rVDcUv82bZfmqhM43HcTwxw8cLeg66eMRcEFn9FL9LDYyVTSU39Ez+M098chvjhcXW LojqqE6SkgXFtmH1d2Nv3Rqvye4vBdlP80xl+2HH3LjXAWHcxSDlXyfwPbQdelTdPghaIMAKY++ GOd1nryC4MA81peimVIDlRSundUcP93+kZ2h8UHiGHC0d88U2Mo/wlx3CuJAOU+SBTtVqizZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-19_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505190150 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >=3D 9 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 9 files changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index b14d0d6886f019c8fa06047baf734e38696f14ce..52ad7e2af0148c9ea81a2c95b27= 0be7058fbaec1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 4c5785332b5240109af36a1256d4ea29c348bced..83f73c7cdcc3a280285fa322307= 96fac57167ed6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index 960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5..b21aab274703ac1f38698bee82d= 5d28b0fb6a0d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 85dcf577b844995fe11322ec506885bc4a85e33c..d7e5f4dd3bccab125b0a42f67ed= df194359dc761 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -30,32 +30,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 00e6f3e56ed1f9af581bad9845971fad315ef83c..a162c4f9ebd79d3ba16b50117ee= 7462afdbbf3d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -110,9 +110,6 @@ BIT(DPU_CTL_VM_CFG) | \ BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) =20 -#define CTL_SM8550_MASK \ - (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 01dd6e65f777f3b92f41e2ccb08f279650d50425..3d6c2db395b65b89845cb728119= 5ca5ca16c22e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -134,7 +134,6 @@ enum { * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs - * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ @@ -143,7 +142,6 @@ enum { DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, - DPU_CTL_HAS_LAYER_EXT4, DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index d58a0f1e8edb524ff3f21ff8c96688dd2ae49541..58bdd4d33b37d83f30931f09fdf= 80bef41e1f0fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -555,7 +555,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_c= tl *ctx, DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]); DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]); DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]); - if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features))) + if (ctx->mdss_ver->core_major_ver >=3D 9) DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]); } =20 @@ -743,12 +743,14 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct = dpu_hw_ctl *ctx, * @dev: Corresponding device for devres management * @cfg: ctl_path catalog entry for which driver object is required * @addr: mapped register io address of MDP + * @mdss_ver: dpu core's major and minor versions * @mixer_count: Number of mixers in @mixer * @mixer: Pointer to an array of Layer Mixers defined in the catalog */ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, const struct dpu_ctl_cfg *cfg, void __iomem *addr, + const struct dpu_mdss_version *mdss_ver, u32 mixer_count, const struct dpu_lm_cfg *mixer) { @@ -762,6 +764,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->hw.log_mask =3D DPU_DBG_MASK_CTL; =20 c->caps =3D cfg; + c->mdss_ver =3D mdss_ver; =20 if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index feb09590bc8fc5c77c2c673fd888c28281a98b5a..9cd9959682c21cc1c6d8d14b8fb= 377deb33cc10d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -274,6 +274,7 @@ struct dpu_hw_ctl_ops { * @pending_cwb_flush_mask: pending CWB flush * @pending_dsc_flush_mask: pending DSC flush * @pending_cdm_flush_mask: pending CDM flush + * @mdss_ver: MDSS revision information * @ops: operation list */ struct dpu_hw_ctl { @@ -295,6 +296,8 @@ struct dpu_hw_ctl { u32 pending_dsc_flush_mask; u32 pending_cdm_flush_mask; =20 + const struct dpu_mdss_version *mdss_ver; + /* ops */ struct dpu_hw_ctl_ops ops; }; @@ -312,6 +315,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct d= pu_hw_blk *hw) struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, const struct dpu_ctl_cfg *cfg, void __iomem *addr, + const struct dpu_mdss_version *mdss_ver, u32 mixer_count, const struct dpu_lm_cfg *mixer); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 2e296f79cba1437470eeb30900a650f6f4e334b6..d728e275ac427f7849dad4f4a05= 5c56840ca2d23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -142,7 +142,7 @@ int dpu_rm_init(struct drm_device *dev, struct dpu_hw_ctl *hw; const struct dpu_ctl_cfg *ctl =3D &cat->ctl[i]; =20 - hw =3D dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer); + hw =3D dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, = cat->mixer); if (IS_ERR(hw)) { rc =3D PTR_ERR(hw); DPU_ERROR("failed ctl object creation: err %d\n", rc); --=20 2.39.5