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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703f6f1sm1919378e87.248.2025.05.19.09.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 09:05:06 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 19 May 2025 19:04:26 +0300 Subject: [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250519-dpu-drop-features-v4-24-6c5e88e31383@oss.qualcomm.com> References: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> In-Reply-To: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9006; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=IW4d4xBKTgHyNVii0QUGpaeTXsIQim6e/aNBlVdX5gA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoK1Z9pdyh7FLdsFH4gMuj7uy4N88VsmsoCxYC2 SZpwA4/8ZqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCtWfQAKCRCLPIo+Aiko 1RBKB/944p5xRYZlhXU+OIqgwJKrO2ner/qjoHkT0qpR77B3YzfIg7Ptbr0pL/Y4VOWBIa+KCal J2tMaWJpvNkkxaadvcmIP+bMg267D7HNpTlM+B68GjJJfgzVpl55FvL5o3F6GnLy9QFaUfc4+EK XOkI/TNl/9neZR/UmPMR0ppujGltfLG4gbrfZy9aCwxC6rRd893Q1QM8ayvWuafGpihqXy631zz JqZ94oWmwHBolxkl8oGgTMBSeU8I7DhmBDqvDkggK3z8TSYqRSUM2MbGYvXbF8s6bvOdZVwk/ri dhdL3LoDML6PKszkUOpwft4ikQLqL4/xsRoxJ6hO6qSAe6MS X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=OfqYDgTY c=1 sm=1 tr=0 ts=682b56b7 cx=c_pps a=4ztaESFFfuz8Af0l9swBwA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Vb8ASh8KX3Dd0k_o0G4A:9 a=QEXdDO2ut3YA:10 a=TPnrazJqx2CeVZ-ItzZ-:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: dgq7kK1uAd3IwxRFcFBWtnIIbJoJgASX X-Proofpoint-GUID: dgq7kK1uAd3IwxRFcFBWtnIIbJoJgASX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE5MDE1MCBTYWx0ZWRfX42uGJvOLfMYe NLhntkMzDzGBHgqEl2VOr5oD61SgM05FJpvjzAcxm8kyNRO2NY5CmxkHu8SgYVYtPRb0dZrrkNe c8x5CPeOi6s1CjXl2+tYbbbPc9Po5Uch6Otv4I8yU/I9H+FRezBTVvSPfDA1dj1O1xpW3yKWQfB SbaP4rv8NW8D8NUbLoqSVH/T0o+8/TttPsB0/SSLftrBs4wnuWEJMO3FDtz6hue/Ysl7X6tit6/ rshTQmbJ65U4QMoTs6FQ7bHqkBIpfj7/LTjfWzm1av06OJQgwiB3nBmi1XqESOQQMD4juFZig0U GK99D/q5r4l3zvl7oqRMS2ipRVxM9/vNuYN9Qe3TH7paTDzNeX+hHqJL5HbtIp1D2VLrtdgTVS6 kVR2Hlzq7xxVOC0D9jNZAHh4K6V4sObNtMMRxgbaC37y/VrqgZZ1zxP1C/nS6WsAnpWAO4zj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-19_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505190150 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 10 files changed, 8 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 8e37c40620b62aacdcb47c7a04bcfce944ab0b4c..5d3b864d28a86fb86fc4576210c= 9418604afd844 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index a05d2ef8fc9d217898b8c12d4639563b28b4477b..a6e9dfc583f283d752545b3f700= c3d509e2a2965 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_4", .id =3D DSC_4, .base =3D 0x81000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_5", .id =3D DSC_5, .base =3D 0x81400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index cb0b5687b5239418f50c539447f9cfa56e81fcc6..fe9c9301e3d9d2d3a0a34ab9aed= 0f307d08c34ca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -193,11 +193,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 17fa0ef9ac03e4649a218cd837b296211ef4506c..9ceff398fd6f554085440f509b6= f8398b4fbf304 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -258,19 +258,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 06bcaf4d8b0db74c349112af6884f7f3139a7ff8..a46e9e3ff565ba5ef233af76f1c= 6cebb1d0c318a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 9c4e8450b67760c880d9bd2528c6a954a0282e08..98190ee7ec7aca6835376b03037= 9a5a3d8b0859b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 01430ff90ab0988bdaa91b85458dd649aab543b3..41906dadff5a8ef39b2e90f3e80= bb699a5cf59b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -174,14 +174,11 @@ enum { =20 /** * DSC sub-blocks/features - * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets - * the pixel output from this DSC. * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { - DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_NATIVE_42x_EN, + DPU_DSC_NATIVE_42x_EN =3D 0x1, DPU_DSC_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.c index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf= 29a168268839e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk( * @dev: Corresponding device for devres management * @cfg: DSC catalog entry for which driver object is required * @addr: Mapped register io address of MDP + * @mdss_ver: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_dsc context */ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr) + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_dsc *c; =20 @@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *d= ev, c->ops.dsc_disable =3D dpu_hw_dsc_disable; c->ops.dsc_config =3D dpu_hw_dsc_config; c->ops.dsc_config_thresh =3D dpu_hw_dsc_config_thresh; - if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL)) + if (mdss_ver->core_major_ver >=3D 5) c->ops.dsc_bind_pingpong_blk =3D dpu_hw_dsc_bind_pingpong_blk; =20 return c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.h index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e28= 4bb072ecc3395 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -64,7 +64,8 @@ struct dpu_hw_dsc { =20 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr); + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver); =20 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index c2a659512cb747e1dd5ed9e28534286ff8d67f4f..a2219c4f55a45db894ff18c1fd0= a810c1a3cf811 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -171,7 +171,7 @@ int dpu_rm_init(struct drm_device *dev, if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); else - hw =3D dpu_hw_dsc_init(dev, dsc, mmio); + hw =3D dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); =20 if (IS_ERR(hw)) { rc =3D PTR_ERR(hw); --=20 2.39.5