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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-550e703f6f1sm1919378e87.248.2025.05.19.09.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 09:04:53 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 19 May 2025 19:04:20 +0300 Subject: [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250519-dpu-drop-features-v4-18-6c5e88e31383@oss.qualcomm.com> References: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> In-Reply-To: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8101; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=+WjsCRpQ3QCe/Ce1kvO60/iVL+5JGid0k0Ksq+2ENGA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoK1Z86fQc+v66Hc/YT5TqWGoVK9TyJUgTPpwCv yADGvfHtIKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCtWfAAKCRCLPIo+Aiko 1frqB/0cG/LOLfA4Xr9FXr9voaSVWYeW+1tO8GXemyDW+OazjU8gXUNm05zOcuDkB6zMQc9hYEh 6UlGICDt7DK2PuuXP13PuNjm9gFmbmHNzo8cGCDh9NBhUG/L5dZSVssUibdsFKuPXAHXfKDlVJ/ //m8QaI08aDXTsxc5CQHeG2Bv/88YbhdE24hWxwXqhtDGc9ykypaDVHm6NOkI61pg769InULWXC t0QwpCT0pVmZEEqTOOOP8Rsv9YQSn4owRMTqkzydzkGiXhlnm0nH8zn1mp1CHsb4CxXtir4+aB0 PodRwSJ/kgJMZiSmojj9Q8hIWhbW1rjQWO71p8CzZDpOAXVl X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=OfqYDgTY c=1 sm=1 tr=0 ts=682b56a7 cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=MP74wIc9YfZe_pNrw8AA:9 a=QEXdDO2ut3YA:10 a=efpaJB4zofY2dbm2aIRb:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 6t27wsgvdXs1XhunzR-IkgUaPtfLmUVN X-Proofpoint-GUID: 6t27wsgvdXs1XhunzR-IkgUaPtfLmUVN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE5MDE1MCBTYWx0ZWRfX1wG036kyzJGS U2WBaxD4Ub5IyZ0bNh3WLJifLhxcjJJCbJUbNdxNRql0ACWlh9qTwGFhs6hOKNKzkCQRdJISwus OAaxem/UU3ij7H/qOM62sWSo2YBT41ib22ZuXBkQn2LhZXBCcIEALOmo2UJykVWte4CoGog6SAl jKh+Y1QD4xVJDZGtcNG+gXs7LUfpzaBIr6OsP6JG3q8Pt7yc2l19fq97Wb9ahIPFddmSEtbqqY5 Qx1TqLxU8mloOck0q3yA6iH2HGepG8H1R2K000k2EvNkb54eXd1fvxoig7oMT5XXsmIP3wBjFN/ PMgFiIesK0TsBemTNGL29LdmqPmgWyx67Beereh00sfLhJG8MLCGFQeq4bYlCjtmU/xBkVzdpQX mbx9qdUUSJknxmGBIRxOFSetrApeiYtQHq6DTkwnSumByznrbBFp3uTpKYMiN4rXLENAylE6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-19_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 mlxlogscore=808 clxscore=1015 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505190150 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check. Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- 10 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index c0b4db94777c42efd941fdd52993b854ab54c694..29e0eba91930f96fb94c97c33b4= 490771c3a7c17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index d3e4c48be306a04b457cc002910eb018a3f13154..cb1ee4b63f9fe8f0b069ad4a75b= 121d40e988d2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index c488b88332d0e69cfb23bcf4e41a2e4f4be6844d..b44d02b48418f7bca50b0411954= 0122fb861b971 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 0e8e71775f2c1c38af018353c85ffeb6ccddb42f..8af63db315b45a5a44836303c8c= e92eeccc5b1f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index f2ec30837f9ccbff1041f0465d0123382a00355a..f91220496082bd101099c1817c4= 1699215980d53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps =3D { static const struct dpu_mdp_cfg msm8998_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3..8f9a097147c02b538e720dd52f7= 7e705f7ff1ca2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps =3D { static const struct dpu_mdp_cfg sdm660_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 657f733c9ffff73f9eb5051ba55ed2e4e7bb496d..0ad18bd273ff8c080f001f0bee6= 54393cf0c24cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps =3D { static const struct dpu_mdp_cfg sdm630_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 15da5ded19267711e6df8605d576539475fe634c..3e66feb3e18dcc1d9ed5403a429= 89d97f84a8edc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps =3D { static const struct dpu_mdp_cfg sdm845_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), + .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5..92dfbb5e7f916bf32afeffdb6b8= 43f1da3f3fd44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -34,8 +34,6 @@ * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block re= sults * in a failure - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SE= L register - * (moved into INTF block since DPU 5.0.0) * @DPU_MDP_MAX Maximum value =20 */ @@ -44,7 +42,6 @@ enum { DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, - DPU_MDP_VSYNC_SEL, DPU_MDP_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 562a3f4c5238a3ad6c8c1fa4d285b9165ada3cfd..cebe7ce7b258fc178a687770906= f7c4c20aa0d4c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -270,7 +270,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->setup_clk_force_ctrl =3D dpu_hw_setup_clk_force_ctrl; ops->get_danger_status =3D dpu_hw_get_danger_status; =20 - if (cap & BIT(DPU_MDP_VSYNC_SEL)) + if (mdss_rev->core_major_ver < 5) ops->setup_vsync_source =3D dpu_hw_setup_vsync_sel; else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) ops->setup_vsync_source =3D dpu_hw_setup_wd_timer; --=20 2.39.5