From nobody Fri Dec 19 17:19:50 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE491F4736; Sun, 18 May 2025 22:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605923; cv=none; b=qtgztCacJ354plTpwoDL90WAxE7T3XtWSFuWbA9Bk+Fo0phee+aZS93SW3yrzN/FEhRctGc2wkzVVBmP/kvnjkJGDcvFY5WcN4ofgKPReJqLscDR4F1oBzgU7o0D+dbagvA/uSnnPD3aW6TIgEGUStyA7gDcPrOJrdgMqN/Wq4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605923; c=relaxed/simple; bh=uJ7kEC35Tl7HhJpalOGTwGu3l9PgsCwPG8VRXQRWXzk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NbaBRN1i+ZTwngX4o4drwavja613SvPaQBeHFNEhGgE3ndR4HcIvBWCIwaetRMUBJlr3Sea0VKlYE3T7MRez2JiP9N4zoQdRxBmO21X0dENdXeYPcMXtveBDki43vsG1G4H6V2xv7CY6eRx0uvtHt0g7slud+CN6jzTwnsw3fTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=MJjarBC7; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="MJjarBC7" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=4c0/h5O89NEh//kKOA3P/rcNgyur1rYbiL5S7VTGzjg=; b=MJjarBC7NH33DQTOZsIoRh8/Dr EyDCga3YnmDAsQSuCgBmij5Oj/ddu2Fm9St1FwiP5rXY1p8BNHD0NqzKZpViLXqp3TgHQYZIUxFFg E+0eGXMet+nAh64Jv5yllYcUlFV37ttNuKbz0z5H9r2NbIZRtOTZOtNcO4Yc4+rVXvSdwa96SKK9M 2Q2QMdHxHLJT4E0SCJXH9JMCtUe8I5s9r+LJDQChWsAUhQLamBzBEddhoFQ/IknEqgMondS0k/RKO edWJuv3YEh/G5K9HJEn03O6zwlq/VDCNKmM0eAF7bevLuN7v8Vs7l1nRSwC2lk8L4ac22kuVhRoWH iRRsNoYQ==; Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uGm7y-0004gv-Sm; Mon, 19 May 2025 00:05:02 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyao@disroot.org, kever.yang@rock-chips.com, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel test robot Subject: [PATCH 1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses Date: Mon, 19 May 2025 00:04:43 +0200 Message-ID: <20250518220449.2722673-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de> References: <20250518220449.2722673-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The rk3576 pcie nodes currently use the apb register as their unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple= _bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expect= ed "22000000" ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple= _bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expect= ed "22400000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@int= el.com/ Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------ 1 file changed, 108 insertions(+), 108 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 79800959b797..3b62e037772a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -466,6 +466,114 @@ soc { #size-cells =3D <2>; ranges; =20 + pcie0: pcie@22000000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg =3D <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + bus-range =3D <0x0 0xf>; + clocks =3D <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy0_ps PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_PHP>; + ranges =3D <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets =3D <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names =3D "pwr", "pipe"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + pcie1: pcie@22400000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg =3D <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + bus-range =3D <0x20 0x2f>; + clocks =3D <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy1_psu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_SUBPHP>; + ranges =3D <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets =3D <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names =3D "pwr", "pipe"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + usb_drd0_dwc3: usb@23000000 { compatible =3D "rockchip,rk3576-dwc3", "snps,dwc3"; reg =3D <0x0 0x23000000 0x0 0x400000>; @@ -1343,114 +1451,6 @@ qos_npu_m1ro: qos@27f22100 { reg =3D <0x0 0x27f22100 0x0 0x20>; }; =20 - pcie0: pcie@2a200000 { - compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; - reg =3D <0x0 0x22000000 0x0 0x00400000>, - <0x0 0x2a200000 0x0 0x00010000>, - <0x0 0x20000000 0x0 0x00100000>; - reg-names =3D "dbi", "apb", "config"; - bus-range =3D <0x0 0xf>; - clocks =3D <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, - <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, - <&cru CLK_PCIE0_AUX>; - clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux"; - device_type =3D "pci"; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - linux,pci-domain =3D <0>; - max-link-speed =3D <2>; - num-ib-windows =3D <8>; - num-viewport =3D <8>; - num-ob-windows =3D <2>; - num-lanes =3D <1>; - phys =3D <&combphy0_ps PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy"; - power-domains =3D <&power RK3576_PD_PHP>; - ranges =3D <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 - 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 - 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; - resets =3D <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names =3D "pwr", "pipe"; - #address-cells =3D <3>; - #size-cells =3D <2>; - status =3D "disabled"; - - pcie0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-parent =3D <&gic>; - interrupts =3D ; - }; - }; - - pcie1: pcie@2a210000 { - compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; - reg =3D <0x0 0x22400000 0x0 0x00400000>, - <0x0 0x2a210000 0x0 0x00010000>, - <0x0 0x21000000 0x0 0x00100000>; - reg-names =3D "dbi", "apb", "config"; - bus-range =3D <0x20 0x2f>; - clocks =3D <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, - <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, - <&cru CLK_PCIE1_AUX>; - clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux"; - device_type =3D "pci"; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - linux,pci-domain =3D <0>; - max-link-speed =3D <2>; - num-ib-windows =3D <8>; - num-viewport =3D <8>; - num-ob-windows =3D <2>; - num-lanes =3D <1>; - phys =3D <&combphy1_psu PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy"; - power-domains =3D <&power RK3576_PD_SUBPHP>; - ranges =3D <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 - 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 - 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; - resets =3D <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names =3D "pwr", "pipe"; - #address-cells =3D <3>; - #size-cells =3D <2>; - status =3D "disabled"; - - pcie1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-parent =3D <&gic>; - interrupts =3D ; - }; - }; - gmac0: ethernet@2a220000 { compatible =3D "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=XxIy6clM; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="XxIy6clM" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=YbcM1bOFMt6WdPHExqK4799CzGHt6PhTiCIlQuVNo5o=; b=XxIy6clMJgBIwEyNeZA5bMadZY HfHalAUEd+mwkWXQsNs7T/Y2nfipGe4tETLYMVWvoBH2J6ggxhO6z7o9/VhjcOcTk8PCIake1OLxV efIzEe61rGf+81NSHcDII5ZdEXV1LDR+exWgNBzv95QyRfY3SUpIK3kDZ6SaMQwBNjvF3iciwu2QC 9ZCBB6Lf+sUN6YASaZqc9yQN9tcEXEWqE5K2BacZ/RdVZS00GRzpo5qEBXWx87QaK1sF9JZBU2CsE UKNrx0Xgx2/vPPSRqO9UYZjzgOBLlTNlKp3sTclqDDZ8O4YsjzU5vFPPQvccTKFdC/eJnWMLlp/ID UGcD8KPQ==; Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uGm7z-0004gv-Cj; Mon, 19 May 2025 00:05:03 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyao@disroot.org, kever.yang@rock-chips.com, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel test robot Subject: [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node Date: Mon, 19 May 2025 00:04:44 +0200 Message-ID: <20250518220449.2722673-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de> References: <20250518220449.2722673-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple= _bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@int= el.com/ Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 3b62e037772a..0e0a37849874 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -429,6 +429,74 @@ simple-audio-card,cpu { }; }; =20 + pinctrl: pinctrl { + compatible =3D "rockchip,rk3576-pinctrl"; + rockchip,grf =3D <&ioc_grf>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpio0: gpio@27320000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0x27320000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@2ae10000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0x2ae10000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@2ae20000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0x2ae20000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@2ae30000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0x2ae30000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@2ae40000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0x2ae40000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + }; + pmu_a53: pmu-a53 { compatible =3D "arm,cortex-a53-pmu"; interrupts =3D , @@ -2347,74 +2415,6 @@ scmi_shmem: scmi-shmem@4010f000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x4010f000 0x0 0x100>; }; - - pinctrl: pinctrl { - compatible =3D "rockchip,rk3576-pinctrl"; - rockchip,grf =3D <&ioc_grf>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - gpio0: gpio@27320000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0x27320000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 0 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio1: gpio@2ae10000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0x2ae10000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 32 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio2: gpio@2ae20000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0x2ae20000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 64 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio3: gpio@2ae30000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0x2ae30000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 96 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio4: gpio@2ae40000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0x2ae40000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 128 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - }; }; }; =20 --=20 2.47.2 From nobody Fri Dec 19 17:19:50 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFD8D1C1F05; Sun, 18 May 2025 22:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605923; cv=none; b=VOIc47JnVZLK9U8isCRBRF4qoiEuvkJ3JodPaXdGleo68p45Sa8rULZIjlDidXDsaIFYBJXOCqnpu9FhC/9AIxklNsDtcYvHThg+M/EO8R+CYna64WCf5p8Y5EZgGBCxDzLQNcTDnEaZc2oqO0egMwBiKihE/hAqs9tJBs0omTo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605923; c=relaxed/simple; bh=3yP7bMH2jkvcANwa5lLh/klZmT0dwOlq2ra0BALxO5k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" Two empty lines between nodes, is one too many. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 0e0a37849874..b6e946e68b09 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -2000,7 +2000,6 @@ i2c5: i2c@2ac80000 { status =3D "disabled"; }; =20 - i2c6: i2c@2ac90000 { compatible =3D "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg =3D <0x0 0x2ac90000 0x0 0x1000>; --=20 2.47.2 From nobody Fri Dec 19 17:19:50 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 578037DA6A; Sun, 18 May 2025 22:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605922; cv=none; b=WZy+GlOkPPrL1ZuCYUVy5G4AhifafI2e/3Ngwu8tA5mCS1Hfp88Zhg4JY+dZkAy7qgmqKyi16MfH5s/ILta0w0R8RyT8hAsxJkfGiit1FJ/kirPxa81ELdIPQNR3W9kWlpjyA47yzmN6YqO8cEGlH3j7QeeQL3gQvzYjs8+DZWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747605922; c=relaxed/simple; bh=NU40cp6KiJ+yXld4sOYhC3plOaqExos+8xMFH+GRwVE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q5GwwJn2+hJCT/h5caCumV0Blkmnk66DgISL05j8e0WgigSc5qCTwnUy5YUtPsuhQSHvfweLloe8fEuNHlbtgoSsyYJa7nsNvHQMLxPByGtZcp6l3ZVwljCZl7rVPvuHHfmb3NWgUZuynX+UCtGA/BUotxyfoLgh6eIvCk4Wx7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=AaF+5M+U; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="AaF+5M+U" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=3vhXblRFFwM/P/okDicuxONQXGTlkPhFwvYUgdAVGKI=; b=AaF+5M+UvBJEspTTK4LVn+ALh8 1tcASx13Vmu96SIhGVcZoqQwS68qSQPmMXWw+DQCIb1gvy9MBuot+KgEdqmLiQ/2JWxUuMEVhSCgW RCrWq6IYtvVYaSxB/Uo9+CQiuY1CahOj+KBDGiS45wDrHvDGX4GoGbnRRZfY48eOIXWB9fGh/rgf0 d72g2mrulIATZXkK89mFQ5qWQY+O8e8kPWKqviIbrCeWT8wjIRw37pkSnW4kveR633QUkk5EVNjbY AsZ7L5eoYjXTpiPdA1VxT+0M53HSZEkr6Cw8SUEHbSS87Ol3UMX42n3yyDJwxdEnntVftpCoJHnvW aq5ibW2Q==; Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uGm80-0004gv-Bq; Mon, 19 May 2025 00:05:04 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyao@disroot.org, kever.yang@rock-chips.com, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node Date: Mon, 19 May 2025 00:04:46 +0200 Message-ID: <20250518220449.2722673-5-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de> References: <20250518220449.2722673-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_b= us_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index b2724c969a76..d1c72b52aa4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -95,6 +95,74 @@ scmi_clk: protocol@14 { }; }; =20 + pinctrl: pinctrl { + compatible =3D "rockchip,rk3528-pinctrl"; + rockchip,grf =3D <&ioc_grf>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff610000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffaf0000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@ffb00000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffb00000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@ffb10000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffb10000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@ffb20000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffb20000 0x0 0x200>; + clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + psci { compatible =3D "arm,psci-1.0", "arm,psci-0.2"; method =3D "smc"; @@ -866,74 +934,6 @@ dmac: dma-controller@ffd60000 { #dma-cells =3D <1>; arm,pl330-periph-burst; }; - - pinctrl: pinctrl { - compatible =3D "rockchip,rk3528-pinctrl"; - rockchip,grf =3D <&ioc_grf>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - gpio0: gpio@ff610000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xff610000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl 0 0 32>; - interrupt-controller; - #interrupt-cells =3D <2>; - }; - - gpio1: gpio@ffaf0000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffaf0000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl 0 32 32>; - interrupt-controller; - #interrupt-cells =3D <2>; - }; - - gpio2: gpio@ffb00000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffb00000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl 0 64 32>; - interrupt-controller; - #interrupt-cells =3D <2>; - }; - - gpio3: gpio@ffb10000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffb10000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl 0 96 32>; - interrupt-controller; - #interrupt-cells =3D <2>; - }; - - gpio4: gpio@ffb20000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffb20000 0x0 0x200>; - clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - interrupts =3D ; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl 0 128 32>; - interrupt-controller; - #interrupt-cells =3D <2>; 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Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uGm80-0004gv-RL; Mon, 19 May 2025 00:05:04 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyao@disroot.org, kever.yang@rock-chips.com, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses Date: Mon, 19 May 2025 00:04:47 +0200 Message-ID: <20250518220449.2722673-6-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de> References: <20250518220449.2722673-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The rk3562 pcie node currently uses the apb register as its unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:624.26-675.5: Warning (simple_b= us_reg): /soc/pcie@ff500000: simple-bus unit address format error, expected= "fe000000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. With the move also move the reg + reg-names below the compatible, as is the preferred position. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 106 +++++++++++------------ 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi index 6268f84efa13..292e82ec5d45 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -249,6 +249,59 @@ soc { #size-cells =3D <2>; ranges; =20 + pcie2x1: pcie@fe000000 { + compatible =3D "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; + reg =3D <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names =3D "dbi", "apb", "config"; + bus-range =3D <0x0 0xff>; + clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power 15>; + ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + resets =3D <&cru SRST_PCIE20_POWERUP>; + reset-names =3D "pipe"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + gic: interrupt-controller@fe901000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <3>; @@ -621,59 +674,6 @@ gpu: gpu@ff320000 { status =3D "disabled"; }; =20 - pcie2x1: pcie@ff500000 { - compatible =3D "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; - bus-range =3D <0x0 0xff>; - clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX>; - clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type =3D "pci"; - interrupts =3D , - , - , - , - , - ; - interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie2x1_intc 0>, - <0 0 0 2 &pcie2x1_intc 1>, - <0 0 0 3 &pcie2x1_intc 2>, - <0 0 0 4 &pcie2x1_intc 3>; - linux,pci-domain =3D <0>; - max-link-speed =3D <2>; - num-ib-windows =3D <8>; - num-viewport =3D <8>; - num-ob-windows =3D <2>; - num-lanes =3D <1>; - phys =3D <&combphy PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy"; - power-domains =3D <&power 15>; - ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 - 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 - 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; - reg =3D <0x0 0xfe000000 0x0 0x400000>, - <0x0 0xff500000 0x0 0x10000>, - <0x0 0xfc000000 0x0 0x100000>; - reg-names =3D "dbi", "apb", "config"; - resets =3D <&cru SRST_PCIE20_POWERUP>; - reset-names =3D "pipe"; - #address-cells =3D <3>; - #size-cells =3D <2>; - status =3D "disabled"; - - pcie2x1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-parent =3D <&gic>; - interrupts =3D ; - }; - }; - spi1: spi@ff640000 { compatible =3D "rockchip,rk3066-spi"; reg =3D <0x0 0xff640000 0x0 0x1000>; --=20 2.47.2 From nobody Fri Dec 19 17:19:50 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFF1C1FBE8C; Sun, 18 May 2025 22:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; 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Mon, 19 May 2025 00:05:05 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyao@disroot.org, kever.yang@rock-chips.com, nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node Date: Mon, 19 May 2025 00:04:48 +0200 Message-ID: <20250518220449.2722673-7-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de> References: <20250518220449.2722673-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple= _bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 136 +++++++++++------------ 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi index 292e82ec5d45..def504ffa326 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -218,6 +218,74 @@ scmi_clk: protocol@14 { }; }; =20 + pinctrl: pinctrl { + compatible =3D "rockchip,rk3562-pinctrl"; + rockchip,grf =3D <&ioc_grf>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff260000 0x0 0x100>; + clocks =3D <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@ff620000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff620000 0x0 0x100>; + clocks =3D <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@ff630000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff630000 0x0 0x100>; + clocks =3D <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@ffac0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffac0000 0x0 0x100>; + clocks =3D <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@ffad0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffad0000 0x0 0x100>; + clocks =3D <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + }; + psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; @@ -1111,74 +1179,6 @@ saradc1: adc@ffaa0000 { #io-channel-cells =3D <1>; status =3D "disabled"; }; - - pinctrl: pinctrl { - compatible =3D "rockchip,rk3562-pinctrl"; - rockchip,grf =3D <&ioc_grf>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - gpio0: gpio@ff260000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xff260000 0x0 0x100>; - clocks =3D <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 0 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio1: gpio@ff620000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xff620000 0x0 0x100>; - clocks =3D <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 32 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio2: gpio@ff630000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xff630000 0x0 0x100>; - clocks =3D <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 64 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio3: gpio@ffac0000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffac0000 0x0 0x100>; - clocks =3D <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 96 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - - gpio4: gpio@ffad0000 { - compatible =3D "rockchip,gpio-bank"; - reg =3D <0x0 0xffad0000 0x0 0x100>; - clocks =3D <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; - gpio-controller; - gpio-ranges =3D <&pinctrl 0 128 32>; - interrupts =3D ; - interrupt-controller; - #gpio-cells =3D <2>; - #interrupt-cells =3D <2>; - }; - }; }; }; =20 --=20 2.47.2