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Sun, 18 May 2025 19:32:21 +0000 (GMT) X-AuditID: b6c32a52-41dfa70000004c16-56-682a35c5e846 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 7C.39.19478.5C53A286; Mon, 19 May 2025 04:32:21 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193218epsmtip14b990810bf80067490cc48b266f28a35~AtfmC8r6v0974409744epsmtip1e; Sun, 18 May 2025 19:32:18 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 01/10] PCI: exynos: Change macro names to exynos specific Date: Mon, 19 May 2025 01:01:43 +0530 Message-ID: <20250518193152.63476-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWy7bCSnO5RU60Mg3nT5S0ezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugSvj44tZTAVrbCt2HF3N1MA427SLkZNDQsBEYsvVFYxdjFwcQgLbGSWubnvFDpGQlPh8 cR0ThC0ssfLfc3aIok+MEp9WrmMESbAJaEk0fu1iBrFFBE4wSvTdsgQpYhZ4zyQxc8EvsG5h AU+Jx03vwIpYBFQlFu+8BWbzClhJbNoxla2LkQNog7xEf4cESJhTwFpi2/qpYK1CQCULn+xk hCgXlDg58wkLiM0MVN68dTbzBEaBWUhSs5CkFjAyrWIUTS0ozk3PTS4w1CtOzC0uzUvXS87P 3cQIjkKtoB2My9b/1TvEyMTBeIhRgoNZSYR31WaNDCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8 yjmdKUIC6YklqdmpqQWpRTBZJg5OqQamGO4Lr65c2XL3yc0Vm4PcGVI4fDf+7LqfseLv5VXi lU9UO6V/LHnAur/67lp3kejFuU/F9WsXsP9ayP+qVPLAJwc1AfV3Z5lfLRTYdrnR6YauzO2j NX9N16eWOppn/5lxr5JRYdJc47xP9zz95VX7NvOK7H6h+tnz4ukHSUF7sr4Kxiam258+tdT7 8bKNxw7OKdbgzw+78aN3ybya+UE3qgXu2dwNmX37h3GQ62pN65tTpd8ZdL7XEPobvnly24vM 2i/53OGWUubNSj9uh3EfepD2op470eGLR9aNg/53bnKwJTl3/Au8rTDPPaGdy+mK4fTCqz1M 2V/UrNdON9ln1evzRDT97FJ+PY2vgtO2K7EUZyQaajEXFScCAL7XumkxAwAA X-CMS-MailID: 20250518193221epcas5p3c648c773d901f18639dd32fa452fd688 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193221epcas5p3c648c773d901f18639dd32fa452fd688 References: <20250518193152.63476-1-shradha.t@samsung.com> Prefix macro names in exynos file with the term "EXYNOS" as the current macro names seem to be generic to PCIe. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 116 ++++++++++++------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index ace736b025b1..1c70b036376d 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -26,30 +26,30 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) =20 /* PCIe ELBI registers */ -#define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT BIT(0) -#define IRQ_INTB_ASSERT BIT(2) -#define IRQ_INTC_ASSERT BIT(4) -#define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_LEVEL 0x004 -#define PCIE_IRQ_SPECIAL 0x008 -#define PCIE_IRQ_EN_PULSE 0x00c -#define PCIE_IRQ_EN_LEVEL 0x010 -#define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_SW_WAKE 0x018 -#define PCIE_BUS_EN BIT(1) -#define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE BIT(0) -#define PCIE_STICKY_RESET 0x020 -#define PCIE_NONSTICKY_RESET 0x024 -#define PCIE_APP_INIT_RESET 0x028 -#define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x074 -#define PCIE_ELBI_XMLH_LINKUP BIT(4) -#define PCIE_ELBI_LTSSM_ENABLE 0x1 -#define PCIE_ELBI_SLV_AWMISC 0x11c -#define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) +#define EXYNOS_PCIE_IRQ_LEVEL 0x004 +#define EXYNOS_PCIE_IRQ_SPECIAL 0x008 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 +#define EXYNOS_PCIE_SW_WAKE 0x018 +#define EXYNOS_PCIE_BUS_EN BIT(1) +#define EXYNOS_PCIE_CORE_RESET 0x01c +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) +#define EXYNOS_PCIE_STICKY_RESET 0x020 +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 struct exynos_pcie { struct dw_pcie pci; @@ -73,49 +73,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exyn= os_pcie *ep, bool on) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); } =20 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool o= n) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); } =20 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val &=3D ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val &=3D ~EXYNOS_PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } =20 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val |=3D PCIE_CORE_RESET_ENABLE; + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val |=3D EXYNOS_PCIE_CORE_RESET_ENABLE; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } =20 static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -123,21 +123,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep =3D to_exynos_pcie(pci); u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &=3D ~PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val &=3D ~EXYNOS_PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); =20 /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } =20 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); } =20 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -150,12 +150,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, v= oid *arg) =20 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + u32 val =3D EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } =20 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -212,9 +212,9 @@ static struct pci_ops exynos_pci_ops =3D { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep =3D to_exynos_pcie(pci); - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP= ); =20 - return (val & PCIE_ELBI_XMLH_LINKUP); + return (val & EXYNOS_PCIE_ELBI_XMLH_LINKUP); } =20 static int exynos_pcie_host_init(struct dw_pcie_rp *pp) --=20 2.49.0