From nobody Fri Dec 19 17:23:31 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E703E267387 for ; Mon, 19 May 2025 09:29:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646953; cv=none; b=Qy3fStpuMVF+1/6qe44ok9U1Ab7oA3S0kVKepHGf3Dj7HepiCgDMCz6SBI7AXfGAObMA0HR1q9B9Qdtd8qGjEhX2oJtXDnam1kBIwmuxKhFJkl0qIQiqWCvP1I1D23uwLNDsKB1Fsq4xnwTpVMkg3Nioe7mYdG/hMun4LnyhvGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646953; c=relaxed/simple; bh=7ABxo1o+iuz7KS3oeJ+a4ETKImt3JwKUnmUjJWWurCg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=isTH72RRRHf33a4qd2M9A5UfDkfpjxpY5utfs/Q904hlPNO2N+Wemxh3PnM35K3kmsxi62OrUWz8iJnKi01RG4LZx4hDMgqM4HHcxmGlAJU51aeM9RxbyPYrYRNHUwuclMu1xRUTzptV7UlTxLmfQBdrXD4QBBSkfXrAxUu3vz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Tt9sQGyN; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Tt9sQGyN" Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250519092907epoutp0370210f655bc428d3b603f5be498a6068~A46O9FyCd2921329213epoutp03Z for ; Mon, 19 May 2025 09:29:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250519092907epoutp0370210f655bc428d3b603f5be498a6068~A46O9FyCd2921329213epoutp03Z DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646947; bh=U4vYel9SC3RXLTELAk4xNUjVAeemDzAM0ckAtX/d39U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tt9sQGyNAWanO5Ka6ujmUULn+ixy7PN+WB0jSOl+MSc0idGBZZqs/dpAJ3y1IYGjR +hNIwKnFiISBtRw91ifeuBAYOrELfVBuD9L0vJgYweBL+Hav0yqB68bRv5NoP3IUSU D5NNO18fvPtxEo9zYpUkoTH4qVdkoIMkayYFc2cE= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250519092906epcas5p2b51cee8b512ed58c44cb88bb885bb095~A46NvruTe0614106141epcas5p22; Mon, 19 May 2025 09:29:06 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.176]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4b1C752B2vz2SSKp; Mon, 19 May 2025 09:29:05 +0000 (GMT) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250518193221epcas5p3c648c773d901f18639dd32fa452fd688~AtfoxwtPt1682016820epcas5p33; Sun, 18 May 2025 19:32:21 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250518193221epsmtrp249aa1fd57cdeba1334d43b2f0dd71757~Atfow8VJD0348003480epsmtrp2a; Sun, 18 May 2025 19:32:21 +0000 (GMT) X-AuditID: b6c32a52-41dfa70000004c16-56-682a35c5e846 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 7C.39.19478.5C53A286; Mon, 19 May 2025 04:32:21 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193218epsmtip14b990810bf80067490cc48b266f28a35~AtfmC8r6v0974409744epsmtip1e; Sun, 18 May 2025 19:32:18 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 01/10] PCI: exynos: Change macro names to exynos specific Date: Mon, 19 May 2025 01:01:43 +0530 Message-ID: <20250518193152.63476-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWy7bCSnO5RU60Mg3nT5S0ezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugSvj44tZTAVrbCt2HF3N1MA427SLkZNDQsBEYsvVFYxdjFwcQgLbGSWubnvFDpGQlPh8 cR0ThC0ssfLfc3aIok+MEp9WrmMESbAJaEk0fu1iBrFFBE4wSvTdsgQpYhZ4zyQxc8EvsG5h AU+Jx03vwIpYBFQlFu+8BWbzClhJbNoxla2LkQNog7xEf4cESJhTwFpi2/qpYK1CQCULn+xk hCgXlDg58wkLiM0MVN68dTbzBEaBWUhSs5CkFjAyrWIUTS0ozk3PTS4w1CtOzC0uzUvXS87P 3cQIjkKtoB2My9b/1TvEyMTBeIhRgoNZSYR31WaNDCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8 yjmdKUIC6YklqdmpqQWpRTBZJg5OqQamGO4Lr65c2XL3yc0Vm4PcGVI4fDf+7LqfseLv5VXi lU9UO6V/LHnAur/67lp3kejFuU/F9WsXsP9ayP+qVPLAJwc1AfV3Z5lfLRTYdrnR6YauzO2j NX9N16eWOppn/5lxr5JRYdJc47xP9zz95VX7NvOK7H6h+tnz4ukHSUF7sr4Kxiam258+tdT7 8bKNxw7OKdbgzw+78aN3ybya+UE3qgXu2dwNmX37h3GQ62pN65tTpd8ZdL7XEPobvnly24vM 2i/53OGWUubNSj9uh3EfepD2op470eGLR9aNg/53bnKwJTl3/Au8rTDPPaGdy+mK4fTCqz1M 2V/UrNdON9ln1evzRDT97FJ+PY2vgtO2K7EUZyQaajEXFScCAL7XumkxAwAA X-CMS-MailID: 20250518193221epcas5p3c648c773d901f18639dd32fa452fd688 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193221epcas5p3c648c773d901f18639dd32fa452fd688 References: <20250518193152.63476-1-shradha.t@samsung.com> Prefix macro names in exynos file with the term "EXYNOS" as the current macro names seem to be generic to PCIe. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 116 ++++++++++++------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index ace736b025b1..1c70b036376d 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -26,30 +26,30 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) =20 /* PCIe ELBI registers */ -#define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT BIT(0) -#define IRQ_INTB_ASSERT BIT(2) -#define IRQ_INTC_ASSERT BIT(4) -#define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_LEVEL 0x004 -#define PCIE_IRQ_SPECIAL 0x008 -#define PCIE_IRQ_EN_PULSE 0x00c -#define PCIE_IRQ_EN_LEVEL 0x010 -#define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_SW_WAKE 0x018 -#define PCIE_BUS_EN BIT(1) -#define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE BIT(0) -#define PCIE_STICKY_RESET 0x020 -#define PCIE_NONSTICKY_RESET 0x024 -#define PCIE_APP_INIT_RESET 0x028 -#define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x074 -#define PCIE_ELBI_XMLH_LINKUP BIT(4) -#define PCIE_ELBI_LTSSM_ENABLE 0x1 -#define PCIE_ELBI_SLV_AWMISC 0x11c -#define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) +#define EXYNOS_PCIE_IRQ_LEVEL 0x004 +#define EXYNOS_PCIE_IRQ_SPECIAL 0x008 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 +#define EXYNOS_PCIE_SW_WAKE 0x018 +#define EXYNOS_PCIE_BUS_EN BIT(1) +#define EXYNOS_PCIE_CORE_RESET 0x01c +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) +#define EXYNOS_PCIE_STICKY_RESET 0x020 +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 struct exynos_pcie { struct dw_pcie pci; @@ -73,49 +73,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exyn= os_pcie *ep, bool on) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); } =20 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool o= n) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); } =20 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val &=3D ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val &=3D ~EXYNOS_PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } =20 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val |=3D PCIE_CORE_RESET_ENABLE; + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val |=3D EXYNOS_PCIE_CORE_RESET_ENABLE; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } =20 static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -123,21 +123,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep =3D to_exynos_pcie(pci); u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &=3D ~PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val &=3D ~EXYNOS_PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); =20 /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } =20 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); } =20 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -150,12 +150,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, v= oid *arg) =20 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + u32 val =3D EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } =20 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -212,9 +212,9 @@ static struct pci_ops exynos_pci_ops =3D { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep =3D to_exynos_pcie(pci); - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP= ); =20 - return (val & PCIE_ELBI_XMLH_LINKUP); + return (val & EXYNOS_PCIE_ELBI_XMLH_LINKUP); } =20 static int exynos_pcie_host_init(struct dw_pcie_rp *pp) --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AAD826FDB9 for ; Mon, 19 May 2025 09:29:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646961; cv=none; b=rUwrMcceaN0KZW0fZnRiaLWFRC+j+nODRB4GunARzJ5/aP7M/N4D7ISucpCQ9df694ggcLkvlJoy3a8umbl4e8pemzoh/o3ray+m2vILdztJfNRXAQhYdtIdi9Is4h5eFW/pHMuPOHypj54wInhXhUjuA2CoumlhP+uzDaLw3SE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646961; c=relaxed/simple; bh=DjgRCEdJ83elEzSvGykMTo6aeQJl5+Vqze7Lag7Gvho=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=CXg+2SYwxC/ZLv1otGlfaxg+IZ1X1XxC6q/Yj9QbjXsalOB0Z72+CewR7LXwyU7DCYn+H4xDd7+FbVS4twQ3SbX3WXls1qfK3Q8ueSUOWe+5pbAljPHsLU4iWZQatxYCYCMQqllfk5+TzQND9b9cpkqNsfcXwN5tOwRjWMXtlso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=L/RVJ+Wm; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="L/RVJ+Wm" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250519092917epoutp03f878eb1458ffce02234f5f5d3c5e4631~A46YABWeu2924629246epoutp03U for ; Mon, 19 May 2025 09:29:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250519092917epoutp03f878eb1458ffce02234f5f5d3c5e4631~A46YABWeu2924629246epoutp03U DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646957; bh=hyCYV5tKTc12SwshmyJzcHUJ5CSInB31JwFZiJ35RyE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L/RVJ+WmnF96JHVNFe0+ng4FE/5lFVX1zpPcfpmzNf6Z/GkFcrcyAVS3WhTpWt2Fe hSHqQHohli5Crd13u3La/XW1wX8F3DH4STiUQKJXdbg9hyzBrLHSPTj0gWcwiC024t lX/7K9u7WpNMdswguMCxZazFOiO92oJspsqb0hto= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250519092916epcas5p1f944d982a0b8d7b7f94b8e9145e1268b~A46XDOp1s1962019620epcas5p15; Mon, 19 May 2025 09:29:16 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.183]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4b1C7G1Yrdz6B9mJ; Mon, 19 May 2025 09:29:14 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250518193230epcas5p3dfb178a6528556c55e9b694ca8f8ad6c~Atfwy15Xp1682016820epcas5p36; Sun, 18 May 2025 19:32:30 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193230epsmtrp184b5daf49957acd8fd047704d2f70457~AtfwyAvh82445124451epsmtrp1b; Sun, 18 May 2025 19:32:30 +0000 (GMT) X-AuditID: b6c32a52-40bff70000004c16-61-682a35ce3ed9 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id FD.39.19478.EC53A286; Mon, 19 May 2025 04:32:30 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193227epsmtip1824ce2e47b768b1b9d1560fcc5809d57~Atft8GoVD0974409744epsmtip1f; Sun, 18 May 2025 19:32:27 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi , Hrishikesh Dileep Subject: [PATCH 02/10] PCI: exynos: Remove unused MACROs in exynos PCI file Date: Mon, 19 May 2025 01:01:44 +0530 Message-ID: <20250518193152.63476-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsWy7bCSnO45U60Mgxc3WSwezNvGZvF30jF2 iyVNGRZr9p5jsph/5Byrxc2zu9ktbvxqY7VY8WUmu8XR1v/MFi9n3WOzaOj5zWqx6fE1VovL u+awWZydd5zNYsKqbywWZ78vYLJo+dPCYrH2yF12i7stnawW//fsYLfoPVxrsfPOCWYHMY/f vyYxeuycdZfdY8GmUo9NqzrZPO5c28Pm8eTKdCaPzUvqPfq2rGL0OPJ1OovH501yAVxRXDYp qTmZZalF+nYJXBlXtq9kKpjDXvG/o5WlgXEWWxcjJ4eEgInEtctnmLsYuTiEBLYzSjz/8IQJ IiEp8fniOihbWGLlv+fsILaQwCdGiaa5FiA2m4CWROPXLmYQW0TgBKNE3y1LkEHMAvOZJRqa v4E1Cwt4S6x495wVxGYRUJWYs70FLM4rYCVx7OlboKEcQAvkJfo7JEDCnALWEtvWT2WC2GUl sfDJTkaIckGJkzOfsIDYzEDlzVtnM09gFJiFJDULSWoBI9MqRtHUguLc9NzkAkO94sTc4tK8 dL3k/NxNjOBo1Arawbhs/V+9Q4xMHIyHGCU4mJVEeFdt1sgQ4k1JrKxKLcqPLyrNSS0+xCjN waIkzquc05kiJJCeWJKanZpakFoEk2Xi4JRqYCpYl/vJ5syNgIY7jZns8a0JIatnvN93/lhE 0LU8Uf1NQdwX7lj+U598WTXZcMWFvD9z1l+KDoo3sHj9w5GVTW3Hvz/6MwSrfTNZ2b/ozfx9 kn/WhdZaoYY/eyJv8B1Qtpqr8fzMqfoZPcIFns3Wp7RsTHa2heilqJb7L2E6Nzf1n2/sCfmP HkZiAeo23o8ybn9v8Xr3dqJ9/s3f0ws43bSrth9KWDYj61iRTIZXSqm4i4BDpOWWlseuO5Nm bT8hG3tjWd22iBn28cVff9w4duMbWx1TZ8kLH7G6XVk7u24zSLUt58qYt9L53P43YXdO1ZUk 6ybNbFTa7DJd12/9zRV1BznUJk22/HTE1uqflxJLcUaioRZzUXEiAOa88Dk1AwAA X-CMS-MailID: 20250518193230epcas5p3dfb178a6528556c55e9b694ca8f8ad6c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193230epcas5p3dfb178a6528556c55e9b694ca8f8ad6c References: <20250518193152.63476-1-shradha.t@samsung.com> Some MACROs are defined in the exynos PCI file but are not used anywhere within the file. Remove such unused MACROs. Suggested-by: Hrishikesh Dileep Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 1c70b036376d..990aaa16b132 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -31,8 +31,6 @@ #define EXYNOS_IRQ_INTB_ASSERT BIT(2) #define EXYNOS_IRQ_INTC_ASSERT BIT(4) #define EXYNOS_IRQ_INTD_ASSERT BIT(6) -#define EXYNOS_PCIE_IRQ_LEVEL 0x004 -#define EXYNOS_PCIE_IRQ_SPECIAL 0x008 #define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F14B270EB6 for ; Mon, 19 May 2025 09:29:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646986; cv=none; b=pBErUchNc0Q2piuabNUqnd04djMGZt5FtAVKUaH1pnBggnfysr4VsqQN0xHCBEkME+rc86gWnslacL79v5zubej7Se1EgG85t1hcXsDqfrqzBvkJ/JkHhL56J8qo0LIeyyYP4HCifLW9mEf9NMe+cTU30OK1y4mOI9r5Z5RtiEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646986; c=relaxed/simple; bh=z56woakeQWmEguUN8M9JLPjizkUMjCSa+ygM7ouEQcI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=dLtgler6JyWXKE0o+bXM2m10G/vWqMeLhTr8+aZnv/YDp9RbNBKVy0w44DzEsuiuEv4YfCXBKig1bdB95RWf/PZwuj9ihdiYWZ+fp51yTEyaIntnJxcRhLCuBraHbivIzdWjDUkraXxrmvoZJYZkmi2bzjGeb6WqVV3YDquKj8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=AcAPtkbV; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="AcAPtkbV" Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250519092935epoutp04f831407a70d2cdaafc6e0b50938714f8~A46ojwcpo1490414904epoutp04H for ; Mon, 19 May 2025 09:29:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250519092935epoutp04f831407a70d2cdaafc6e0b50938714f8~A46ojwcpo1490414904epoutp04H DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646975; bh=l0gwyC5KI+Ug/i3m/cr/xGdP9J34hXTp0M7gsxc71JQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AcAPtkbVqi7jW/uiBCmnf0zRY4qOnaJ0qOdbeFadctiawjNs8GcW/ukuw9jshS/h/ 5aIHg2n8CQyaIwyUd8vAzk4oAvz7Qzt9b79ggomhkWLaJcC7A2rso/ZmYIPVenGeIt bIGzzXFFrV5XRGDqATpchhB+Jrp81WSXoRGFqvTU= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250519092934epcas5p341c3cb1babdd45de3c1a3699bae31c20~A46oEMhQl0672806728epcas5p3E; Mon, 19 May 2025 09:29:34 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.183]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4b1C7d38GGz6B9mL; Mon, 19 May 2025 09:29:33 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250518193235epcas5p4f0bcf581b583a3acf493a20191ad2b00~Atf1u8wx31869918699epcas5p45; Sun, 18 May 2025 19:32:35 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193235epsmtrp196053957f0114c70e0099601128bb08b~Atf1t79n72445124451epsmtrp1c; Sun, 18 May 2025 19:32:35 +0000 (GMT) X-AuditID: b6c32a52-40bff70000004c16-67-682a35d3922b Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 6F.39.19478.3D53A286; Mon, 19 May 2025 04:32:35 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193232epsmtip16453319fe08b323256750a6a7cafd674~Atfy3TlTS1247812478epsmtip1D; Sun, 18 May 2025 19:32:32 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi , Hrishikesh Dileep Subject: [PATCH 03/10] PCI: exynos: Reorder MACROs to maintain consistency Date: Mon, 19 May 2025 01:01:45 +0530 Message-ID: <20250518193152.63476-4-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsWy7bCSnO5lU60Mg59zJS0ezNvGZvF30jF2 iyVNGRZr9p5jsph/5Byrxc2zu9ktbvxqY7VY8WUmu8XR1v/MFi9n3WOzaOj5zWqx6fE1VovL u+awWZydd5zNYsKqbywWZ78vYLJo+dPCYrH2yF12i7stnawW//fsYLfoPVxrsfPOCWYHMY/f vyYxeuycdZfdY8GmUo9NqzrZPO5c28Pm8eTKdCaPzUvqPfq2rGL0OPJ1OovH501yAVxRXDYp qTmZZalF+nYJXBl3PixnLPjJW3FrwVr2BsYv3F2MHBwSAiYS7x7XdTFycQgJbGeU2P9oHXMX IydQXFLi88V1TBC2sMTKf8/ZIYo+MUr8m9HIDpJgE9CSaPzaBdYgInCCUaLvliVIEbPAfGaJ huZvYN3CAl4Se97tBGtgEVCV6Ptxhg3E5hWwkmh/sZ0d4gp5if4OCZAwp4C1xLb1U8FahYBK Fj7ZyQhRLihxcuYTFhCbGai8eets5gmMArOQpGYhSS1gZFrFKJpaUJybnptcYKhXnJhbXJqX rpecn7uJERyNWkE7GJet/6t3iJGJg/EQowQHs5II76rNGhlCvCmJlVWpRfnxRaU5qcWHGKU5 WJTEeZVzOlOEBNITS1KzU1MLUotgskwcnFINTBNZ9h9Nbb5wzGNKe8fJe3r+6kkPjbz39lxv 1jXK/Ffj81xExcM3Vfdw4ALW6XNnxH5/+3Frl8XReV5z1ja2rlgfs7j7QVhSkDK75s1VU8Oc TRjW+8Uxyb0S6BU9sMVp37YJr9R28G2SmHRpWU3JnNXv7W2O3lm90D7CqS4vNdchMSCwo7Ut 9aTGFF5Wrp6QPP05aa+y9DoTnznmvb9x/s66vXOa8kUOKny3dDxUvq84ffUf3uVeXjYOJhzr N7mUdSy9XXpg0vZ1G26cUP9ickhj8nm2ZdNffujdGNG5qOdo1ymhbL8P5uWtmR6+DtrM5elm 7GJT/u/tWumnyWMS8f6YAJPaBM9FgmsMzc/vVGIpzkg01GIuKk4EAOeqv5I1AwAA X-CMS-MailID: 20250518193235epcas5p4f0bcf581b583a3acf493a20191ad2b00 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193235epcas5p4f0bcf581b583a3acf493a20191ad2b00 References: <20250518193152.63476-1-shradha.t@samsung.com> Exynos PCI file follows MACRO definition order where register offset is defined in ascending order and each bit field within the offset is defined right after offset definition. Some MACROs are out of order and so reorder those MACROs to maintain consistency. Suggested-by: Hrishikesh Dileep Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 990aaa16b132..286f4987d56f 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -27,11 +27,11 @@ =20 /* PCIe ELBI registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_IRQ_INTA_ASSERT BIT(0) #define EXYNOS_IRQ_INTB_ASSERT BIT(2) #define EXYNOS_IRQ_INTC_ASSERT BIT(4) #define EXYNOS_IRQ_INTD_ASSERT BIT(6) -#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 #define EXYNOS_PCIE_SW_WAKE 0x018 @@ -42,12 +42,12 @@ #define EXYNOS_PCIE_NONSTICKY_RESET 0x024 #define EXYNOS_PCIE_APP_INIT_RESET 0x028 #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 #define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 -#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 struct exynos_pcie { struct dw_pcie pci; --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4A08270EC1 for ; Mon, 19 May 2025 09:29:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646989; cv=none; b=PfFEEVACaVEjnsy6UO0hmyGc/rtthpWeinPervzz8WnWtELK/lfeq3RZZfMw0/vETPC1hie1wS0Jxw46WRe5JFUNaUDpJIF0UOn24cKJ5QX0eJQpkbzWCp3MFgXd4D07L+jbcGWBS9KoqHLb8oKOGBXhama2oHjdzDYIrlW698A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646989; c=relaxed/simple; bh=/WDsZLzmqchX0wtDj4TXHQs7eT60ZILGBW715ckf7Go=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=nUufwoy6snqG7wEccFwgwx7d95XuGDcnKTojY49maX3ph1OFUSUpFCYIwfxNVBr+OUKqnD2B0ewruysdvxbiYdhCNmDZcmTwHEf6R6Gg60lLF9H/+LiGQTvXtecZzr6R4xWg8TyypI0JzyNhwgpIVDHr/fGwcQ5U2sjcgzb3y/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=m+pb/Pg9; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="m+pb/Pg9" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250519092945epoutp04693811df1e63dcd35b9ef7cccd288d48~A46xoiBjj1490414904epoutp04J for ; Mon, 19 May 2025 09:29:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250519092945epoutp04693811df1e63dcd35b9ef7cccd288d48~A46xoiBjj1490414904epoutp04J DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646985; bh=kri/rf6JyQa2611OX6tgyLofpFbOtaP/i+pbrhIk82I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m+pb/Pg96GLP6EsD0mNwsbJajFPGlab8S4FDbKmBmbeO21wh/t/ZzoEf4+5Ewl8PY hE2/OqyDj8FIXWMa5VuEO2cms3yb8LzfrNc1GD3IarX4U4bo65KgxptJTG8f5Pnmg4 sIJ4EwNF/Mv2avcrsmLZ8mVWPgjgHaKJpAh7OMnU= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250519092944epcas5p30963fd58c3ff137b3485a8519631fbc5~A46w8LK1C2598025980epcas5p36; Mon, 19 May 2025 09:29:44 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.183]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4b1C7p322cz3hhTD; Mon, 19 May 2025 09:29:42 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250518193239epcas5p4cb4112382560f38ad9708e000eb2335f~Atf54DPB01869218692epcas5p44; Sun, 18 May 2025 19:32:39 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193239epsmtrp152a40df9dae4832cff5cfad71e4b6d0e~Atf53Bh3b2445124451epsmtrp1e; Sun, 18 May 2025 19:32:39 +0000 (GMT) X-AuditID: b6c32a29-566fe7000000223e-2a-682a35d78a58 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 92.C1.08766.7D53A286; Mon, 19 May 2025 04:32:39 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193236epsmtip1a2a9de1995dc37a809fae778aa737597~Atf3CuesD1176111761epsmtip1F; Sun, 18 May 2025 19:32:36 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi , Pankaj Dubey Subject: [PATCH 04/10] PCI: exynos: Add platform device private data Date: Mon, 19 May 2025 01:01:46 +0530 Message-ID: <20250518193152.63476-5-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsWy7bCSnO51U60Mg/M7TCwezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPVYtHWL+wW//fsYLfoPVxrsfPOCWYHMY/f vyYxeuycdZfdY8GmUo9NqzrZPO5c28Pm8eTKdCaPzUvqPfq2rGL0OPJ1OovH501yAVxRXDYp qTmZZalF+nYJXBmXemYzF+yWqpj0ZTl7A+NH0S5GTg4JAROJxkPHWbsYuTiEBHYzStz61sMM kZCU+HxxHROELSyx8t9zdoiiT4wSS162sYMk2AS0JBq/doE1iAicYJTou2UJUsQsMItZYua3 HhaQhLCAi0T7jSVgDSwCqhJ7vneDxXkFrCTOzDnD1sXIAbRBXqK/QwIkzClgLbFt/VSwxUJA JQuf7GSEKBeUODnzCVgrM1B589bZzBMYBWYhSc1CklrAyLSKUTK1oDg3PbfYsMAwL7Vcrzgx t7g0L10vOT93EyM4LrU0dzBuX/VB7xAjEwfjIUYJDmYlEd5VmzUyhHhTEiurUovy44tKc1KL DzFKc7AoifOKv+hNERJITyxJzU5NLUgtgskycXBKNTBJ3jbb0f/2823ZD813PxRuWhH1nmO+ +p2nPJarszRDvv2v/n9DwyJqfvDEu5fPcLx2tfxyoUnuUMuxI5ZdmexxM+RcF1ycOvlCZMnG vOzyJb7vd7113xPYXuJexunxxV9qh0uE++WHEkHzi71eM3ScPLa56Z2fgRnHnEflpw4waQvl ufqp6+vm8a86P+WdbnFfHsMTRy3fr9xt8ScXnudevidm7xru5vRJm/w0Cndx1JuGcq/pa+Wp +jr5xmnPV1ubHNZ5yq5ua+Pyjn+W7v4n8N3BiaoJxpvfVpxR3WyqO+kM8+2am4vUZ1/h7CmI tBGZ9JNx8qNPC3VPl81Y+k9zjvqjnafuzJq9fdKZ6a9SlFiKMxINtZiLihMB8uCLLjoDAAA= X-CMS-MailID: 20250518193239epcas5p4cb4112382560f38ad9708e000eb2335f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193239epcas5p4cb4112382560f38ad9708e000eb2335f References: <20250518193152.63476-1-shradha.t@samsung.com> In order to extend this driver to all Samsung manufactured SoCs having DWC PCIe controller, add private data structure which will hold platform device specific information. It holds function ops like DWC host ops, DWC generic ops, and PCI read/write ops which will be used as driver data for different compatibles. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 32 ++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 286f4987d56f..540612e76f4b 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -49,9 +49,16 @@ #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 +struct samsung_pcie_pdata { + struct pci_ops *pci_ops; + const struct dw_pcie_ops *dwc_ops; + const struct dw_pcie_host_ops *host_ops; +}; + struct exynos_pcie { struct dw_pcie pci; void __iomem *elbi_base; + const struct samsung_pcie_pdata *pdata; struct clk_bulk_data *clks; struct phy *phy; struct regulator_bulk_data supplies[2]; @@ -220,7 +227,7 @@ static int exynos_pcie_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct exynos_pcie *ep =3D to_exynos_pcie(pci); =20 - pp->bridge->ops =3D &exynos_pci_ops; + pp->bridge->ops =3D ep->pdata->pci_ops; =20 exynos_pcie_assert_core_reset(ep); =20 @@ -268,7 +275,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, return 0; } =20 -static const struct dw_pcie_ops dw_pcie_ops =3D { +static const struct dw_pcie_ops exynos_dw_pcie_ops =3D { .read_dbi =3D exynos_pcie_read_dbi, .write_dbi =3D exynos_pcie_write_dbi, .link_up =3D exynos_pcie_link_up, @@ -279,6 +286,7 @@ static int exynos_pcie_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct exynos_pcie *ep; + const struct samsung_pcie_pdata *pdata; struct device_node *np =3D dev->of_node; int ret; =20 @@ -286,8 +294,11 @@ static int exynos_pcie_probe(struct platform_device *p= dev) if (!ep) return -ENOMEM; =20 + pdata =3D of_device_get_match_data(dev); + + ep->pdata =3D pdata; ep->pci.dev =3D dev; - ep->pci.ops =3D &dw_pcie_ops; + ep->pci.ops =3D pdata->dwc_ops; =20 ep->phy =3D devm_of_phy_get(dev, np, NULL); if (IS_ERR(ep->phy)) @@ -363,9 +374,9 @@ static int exynos_pcie_resume_noirq(struct device *dev) return ret; =20 /* exynos_pcie_host_init controls ep->phy */ - exynos_pcie_host_init(pp); + ep->pdata->host_ops->init(pp); dw_pcie_setup_rc(pp); - exynos_pcie_start_link(pci); + ep->pdata->dwc_ops->start_link(pci); return dw_pcie_wait_for_link(pci); } =20 @@ -374,8 +385,17 @@ static const struct dev_pm_ops exynos_pcie_pm_ops =3D { exynos_pcie_resume_noirq) }; =20 +static const struct samsung_pcie_pdata exynos_5433_pcie_rc_pdata =3D { + .dwc_ops =3D &exynos_dw_pcie_ops, + .pci_ops =3D &exynos_pci_ops, + .host_ops =3D &exynos_pcie_host_ops, +}; + static const struct of_device_id exynos_pcie_of_match[] =3D { - { .compatible =3D "samsung,exynos5433-pcie", }, + { + .compatible =3D "samsung,exynos5433-pcie", + .data =3D (void *) &exynos_5433_pcie_rc_pdata, + }, { }, }; =20 --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D87F4272E65 for ; Mon, 19 May 2025 09:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646993; cv=none; b=EtoiufJHgj03F/xBLSb6sdMX8xBskdihMUM59j7As4dmfTSMaylHYc2Lp7eWyx7xj3wcIVww/9klGmhNQlNevKW1xs/r+3IN8BmkoNekt7UTxc4AwlmRQs0XfuC/dy5Zr4d5sntJecaFCInbiM9qu7iT/NBJm3k7pd6HnpSx92c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747646993; c=relaxed/simple; bh=/AdAR2zmfTxgJjuDSRgj9DfQJQZviQObHKCQL1nS6B4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=kunjaqO0mU+C+qNNE0TmzZ5x4VYFVEK97uO4Rgc2OL6ZmNHeVAmZ1SwZC8DGRpCL4kD0bUtgN5pwZpzJXCj7Hdfs9Alk7e3ZGJHpV4n4wJT1TnaTtSqNpWUv7AgNeTqJCeZ+pntWK/qsr68RXv845JHNFsLPXT99h4YiPc0x+5E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=SFkk6CRB; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="SFkk6CRB" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250519092950epoutp0432fa9b030328a15a7e04d76711174ac0~A462XZGqB1488614886epoutp04h for ; Mon, 19 May 2025 09:29:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250519092950epoutp0432fa9b030328a15a7e04d76711174ac0~A462XZGqB1488614886epoutp04h DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646990; bh=IJpZcpD1d5dpWvWjfti1Y5L7PqYI+cpCLRPKeNXMOWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SFkk6CRBp7p0yVMucy4fphibWMqhDAvbodTQ+hRY9efZHnzZ0ve/han+HudxaayJy WbiIo6ZiGcqq2hWD8gYTLmh4NI2UOfLF6ptAMQtsUwPvmqxlML4A4X4P4T9Z/Z9Ei9 1/KoWLmXhWwWPBH7H7sHRz+X6Yzrg2Of+1px5kJw= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250519092949epcas5p18bac5ac8e7f810361dce5a8f3353c3c3~A461pcyDX1901519015epcas5p1G; Mon, 19 May 2025 09:29:49 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.176]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4b1C7w29tNz3hhT8; Mon, 19 May 2025 09:29:48 +0000 (GMT) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250518193244epcas5p3cacfbdc3b0e5c32f7a4dd97062a931a4~Atf967Alz0813608136epcas5p3B; Sun, 18 May 2025 19:32:44 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250518193244epsmtrp2c4b02c7e6addaa1a33067c36d4e15b0b~Atf91HOJX0348003480epsmtrp2d; Sun, 18 May 2025 19:32:44 +0000 (GMT) X-AuditID: b6c32a28-460ee70000001e8a-e7-682a35dcde5e Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 8E.5A.07818.CD53A286; Mon, 19 May 2025 04:32:44 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193241epsmtip151108dc988d8d842e0cc851cf61400db~Atf68npNX1247812478epsmtip1F; Sun, 18 May 2025 19:32:40 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi , Pankaj Dubey Subject: [PATCH 05/10] PCI: exynos: Add structure to hold resource operations Date: Mon, 19 May 2025 01:01:47 +0530 Message-ID: <20250518193152.63476-6-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA02ReUiTYRjAe7/b0ehrWb1aaA2UtdJaF28WS6HiC7qMoJLE5vzYJF1jUzvW scyOTTNJw1xhJnatzJzTPIpqLktISyob04U1OyQ00tJqXW4S9N8Pfr/nef54GFx0iQhlUjUZ vE6jSBNTAqKuWRwW1b1Iqp43YiVRT2kdhX6daqFRRbYaXb/TjqHzznYSuX4cJdGVLyU0enDk D476LK8oZMzzkcjm7STRs8ZzFGorfUihAuswgdpGyjCU8zOHQJVOD408OSYSldd+odGf2/U0 OtG8HzV0P8Jjp3C+H6cA12Dx0FyZLZOzWU0U1915m+J6nxdjXE3FQS7fbgWc82sxwQ3ZwjYI EgTLUvi01CxeN1e+XaAuv+OjtS7Z7su2LtIIPkjMIIiB7EI48L2YMgMBI2KbAGwsqiLHRAgc 6riBjfEkePX3e3osGgTQ9eZjIKJYKTz01Yz7OZh9BGC+e4k/wlkLDkuG8wi/mMSuhbWfWwJM sBGww9M8OsAwQjYG5lbE+BGy4fDkcegvgtilsK7qdOCuaLS40NsA/CxkJ8LWkt7AFnw0P1x7 Fi8ArOU/ZflPlQHMCkJ4rT5dla6UaWUafle0XpGuz9SoopU7020g8EqppB4MDGfPdQCMAQ4A GVwcLLTWSNQiYYpiz15etzNJl5nG6x1gGkOIpwqvyraoRKxKkcHv4Hktr/tnMSYo1IjJ4kjP eWL27HuvBd5x7hcGKn89wM4lHNBlnKDXea9FxB2TS2ZJNkzo+iSfti/lbt/q5LiSwrYR9fTO oW+GkM17kxIPmRJDNj3pf5uqPPMudCSae7zcVSCvthc5l2ZXd7xMjFmstGti4sMMrTPBTxO5 cfCkd8KH7wvcubmOCGuEys3q7Wvqtimj4lsju+zTMaOZekoNSkB/7T3K+hG/2fvpVtac/KjN A+Wx40u1fRcrM1c0u8462yfv8qx0rHrp1Rw8XdmpayrEzL68hQmRLRdDL8yP3Wog+pMf3K/J SGs3VDWYyMLB/eLSaipLPss9oym8R2oIDzaJPD0+t7FITOjVCpkU1+kVfwFuNVp5OQMAAA== X-CMS-MailID: 20250518193244epcas5p3cacfbdc3b0e5c32f7a4dd97062a931a4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193244epcas5p3cacfbdc3b0e5c32f7a4dd97062a931a4 References: <20250518193152.63476-1-shradha.t@samsung.com> Some resources might differ based on platforms and we need platform specific functions to initialize or alter them. For better code re-usability, making a separate res_ops which will hold all such function pointers or other resource specific data. Also move common operations for host init into the probe sequence. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 105 ++++++++++++++++++------ 1 file changed, 80 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 540612e76f4b..b122a2ae8681 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -53,6 +53,7 @@ struct samsung_pcie_pdata { struct pci_ops *pci_ops; const struct dw_pcie_ops *dwc_ops; const struct dw_pcie_host_ops *host_ops; + const struct samsung_res_ops *res_ops; }; =20 struct exynos_pcie { @@ -61,7 +62,13 @@ struct exynos_pcie { const struct samsung_pcie_pdata *pdata; struct clk_bulk_data *clks; struct phy *phy; - struct regulator_bulk_data supplies[2]; + struct regulator_bulk_data *supplies; + int supplies_cnt; +}; + +struct samsung_res_ops { + int (*init_regulator)(struct exynos_pcie *ep); + irqreturn_t (*pcie_irq_handler)(int irq, void *arg); }; =20 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -74,6 +81,36 @@ static u32 exynos_pcie_readl(void __iomem *base, u32 reg) return readl(base + reg); } =20 +static int samsung_regulator_enable(struct exynos_pcie *ep) +{ + struct device *dev =3D ep->pci.dev; + int ret; + + if (ep->supplies_cnt =3D=3D 0) + return 0; + + ret =3D devm_regulator_bulk_get(dev, ep->supplies_cnt, ep->supplies); + if (ret) + return ret; + + ret =3D regulator_bulk_enable(ep->supplies_cnt, ep->supplies); + + return ret; +} + +static void samsung_regulator_disable(struct exynos_pcie *ep) +{ + struct device *dev =3D ep->pci.dev; + int ret; + + if (ep->supplies_cnt =3D=3D 0) + return; + + ret =3D regulator_bulk_disable(ep->supplies_cnt, ep->supplies); + if (ret) + dev_warn(dev, "failed to disable regulators: %d\n", ret); +} + static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool o= n) { u32 val; @@ -244,7 +281,23 @@ static const struct dw_pcie_host_ops exynos_pcie_host_= ops =3D { .init =3D exynos_pcie_host_init, }; =20 -static int exynos_add_pcie_port(struct exynos_pcie *ep, +static int exynos_init_regulator(struct exynos_pcie *ep) +{ + struct device *dev =3D ep->pci.dev; + + ep->supplies_cnt =3D 2; + + ep->supplies =3D devm_kcalloc(dev, ep->supplies_cnt, sizeof(*ep->supplies= ), GFP_KERNEL); + if (!ep->supplies) + return -ENOMEM; + + ep->supplies[0].supply =3D "vdd18"; + ep->supplies[1].supply =3D "vdd10"; + + return 0; +} + +static int samsung_irq_init(struct exynos_pcie *ep, struct platform_device *pdev) { struct dw_pcie *pci =3D &ep->pci; @@ -256,22 +309,15 @@ static int exynos_add_pcie_port(struct exynos_pcie *e= p, if (pp->irq < 0) return pp->irq; =20 - ret =3D devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, + ret =3D devm_request_irq(dev, pp->irq, ep->pdata->res_ops->pcie_irq_handl= er, IRQF_SHARED, "exynos-pcie", ep); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; } =20 - pp->ops =3D &exynos_pcie_host_ops; pp->msi_irq[0] =3D -ENODEV; =20 - ret =3D dw_pcie_host_init(pp); - if (ret) { - dev_err(dev, "failed to initialize host\n"); - return ret; - } - return 0; } =20 @@ -282,6 +328,11 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops =3D= { .start_link =3D exynos_pcie_start_link, }; =20 +static const struct samsung_res_ops exynos_res_ops_data =3D { + .init_regulator =3D exynos_init_regulator, + .pcie_irq_handler =3D exynos_pcie_irq_handler, +}; + static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -313,28 +364,31 @@ static int exynos_pcie_probe(struct platform_device *= pdev) if (ret < 0) return ret; =20 - ep->supplies[0].supply =3D "vdd18"; - ep->supplies[1].supply =3D "vdd10"; - ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), - ep->supplies); - if (ret) - return ret; + if (pdata->res_ops && pdata->res_ops->init_regulator) { + ret =3D ep->pdata->res_ops->init_regulator(ep); + if (ret) + return ret; + } =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + ret =3D samsung_regulator_enable(ep); if (ret) return ret; =20 platform_set_drvdata(pdev, ep); - - ret =3D exynos_add_pcie_port(ep, pdev); + ret =3D samsung_irq_init(ep, pdev); + if (ret) + goto fail_regulator; + ep->pci.pp.ops =3D pdata->host_ops; + ret =3D dw_pcie_host_init(&ep->pci.pp); if (ret < 0) - goto fail_probe; + goto fail_phy_init; =20 return 0; =20 -fail_probe: +fail_phy_init: phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); +fail_regulator: + samsung_regulator_disable(ep); =20 return ret; } @@ -347,7 +401,7 @@ static void exynos_pcie_remove(struct platform_device *= pdev) exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + samsung_regulator_disable(ep); } =20 static int exynos_pcie_suspend_noirq(struct device *dev) @@ -357,7 +411,7 @@ static int exynos_pcie_suspend_noirq(struct device *dev) exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + samsung_regulator_disable(ep); =20 return 0; } @@ -369,7 +423,7 @@ static int exynos_pcie_resume_noirq(struct device *dev) struct dw_pcie_rp *pp =3D &pci->pp; int ret; =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + ret =3D samsung_regulator_enable(ep); if (ret) return ret; =20 @@ -389,6 +443,7 @@ static const struct samsung_pcie_pdata exynos_5433_pcie= _rc_pdata =3D { .dwc_ops =3D &exynos_dw_pcie_ops, .pci_ops =3D &exynos_pci_ops, .host_ops =3D &exynos_pcie_host_ops, + .res_ops =3D &exynos_res_ops_data, }; =20 static const struct of_device_id exynos_pcie_of_match[] =3D { --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F3B22741B9 for ; Mon, 19 May 2025 09:29:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647000; cv=none; b=jbPDEoXN6JZkeWyw9erS9PycjV279bh2GLJPylO9jAcAt1w3/MJO1mAgRt4vcW1YsUOwSIp1Ohoiu44BEnazbPk9v6isM0JxFOVhdDrAaJViZh9U/YvhIaGIo/IHRvwES25RCXKIMMEttJymWfC3RviDM2fCzhVWmjfyfMv5loc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647000; c=relaxed/simple; bh=o7E4Ge5+IqmPYeWMzVGgLfbb1jj2dtv2UWR5K2wT+dA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=dy8gxZI6KQQPw9ZX0yXjUiCHqHg5tDWSGEuFvRiH0c408DrYMiGflIFNvAWYXiH+q4/nlk9AFs+i/ISW4itDhIYmQn9rG/bpohQze68UBI78KL1mIMALl5SqaoKe+fDcSM1a09dJDus7lbK+3CIUS8JEjBDQDR5LeS3ICuLjuko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=EjuQ3hlv; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="EjuQ3hlv" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250519092955epoutp01ce9e3cb6042fa250866afe341fd20595~A467lkCPY2776827768epoutp01o for ; Mon, 19 May 2025 09:29:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250519092955epoutp01ce9e3cb6042fa250866afe341fd20595~A467lkCPY2776827768epoutp01o DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747646995; bh=G6bxBd/QHvNMBGkOZD6iu8vb/nuF7pjsH4P9bCfA75s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EjuQ3hlvoeEE2XNt3PjQGUO4dnkZDv1/EbuVeI0wggWL7c87CJZtRF0FUmkHE4QvV 2uAoX1/1lZ5RWdzvMYuFaxhyO4xZW4MpIKf5M4axXah20hzezK3qj3lBVZ6nAaUtPp eaAJmW18cggYQ5QGAWftDKk8+ImSj+jrc37hATf0= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250519092955epcas5p20f3de7692b8000623ede42fec91be7af~A467BsoSp2975829758epcas5p2J; Mon, 19 May 2025 09:29:55 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.177]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4b1C811dHJz6B9mC; Mon, 19 May 2025 09:29:53 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250518193248epcas5p2543146c715eb249ea6c2ce3c78d03b34~AtgB1aqiq2822528225epcas5p2u; Sun, 18 May 2025 19:32:48 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193248epsmtrp14b16d55e1cf09c0fcbcf001d4c29aedf~AtgBpZoXP2445124451epsmtrp1h; Sun, 18 May 2025 19:32:48 +0000 (GMT) X-AuditID: b6c32a29-566fe7000000223e-34-682a35e02254 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 34.C1.08766.0E53A286; Mon, 19 May 2025 04:32:48 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193245epsmtip1d90c3479b8645ecfad9cfb93a33d0c16~Atf_65Vev1176111761epsmtip1H; Sun, 18 May 2025 19:32:45 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 06/10] dt-bindings: PCI: Add bindings support for Tesla FSD SoC Date: Mon, 19 May 2025 01:01:48 +0530 Message-ID: <20250518193152.63476-7-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWy7bCSnO4DU60Mg3dneSwezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugStj0cXdrAUbXSruPb/C0sC4VK+LkZNDQsBEYvvZRawgtpDAbkaJNS9LIeKSEp8vrmOC sIUlVv57zt7FyAVU84lR4ujyFmaQBJuAlkTj1y4wW0TgBKNE3y1LkCJmgfdMEjMX/ALrFhbw l5j6bA0LiM0ioCoxddddxi5GDg5eASuJt/f1QEwJAXmJ/g4JkApOAWuJbeunMkHcYyWx8MlO RhCbV0BQ4uTMJ2BTmIHKm7fOZp7AKDALSWoWktQCRqZVjJKpBcW56bnFhgWGeanlesWJucWl eel6yfm5mxjBkailuYNx+6oPeocYmTgYDzFKcDArifCu2qyRIcSbklhZlVqUH19UmpNafIhR moNFSZxX/EVvipBAemJJanZqakFqEUyWiYNTqoFp8px7U3Nl1e3jn4tFnGy1iMmZdNH7yZxt t0ptTtVcPfKn85dkEVeI8O+100Nc1IpedrRcyPa6GLBN7b93yIaM/bKr7a+GBzjd9XXjOtiw 8caF5OhNDz91xNa5Sl6xYJhwS98lSIe9SXzO/4N7HnNuj/uV1Lyad8v8SfY/fkuXdfCqv7Pa szvq8f1HlVO+epXV2XVLpVexdLLKK/atyDxUPc+o0EH6ZoPRwe032c5/aa3iOvcoNDVs+cUw k91LOGWOCwZudosstTRjf5MbxCKaUrmo4M+7WWHrD+wy/vysYIfNne/Gsy3klspILja9NSFb 9ODF9dc9464Jzdk8O6F/Imdqst7nc7YZ/Aej2ASVWIozEg21mIuKEwHXt3VgMwMAAA== X-CMS-MailID: 20250518193248epcas5p2543146c715eb249ea6c2ce3c78d03b34 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193248epcas5p2543146c715eb249ea6c2ce3c78d03b34 References: <20250518193152.63476-1-shradha.t@samsung.com> Document the PCIe controller device tree bindings for Tesla FSD SoC for both RC and EP. Signed-off-by: Shradha Todi --- .../bindings/pci/samsung,exynos-pcie-ep.yaml | 66 ++++++ .../bindings/pci/samsung,exynos-pcie.yaml | 199 ++++++++++++------ 2 files changed, 198 insertions(+), 67 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pc= ie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.y= aml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml new file mode 100644 index 000000000000..5d4a9067f727 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Endpoint Controller + +maintainers: + - Shradha Todi + +description: |+ + Samsung SoCs PCIe endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +properties: + compatible: + oneOf: + - enum: + - tesla,fsd-pcie-ep + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-pcie-ep + then: + properties: + samsung,syscon-pcie: + description: phandle for system control registers, used to + control signals at system level + + required: + - samsung,syscon-pcie + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcieep0: pcie-ep@16a00000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x16a01000 0x0 0x80>, + <0x0 0x17000000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + phys =3D <&pciephy1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml= b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index f20ed7e709f7..a3803bf0ef84 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -11,78 +11,113 @@ maintainers: - Jaehoon Chung =20 description: |+ - Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + Samsung SoCs PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. =20 -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - properties: compatible: - const: samsung,exynos5433-pcie - - reg: - items: - - description: Data Bus Interface (DBI) registers. - - description: External Local Bus interface (ELBI) registers. - - description: PCIe configuration space region. - - reg-names: - items: - - const: dbi - - const: elbi - - const: config - - interrupts: - maxItems: 1 - - clocks: - items: - - description: PCIe bridge clock - - description: PCIe bus clock - - clock-names: - items: - - const: pcie - - const: pcie_bus - - phys: - maxItems: 1 - - vdd10-supply: - description: - Phandle to a regulator that provides 1.0V power to the PCIe block. - - vdd18-supply: - description: - Phandle to a regulator that provides 1.8V power to the PCIe block. - - num-lanes: - const: 1 - - num-viewport: - const: 3 - -required: - - reg - - reg-names - - interrupts - - "#address-cells" - - "#size-cells" - - "#interrupt-cells" - - interrupt-map - - interrupt-map-mask - - ranges - - bus-range - - device_type - - num-lanes - - num-viewport - - clocks - - clock-names - - phys - - vdd10-supply - - vdd18-supply + oneOf: + - enum: + - samsung,exynos5433-pcie + - tesla,fsd-pcie + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-pcie + then: + properties: + samsung,syscon-pcie: + description: phandle for system control registers, used to + control signals at system level + + required: + - samsung,syscon-pcie + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-pcie + then: + properties: + reg: + items: + - description: controller's own configuration registers + are available. + - description: controller's application logic registers + - description: configuration registers + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: pcie bridge clock + - description: pcie bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + vdd10-supply: + description: + phandle to a regulator that provides 1.0v power to the pcie bl= ock. + + vdd18-supply: + description: + phandle to a regulator that provides 1.8v power to the pcie bl= ock. + + num-lanes: + const: 1 + + num-viewport: + const: 3 + + assigned-clocks: + maxItems: 2 + + assigned-clock-parents: + maxItems: 2 + + assigned-clock-rates: + maxItems: 2 + + required: + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - num-viewport + - clocks + - clock-names + - phys + - vdd10-supply + - vdd18-supply =20 unevaluatedProperties: false =20 @@ -116,4 +151,34 @@ examples: interrupt-map-mask =3D <0 0 0 0>; interrupt-map =3D <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; }; + - | + #include + #include + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcierc0: pcie@16a00000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x17000000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0 0x17001000 0 0x17001000 0 0xffefff>; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + phys =3D <&pciephy1>; + iommu-map =3D <0x0 &smmu_imem 0x0 0x10000>; + iommu-map-mask =3D <0x0>; + }; + }; ... --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F28267B87 for ; Mon, 19 May 2025 09:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647004; cv=none; b=poN3pckzPQXoLsjmB8oz0pHn8Gm77VCPbyoQMvagvxSjROJxhCBsugh36vJwCkNeXgVBgXeUxKzpCt7NiJV7HeXnSRRVPfXHDLJY6A6ck8LFf1novvmAl54EIS5tMBLh2nFSACN/6v0LBW9uVAxOoJh0O7Zko3C1AUeBu5As/YQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647004; c=relaxed/simple; bh=pLpdyLnnLg8RqNMVrQvGnrEx5EzmgLtIkoNdov0Ray0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=EvSmTbNTAGsOryb2MEai+wCYTLq/ABBL0FYSErwADNu6ppFF2erhk8WVy7eeCoIdNLatqo3m6jdoTCVlszSlvTXfRSssyZEOf7FCmQrJS5LftH1zPNL6JS1y7BdV5AySlM+TStuhMAuqfuTMVSaVVt+kQqwLr7CEBH+qbYXyRho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=IvLgBCEl; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="IvLgBCEl" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250519093001epoutp014d7147f4ddadce51bf057193b006ca3b~A47Ain7dT2777527775epoutp01t for ; Mon, 19 May 2025 09:30:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250519093001epoutp014d7147f4ddadce51bf057193b006ca3b~A47Ain7dT2777527775epoutp01t DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747647001; bh=HuTIFNEhjuQ85+QQGzAj+OEG2nYx+LsLsWxFAqZ7y7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IvLgBCEl5pTCow6NOOqjyk6Gmz8F/b/2sdeNFArtgBhv15nlINVfFavUliJs/EWOT fZuunkwRM5gX0G972BkdGNIL8myI5mWSisEf+ES0Ov/9zf99PI4qV9bfTSp6OPUDCV 4Oe3mNf/5ogWJF0M0tugqgwH9fc64pfQ/sLffbpI= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250519093000epcas5p3c547f22a4a3250d09ced6e4c9d37dbc1~A46--ak0E1502815028epcas5p3U; Mon, 19 May 2025 09:30:00 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.182]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4b1C863Wsfz6B9m4; Mon, 19 May 2025 09:29:58 +0000 (GMT) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250518193252epcas5p3e4d1d329f1e5616e842801ceb26728b6~AtgF5nFzO0813608136epcas5p3D; Sun, 18 May 2025 19:32:52 +0000 (GMT) Received: from epsmgms1p2new.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250518193252epsmtrp2afa5e6b63a5605d32da707ac5717baef~AtgF4rZI70226302263epsmtrp2b; Sun, 18 May 2025 19:32:52 +0000 (GMT) X-AuditID: b6c32a2a-d63ff70000002265-dc-682a35e4c1eb Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 16.6B.08805.4E53A286; Mon, 19 May 2025 04:32:52 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193249epsmtip1c2eae81d2f215bb8b46b8b517bb25941~AtgCoIpr01176111761epsmtip1I; Sun, 18 May 2025 19:32:49 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC Date: Mon, 19 May 2025 01:01:49 +0530 Message-ID: <20250518193152.63476-8-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWy7bCSnO4TU60Mg2lXuCwezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugSuj/fV0poId7BXfj09ibWDsYuti5OSQEDCR6Pr7nbGLkYtDSGA3o8T+SbdZIRKSEp8v rmOCsIUlVv57zg5iCwl8YpTYfj4ZxGYT0JJo/NrFDGKLCJxglOi7ZQkyiFngPZPEzAW/wJqF BXwlrrzbAGazCKhK7HnbztLFyMHBK2Al8aG7GsSUEJCX6O+QAKngFLCW2LZ+KhPEKiuJhU92 MoLYvAKCEidnPmEBsZmBypu3zmaewCgwC0lqFpLUAkamVYySqQXFuem5xYYFRnmp5XrFibnF pXnpesn5uZsYwZGopbWDcc+qD3qHGJk4GA8xSnAwK4nwrtqskSHEm5JYWZValB9fVJqTWnyI UZqDRUmc99vr3hQhgfTEktTs1NSC1CKYLBMHp1QDE6vGcv9Wqw0nbHbsjLePvrcp82FWTYj6 lfmS91a0FCTJ3nwg9He/FOPnptxOl6s2vqKXn3AEb+486bBm5blFahdkVMrTZq66HKf6Yek1 7d3nPQTO5nhP31r+85N94frIorMfrx+LiTnokOBsfV/npvtOj86mfWzLF2ZNuHD5VkrF0+9l /Knf257XvxfmuzKFgbGq9F/B3wf+52927NHdUPGjfa2j1alzPjzpCgcd8vsNtonmXDjq8PhN o8GvC68OR0xdd1508qfU7siH1+98POt2mzNr7onpZoJmErsUBX8VlVeeDP/xpDhL3CH6MR+j WdVLQZOJG/20b5zdk77utOeR0lgjs3uW+vFR3zjd2pVYijMSDbWYi4oTAV1WeJEzAwAA X-CMS-MailID: 20250518193252epcas5p3e4d1d329f1e5616e842801ceb26728b6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193252epcas5p3e4d1d329f1e5616e842801ceb26728b6 References: <20250518193152.63476-1-shradha.t@samsung.com> Document PHY device tree bindings for Tesla FSD SoCs. Signed-off-by: Shradha Todi --- .../devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml index 41df8bb08ff7..3a5bff0fb82d 100644 --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -15,10 +15,14 @@ properties: const: 0 =20 compatible: - const: samsung,exynos5433-pcie-phy + oneOf: + - enum: + - samsung,exynos5433-pcie-phy + - tesla,fsd-pcie-phy =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEFB32749E3 for ; Mon, 19 May 2025 09:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647008; cv=none; b=BlnwpM801IUSOvyU06fO94DYfK3D4K2C+Bi3ptRHJk3Cl6Xrt4KoqOTox7G6TS5of6zPt6WqFDBTxq0NWfEYj5d8rjhJSXiGp2n7MKVhDH5EEBU9Qgh4oJdABYIdU8I0/KvbcU4GN2u68dn7BZvMbv0vYJQ5C48OX2l7hDHkKis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647008; c=relaxed/simple; bh=LsdDmyooRiDAt3n62XYKpA4Gb2KJcx8x78g7yFgQiLk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=OBY/e1AT/vewOo39pWR1h3d2O3ZaYornqCM+WZP1sEPv+6xVJxRRgVjhZGaJL/S7G1OATkYmyeC0uUrvCd4SfcLwMXpCMZwCqlKednZiq6nKq5Y64dTP/0pvqPhPwRY+05SamHL4noWoeCaBlVmJN0Pe/O+EXiCqnRfDwQSewp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=BP/27H7Q; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="BP/27H7Q" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250519093004epoutp02d3ca9b4ae8c5ab7cb1e49d1ac44c3caf~A47EMtM_C0853008530epoutp02Q for ; Mon, 19 May 2025 09:30:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250519093004epoutp02d3ca9b4ae8c5ab7cb1e49d1ac44c3caf~A47EMtM_C0853008530epoutp02Q DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747647005; bh=K21TW+apj+UqDGFEskJE4tHm+9u+Y6333ZdWE6ryTJE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BP/27H7Qnmwc0B1w26FHupRX3cMpDcLFsuh9LeGRicdo2Lm4j+TautLCTnIq9ev3M Ns5ed2F7XzDjhZkcF9V2GY4vKSOpny9cbcatkvi0qvVY+muyQrAnX/xof/LRGoNlDu CwsBcR8ITrBYC4dW94Z5/CumUocUjcKED9X+zQaY= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250519093004epcas5p34809d4f6059d5c87f08a388fadf386d4~A47DggzMH1987119871epcas5p3M; Mon, 19 May 2025 09:30:04 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.175]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4b1C8B65dLz6B9mJ; Mon, 19 May 2025 09:30:02 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250518193256epcas5p442e9549fd8fd810522f960df74c22e34~AtgI8aQmL1869218692epcas5p4-; Sun, 18 May 2025 19:32:56 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193256epsmtrp1f5221d236c680a2c817e0debfbab93c3~AtgI7VQZb2445124451epsmtrp1k; Sun, 18 May 2025 19:32:56 +0000 (GMT) X-AuditID: b6c32a28-460ee70000001e8a-f5-682a35e7f176 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 60.6A.07818.7E53A286; Mon, 19 May 2025 04:32:55 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193253epsmtip1f2d2241ae535c7ecf6713ef003408cf5~AtgGKaxM41176111761epsmtip1K; Sun, 18 May 2025 19:32:53 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 08/10] phy: exynos: Add PCIe PHY support for FSD SoC Date: Mon, 19 May 2025 01:01:50 +0530 Message-ID: <20250518193152.63476-9-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsWy7bCSnO5zU60Mg+d/bSwezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugStj7oJTjAXTqyuO/Z7I2MB4MLuLkZNDQsBEYv+Co8xdjFwcQgK7GSX+/JvHBJGQlPh8 cR2ULSyx8t9zdoiiT4wSbxftAUuwCWhJNH7tYgaxRQROMEr03bIEKWIWeM8kMXPBL7AiYQEX iaYnv1lBbBYBVYnJR5cwdjFycPAKWEl8vZcHYkoIyEv0d0iAVHAKWEtsWz8VrFMIqGLhk52M IDavgKDEyZlPWEBsZqDy5q2zmScwCsxCkpqFJLWAkWkVo2RqQXFuem6yYYFhXmq5XnFibnFp Xrpecn7uJkZwLGpp7GB8961J/xAjEwfjIUYJDmYlEd5VmzUyhHhTEiurUovy44tKc1KLDzFK c7AoifOuNIxIFxJITyxJzU5NLUgtgskycXBKNTDlsnplz/r04YZ7Wvu1d5NLKpN1Ihs6EtO0 fxaffrR2GlOWxb1C9c7287t5q9skFixdK+zJV/Rj4obMjKNapzffknu8erqxk0LGkyfxF5VM xPVfVi9ammHjaCnTPnO3ck7olr9vTO8t+dQ8U4tXqnK64/MCp5ZvVb8MDjXH1H30tl2/wqek 02JuHUvC5v2fGRjO/JtXXrOQ75/HZOFlQZMVVfXmma9dUszhJlrzSIJ19v1j1Y/Mp/c8Fb9g taz23pWbuzS/BN3+96RxT7HJg6pP18tyfSYxvn195mBHbblCpnuGuO4GkyeTt+88xF9sqHn0 qP5JdtHAhmcROv0BQseeKocn9k66tPPFg3//9zgrsRRnJBpqMRcVJwIApTLP+zQDAAA= X-CMS-MailID: 20250518193256epcas5p442e9549fd8fd810522f960df74c22e34 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193256epcas5p442e9549fd8fd810522f960df74c22e34 References: <20250518193152.63476-1-shradha.t@samsung.com> Add PCIe PHY support for Tesla FSD SoC. Signed-off-by: Shradha Todi --- drivers/phy/samsung/phy-exynos-pcie.c | 357 +++++++++++++++++++++++++- 1 file changed, 356 insertions(+), 1 deletion(-) diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/ph= y-exynos-pcie.c index 53c9230c2907..0e4c00c1121e 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -34,11 +34,121 @@ /* PMU PCIE PHY isolation control */ #define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730 =20 +/* FSD: PCIe PHY common registers */ +#define FSD_PCIE_PHY_TRSV_CMN_REG03 0x000c +#define FSD_PCIE_PHY_TRSV_CMN_REG01E 0x0078 +#define FSD_PCIE_PHY_TRSV_CMN_REG02D 0x00b4 +#define FSD_PCIE_PHY_TRSV_CMN_REG031 0x00c4 +#define FSD_PCIE_PHY_TRSV_CMN_REG036 0x00d8 +#define FSD_PCIE_PHY_TRSV_CMN_REG05F 0x017c +#define FSD_PCIE_PHY_TRSV_CMN_REG060 0x0180 +#define FSD_PCIE_PHY_TRSV_CMN_REG062 0x0188 +#define FSD_PCIE_PHY_TRSV_CMN_REG061 0x0184 +#define FSD_PCIE_PHY_AGG_BIF_RESET 0x0200 +#define FSD_PCIE_PHY_AGG_BIF_CLOCK 0x0208 +#define FSD_PCIE_PHY_CMN_RESET 0x0228 + +/* FSD: PCIe PHY lane registers */ +#define FSD_PCIE_PHY_LANE_OFFSET 0x400 +#define FSD_PCIE_PHY_TRSV_REG001_LN_N 0x404 +#define FSD_PCIE_PHY_TRSV_REG002_LN_N 0x408 +#define FSD_PCIE_PHY_TRSV_REG005_LN_N 0x414 +#define FSD_PCIE_PHY_TRSV_REG006_LN_N 0x418 +#define FSD_PCIE_PHY_TRSV_REG007_LN_N 0x41c +#define FSD_PCIE_PHY_TRSV_REG009_LN_N 0x424 +#define FSD_PCIE_PHY_TRSV_REG00A_LN_N 0x428 +#define FSD_PCIE_PHY_TRSV_REG00C_LN_N 0x430 +#define FSD_PCIE_PHY_TRSV_REG012_LN_N 0x448 +#define FSD_PCIE_PHY_TRSV_REG013_LN_N 0x44c +#define FSD_PCIE_PHY_TRSV_REG014_LN_N 0x450 +#define FSD_PCIE_PHY_TRSV_REG015_LN_N 0x454 +#define FSD_PCIE_PHY_TRSV_REG016_LN_N 0x458 +#define FSD_PCIE_PHY_TRSV_REG018_LN_N 0x460 +#define FSD_PCIE_PHY_TRSV_REG020_LN_N 0x480 +#define FSD_PCIE_PHY_TRSV_REG026_LN_N 0x498 +#define FSD_PCIE_PHY_TRSV_REG029_LN_N 0x4a4 +#define FSD_PCIE_PHY_TRSV_REG031_LN_N 0x4c4 +#define FSD_PCIE_PHY_TRSV_REG036_LN_N 0x4d8 +#define FSD_PCIE_PHY_TRSV_REG039_LN_N 0x4e4 +#define FSD_PCIE_PHY_TRSV_REG03B_LN_N 0x4ec +#define FSD_PCIE_PHY_TRSV_REG03C_LN_N 0x4f0 +#define FSD_PCIE_PHY_TRSV_REG03E_LN_N 0x4f8 +#define FSD_PCIE_PHY_TRSV_REG03F_LN_N 0x4fc +#define FSD_PCIE_PHY_TRSV_REG043_LN_N 0x50c +#define FSD_PCIE_PHY_TRSV_REG044_LN_N 0x510 +#define FSD_PCIE_PHY_TRSV_REG046_LN_N 0x518 +#define FSD_PCIE_PHY_TRSV_REG048_LN_N 0x520 +#define FSD_PCIE_PHY_TRSV_REG049_LN_N 0x524 +#define FSD_PCIE_PHY_TRSV_REG04E_LN_N 0x538 +#define FSD_PCIE_PHY_TRSV_REG052_LN_N 0x548 +#define FSD_PCIE_PHY_TRSV_REG068_LN_N 0x5a0 +#define FSD_PCIE_PHY_TRSV_REG069_LN_N 0x5a4 +#define FSD_PCIE_PHY_TRSV_REG06A_LN_N 0x5a8 +#define FSD_PCIE_PHY_TRSV_REG06B_LN_N 0x5ac +#define FSD_PCIE_PHY_TRSV_REG07B_LN_N 0x5ec +#define FSD_PCIE_PHY_TRSV_REG083_LN_N 0x60c +#define FSD_PCIE_PHY_TRSV_REG084_LN_N 0x610 +#define FSD_PCIE_PHY_TRSV_REG086_LN_N 0x618 +#define FSD_PCIE_PHY_TRSV_REG087_LN_N 0x61c +#define FSD_PCIE_PHY_TRSV_REG08B_LN_N 0x62c +#define FSD_PCIE_PHY_TRSV_REG09C_LN_N 0x670 +#define FSD_PCIE_PHY_TRSV_REG09D_LN_N 0x674 +#define FSD_PCIE_PHY_TRSV_REG09E_LN_N 0x678 +#define FSD_PCIE_PHY_TRSV_REG09F_LN_N 0x67c +#define FSD_PCIE_PHY_TRSV_REG0A2_LN_N 0x688 +#define FSD_PCIE_PHY_TRSV_REG0A4_LN_N 0x690 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_N 0x738 +#define FSD_PCIE_PHY_TRSV_REG0FC_LN_N 0x7f0 +#define FSD_PCIE_PHY_TRSV_REG0FD_LN_N 0x7f4 +#define FSD_PCIE_PHY_TRSV_REG0FE_LN_N 0x7f8 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_1 0xb38 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_2 0xf38 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_3 0x1338 + +/* FSD: PCIe PCS registers */ +#define FSD_PCIE_PCS_BRF_0 0x0004 +#define FSD_PCIE_PCS_BRF_1 0x0804 +#define FSD_PCIE_PCS_CLK 0x0180 + +/* FSD: PCIe SYSREG registers */ +#define FSD_PCIE_SYSREG_PHY_0_CON_MASK 0x3ff +#define FSD_PCIE_SYSREG_PHY_0_CON 0x042C +#define FSD_PCIE_SYSREG_PHY_0_REF_SEL_MASK 0x3 +#define FSD_PCIE_SYSREG_PHY_0_REF_SEL (0x2 << 0) +#define FSD_PCIE_SYSREG_PHY_0_SSC_EN_MASK 0x8 +#define FSD_PCIE_SYSREG_PHY_0_SSC_EN BIT(3) +#define FSD_PCIE_SYSREG_PHY_0_AUX_EN_MASK 0x10 +#define FSD_PCIE_SYSREG_PHY_0_AUX_EN BIT(4) +#define FSD_PCIE_SYSREG_PHY_0_CMN_RSTN_MASK 0x100 +#define FSD_PCIE_SYSREG_PHY_0_CMN_RSTN BIT(8) +#define FSD_PCIE_SYSREG_PHY_0_INIT_RSTN_MASK 0x200 +#define FSD_PCIE_SYSREG_PHY_0_INIT_RSTN BIT(9) + +#define FSD_PCIE_SYSREG_PHY_1_CON_MASK 0x1ff +#define FSD_PCIE_SYSREG_PHY_1_CON 0x0500 +#define FSD_PCIE_SYSREG_PHY_1_REF_SEL_MASK 0x30 +#define FSD_PCIE_SYSREG_PHY_1_REF_SEL (0x2 << 4) +#define FSD_PCIE_SYSREG_PHY_1_SSC_EN_MASK 0x80 +#define FSD_PCIE_SYSREG_PHY_1_SSC_EN BIT(7) +#define FSD_PCIE_SYSREG_PHY_1_AUX_EN_MASK 0x1 +#define FSD_PCIE_SYSREG_PHY_1_AUX_EN BIT(0) +#define FSD_PCIE_SYSREG_PHY_1_CMN_RSTN_MASK 0x2 +#define FSD_PCIE_SYSREG_PHY_1_CMN_RSTN BIT(1) +#define FSD_PCIE_SYSREG_PHY_1_INIT_RSTN_MASK 0x8 +#define FSD_PCIE_SYSREG_PHY_1_INIT_RSTN BIT(3) + /* For Exynos pcie phy */ struct exynos_pcie_phy { void __iomem *base; + void __iomem *pcs_base; struct regmap *pmureg; struct regmap *fsysreg; + int phy_id; + const struct samsung_drv_data *drv_data; +}; + +struct samsung_drv_data { + const struct phy_ops *phy_ops; }; =20 static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) @@ -133,9 +243,244 @@ static const struct phy_ops exynos5433_phy_ops =3D { .owner =3D THIS_MODULE, }; =20 +struct fsd_pcie_phy_pdata { + u32 phy_con_mask; + u32 phy_con; + u32 phy_ref_sel_mask; + u32 phy_ref_sel; + u32 phy_ssc_en_mask; + u32 phy_ssc_en; + u32 phy_aux_en_mask; + u32 phy_aux_en; + u32 phy_cmn_rstn_mask; + u32 phy_cmn_rstn; + u32 phy_init_rstn_mask; + u32 phy_init_rstn; + u32 num_lanes; + u32 lane_offset; +}; + +struct fsd_pcie_phy_pdata fsd_phy_con[] =3D { + { + .phy_con =3D FSD_PCIE_SYSREG_PHY_0_CON, + .phy_con_mask =3D FSD_PCIE_SYSREG_PHY_0_CON_MASK, + .phy_ref_sel_mask =3D FSD_PCIE_SYSREG_PHY_0_REF_SEL_MASK, + .phy_ref_sel =3D FSD_PCIE_SYSREG_PHY_0_REF_SEL, + .phy_ssc_en_mask =3D FSD_PCIE_SYSREG_PHY_0_SSC_EN_MASK, + .phy_ssc_en =3D FSD_PCIE_SYSREG_PHY_0_SSC_EN, + .phy_aux_en_mask =3D FSD_PCIE_SYSREG_PHY_0_AUX_EN_MASK, + .phy_aux_en =3D FSD_PCIE_SYSREG_PHY_0_AUX_EN, + .phy_cmn_rstn_mask =3D FSD_PCIE_SYSREG_PHY_0_CMN_RSTN_MASK, + .phy_cmn_rstn =3D FSD_PCIE_SYSREG_PHY_0_CMN_RSTN, + .phy_init_rstn_mask =3D FSD_PCIE_SYSREG_PHY_0_INIT_RSTN_MASK, + .phy_init_rstn =3D FSD_PCIE_SYSREG_PHY_0_INIT_RSTN, + .num_lanes =3D 0x4, + .lane_offset =3D FSD_PCIE_PHY_LANE_OFFSET, + }, + { + .phy_con =3D FSD_PCIE_SYSREG_PHY_1_CON, + .phy_con_mask =3D FSD_PCIE_SYSREG_PHY_1_CON_MASK, + .phy_ref_sel_mask =3D FSD_PCIE_SYSREG_PHY_1_REF_SEL_MASK, + .phy_ref_sel =3D FSD_PCIE_SYSREG_PHY_1_REF_SEL, + .phy_ssc_en_mask =3D FSD_PCIE_SYSREG_PHY_1_SSC_EN_MASK, + .phy_ssc_en =3D FSD_PCIE_SYSREG_PHY_1_SSC_EN, + .phy_aux_en_mask =3D FSD_PCIE_SYSREG_PHY_1_AUX_EN_MASK, + .phy_aux_en =3D FSD_PCIE_SYSREG_PHY_1_AUX_EN, + .phy_cmn_rstn_mask =3D FSD_PCIE_SYSREG_PHY_1_CMN_RSTN_MASK, + .phy_cmn_rstn =3D FSD_PCIE_SYSREG_PHY_1_CMN_RSTN, + .phy_init_rstn_mask =3D FSD_PCIE_SYSREG_PHY_1_INIT_RSTN_MASK, + .phy_init_rstn =3D FSD_PCIE_SYSREG_PHY_1_INIT_RSTN, + .num_lanes =3D 0x4, + .lane_offset =3D FSD_PCIE_PHY_LANE_OFFSET, + }, + { }, +}; + +struct fsd_pcie_phy_setting { + u32 addr; + u32 val; + bool is_cmn_reg; +}; + +struct fsd_pcie_phy_setting fsd_pcie_phy0_setting[] =3D { + {FSD_PCIE_PHY_TRSV_REG07B_LN_N, 0x20, false}, + {FSD_PCIE_PHY_TRSV_REG052_LN_N, 0x00, false}, + {FSD_PCIE_PHY_TRSV_CMN_REG05F, 0x11, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG060, 0x23, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG062, 0x0, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG03, 0x15, true}, + {FSD_PCIE_PHY_TRSV_REG0CE_LN_N, 0x8, false}, + {FSD_PCIE_PHY_TRSV_REG039_LN_N, 0xf, false}, + {FSD_PCIE_PHY_TRSV_REG03B_LN_N, 0x13, false}, + {FSD_PCIE_PHY_TRSV_REG03C_LN_N, 0xf6, false}, + {FSD_PCIE_PHY_TRSV_REG044_LN_N, 0x57, false}, + {FSD_PCIE_PHY_TRSV_REG03E_LN_N, 0x10, false}, + {FSD_PCIE_PHY_TRSV_REG03F_LN_N, 0x04, false}, + {FSD_PCIE_PHY_TRSV_REG043_LN_N, 0x11, false}, + {FSD_PCIE_PHY_TRSV_REG049_LN_N, 0x6f, false}, + {FSD_PCIE_PHY_TRSV_REG04E_LN_N, 0x18, false}, + {FSD_PCIE_PHY_TRSV_REG068_LN_N, 0x1f, false}, + {FSD_PCIE_PHY_TRSV_REG069_LN_N, 0xc, false}, + {FSD_PCIE_PHY_TRSV_REG06B_LN_N, 0x78, false}, + {FSD_PCIE_PHY_TRSV_REG083_LN_N, 0xa, false}, + {FSD_PCIE_PHY_TRSV_REG084_LN_N, 0x80, false}, + {FSD_PCIE_PHY_TRSV_REG086_LN_N, 0xff, false}, + {FSD_PCIE_PHY_TRSV_REG087_LN_N, 0x3c, false}, + {FSD_PCIE_PHY_TRSV_REG09D_LN_N, 0x7c, false}, + {FSD_PCIE_PHY_TRSV_REG09E_LN_N, 0x33, false}, + {FSD_PCIE_PHY_TRSV_REG09F_LN_N, 0x33, false}, + {FSD_PCIE_PHY_TRSV_REG001_LN_N, 0x3f, false}, + {FSD_PCIE_PHY_TRSV_REG002_LN_N, 0x1c, false}, + {FSD_PCIE_PHY_TRSV_REG005_LN_N, 0x2b, false}, + {FSD_PCIE_PHY_TRSV_REG006_LN_N, 0x3, false}, + {FSD_PCIE_PHY_TRSV_REG007_LN_N, 0x0c, false}, + {FSD_PCIE_PHY_TRSV_REG009_LN_N, 0x10, false}, + {FSD_PCIE_PHY_TRSV_REG00A_LN_N, 0x1, false}, + {FSD_PCIE_PHY_TRSV_REG00C_LN_N, 0x93, false}, + {FSD_PCIE_PHY_TRSV_REG012_LN_N, 0x1, false}, + {FSD_PCIE_PHY_TRSV_REG013_LN_N, 0x0, false}, + {FSD_PCIE_PHY_TRSV_REG014_LN_N, 0x70, false}, + {FSD_PCIE_PHY_TRSV_REG015_LN_N, 0x0, false}, + {FSD_PCIE_PHY_TRSV_REG016_LN_N, 0x70, false}, + {FSD_PCIE_PHY_TRSV_REG0FC_LN_N, 0x80, false}, + {FSD_PCIE_PHY_TRSV_REG0FD_LN_N, 0x0, false}, +}; + +struct fsd_pcie_phy_setting fsd_pcie_phy1_setting[] =3D { + {FSD_PCIE_PHY_TRSV_REG07B_LN_N, 0x20, false}, + {FSD_PCIE_PHY_TRSV_REG052_LN_N, 0x00, false}, + {FSD_PCIE_PHY_TRSV_CMN_REG01E, 0xaa, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG02D, 0x28, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG031, 0x28, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG036, 0x21, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG05F, 0x12, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG060, 0x23, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG061, 0x0, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG062, 0x0, true}, + {FSD_PCIE_PHY_TRSV_CMN_REG03, 0x15, true}, + {FSD_PCIE_PHY_TRSV_REG039_LN_N, 0xf, false}, + {FSD_PCIE_PHY_TRSV_REG03B_LN_N, 0x13, false}, + {FSD_PCIE_PHY_TRSV_REG03C_LN_N, 0x66, false}, + {FSD_PCIE_PHY_TRSV_REG044_LN_N, 0x57, false}, + {FSD_PCIE_PHY_TRSV_REG03E_LN_N, 0x10, false}, + {FSD_PCIE_PHY_TRSV_REG03F_LN_N, 0x44, false}, + {FSD_PCIE_PHY_TRSV_REG043_LN_N, 0x11, false}, + {FSD_PCIE_PHY_TRSV_REG046_LN_N, 0xef, false}, + {FSD_PCIE_PHY_TRSV_REG048_LN_N, 0x06, false}, + {FSD_PCIE_PHY_TRSV_REG049_LN_N, 0xaf, false}, + {FSD_PCIE_PHY_TRSV_REG04E_LN_N, 0x28, false}, + {FSD_PCIE_PHY_TRSV_REG068_LN_N, 0x1f, false}, + {FSD_PCIE_PHY_TRSV_REG069_LN_N, 0xc, false}, + {FSD_PCIE_PHY_TRSV_REG06A_LN_N, 0x8, false}, + {FSD_PCIE_PHY_TRSV_REG06B_LN_N, 0x78, false}, + {FSD_PCIE_PHY_TRSV_REG083_LN_N, 0xa, false}, + {FSD_PCIE_PHY_TRSV_REG084_LN_N, 0x80, false}, + {FSD_PCIE_PHY_TRSV_REG087_LN_N, 0x30, false}, + {FSD_PCIE_PHY_TRSV_REG08B_LN_N, 0xa0, false}, + {FSD_PCIE_PHY_TRSV_REG09C_LN_N, 0xf7, false}, + {FSD_PCIE_PHY_TRSV_REG09E_LN_N, 0x33, false}, + {FSD_PCIE_PHY_TRSV_REG0A2_LN_N, 0xfa, false}, + {FSD_PCIE_PHY_TRSV_REG0A4_LN_N, 0xf2, false}, + {FSD_PCIE_PHY_TRSV_REG0CE_LN_N, 0x08, true}, + {FSD_PCIE_PHY_TRSV_REG0CE_LN_1, 0x09, true}, + {FSD_PCIE_PHY_TRSV_REG0CE_LN_2, 0x09, true}, + {FSD_PCIE_PHY_TRSV_REG0CE_LN_3, 0x09, true}, + {FSD_PCIE_PHY_TRSV_REG0FE_LN_N, 0x33, false}, + {FSD_PCIE_PHY_TRSV_REG001_LN_N, 0x3f, false}, + {FSD_PCIE_PHY_TRSV_REG005_LN_N, 0x2b, false}, +}; + +static void fsd_pcie_phy_writel(struct exynos_pcie_phy *phy_ctrl, + u32 val, u32 offset) +{ + struct fsd_pcie_phy_pdata *pdata =3D &fsd_phy_con[phy_ctrl->phy_id]; + void __iomem *phy_base =3D phy_ctrl->base; + u32 i; + + for (i =3D 0; i < pdata->num_lanes; i++) + writel(val, phy_base + (offset + i * pdata->lane_offset)); +} + +static int fsd_pcie_phy_reset(struct phy *phy) +{ + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + struct fsd_pcie_phy_pdata *pdata =3D &fsd_phy_con[phy_ctrl->phy_id]; + + writel(0x1, phy_ctrl->pcs_base + FSD_PCIE_PCS_CLK); + + regmap_update_bits(phy_ctrl->fsysreg, pdata->phy_con, pdata->phy_con_mask, + 0x0); + regmap_update_bits(phy_ctrl->fsysreg, pdata->phy_con, pdata->phy_aux_en_m= ask, + pdata->phy_aux_en); + regmap_update_bits(phy_ctrl->fsysreg, pdata->phy_con, pdata->phy_ref_sel_= mask, + pdata->phy_ref_sel); + + /* perform init reset release */ + regmap_update_bits(phy_ctrl->fsysreg, pdata->phy_con, + pdata->phy_init_rstn_mask, pdata->phy_init_rstn); + return 0; +} + +static int fsd_pcie_phy_init(struct phy *phy) +{ + struct fsd_pcie_phy_setting *phy_param =3D fsd_pcie_phy0_setting; + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + struct fsd_pcie_phy_pdata *pdata =3D &fsd_phy_con[phy_ctrl->phy_id]; + int len =3D ARRAY_SIZE(fsd_pcie_phy0_setting); + void __iomem *phy_base =3D phy_ctrl->base; + int i; + + fsd_pcie_phy_reset(phy); + + if (phy_ctrl->phy_id =3D=3D 1) { + writel(0x2, phy_base + FSD_PCIE_PHY_CMN_RESET); + phy_param =3D fsd_pcie_phy1_setting; + len =3D ARRAY_SIZE(fsd_pcie_phy1_setting); + } + + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_0); + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_1); + writel(0x00, phy_base + FSD_PCIE_PHY_AGG_BIF_RESET); + writel(0x00, phy_base + FSD_PCIE_PHY_AGG_BIF_CLOCK); + + for (i =3D 0; i < len; i++) { + if (phy_param[i].is_cmn_reg) + writel(phy_param[i].val, phy_base + phy_param[i].addr); + else + fsd_pcie_phy_writel(phy_ctrl, phy_param[i].val, phy_param[i].addr); + } + + if (phy_ctrl->phy_id =3D=3D 1) + writel(0x3, phy_base + FSD_PCIE_PHY_CMN_RESET); + + regmap_update_bits(phy_ctrl->fsysreg, pdata->phy_con, + pdata->phy_cmn_rstn_mask, pdata->phy_cmn_rstn); + + return 0; +} + +static const struct phy_ops fsd_phy_ops =3D { + .init =3D fsd_pcie_phy_init, + .reset =3D fsd_pcie_phy_reset, + .owner =3D THIS_MODULE, +}; + +static const struct samsung_drv_data exynos5433_drv_data =3D { + .phy_ops =3D &exynos5433_phy_ops, +}; + +static const struct samsung_drv_data fsd_drv_data =3D { + .phy_ops =3D &fsd_phy_ops, +}; + static const struct of_device_id exynos_pcie_phy_match[] =3D { { .compatible =3D "samsung,exynos5433-pcie-phy", + .data =3D &exynos5433_drv_data, + }, + { + .compatible =3D "tesla,fsd-pcie-phy", + .data =3D &fsd_drv_data, }, {}, }; @@ -146,11 +491,18 @@ static int exynos_pcie_phy_probe(struct platform_devi= ce *pdev) struct exynos_pcie_phy *exynos_phy; struct phy *generic_phy; struct phy_provider *phy_provider; + const struct samsung_drv_data *drv_data; + + drv_data =3D of_device_get_match_data(dev); + if (!drv_data) + return -ENODEV; =20 exynos_phy =3D devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL); if (!exynos_phy) return -ENOMEM; =20 + exynos_phy->drv_data =3D drv_data; + exynos_phy->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(exynos_phy->base)) return PTR_ERR(exynos_phy->base); @@ -169,12 +521,15 @@ static int exynos_pcie_phy_probe(struct platform_devi= ce *pdev) return PTR_ERR(exynos_phy->fsysreg); } =20 - generic_phy =3D devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops); + generic_phy =3D devm_phy_create(dev, dev->of_node, drv_data->phy_ops); if (IS_ERR(generic_phy)) { dev_err(dev, "failed to create PHY\n"); return PTR_ERR(generic_phy); } =20 + exynos_phy->pcs_base =3D devm_platform_ioremap_resource(pdev, 1); + exynos_phy->phy_id =3D of_alias_get_id(dev->of_node, "pciephy"); + phy_set_drvdata(generic_phy, exynos_phy); phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); =20 --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10AD274FCA for ; Mon, 19 May 2025 09:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647015; cv=none; b=CLNa92qiJh0zgoZ/U4nXkcUTKHiGE1MzQT2ELKClF7/BROvBhjgt+0qoL4bvFJsYYKUtgXttmZCKSjzpBf+HVLk/iT+vfOv+4a9wqYFZBdys+T2u6HkBytT0BBx+NvpuiX3DiaNCvy6Dn7eV8CYFMP1O1BkOPnC6b8oo1fw5MaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647015; c=relaxed/simple; bh=fByouTismpV6LoWSPRah4Un6a1qHkZ36BKHM45wfpMY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=b6Uz9dW7CAwSO1hlfhZH4TnGzbDe9zvc5U31JN/mbVUZMe1aV3iyJ/IaPPKYP9MbtgjlK94ecLgOUeb0C57UinFrKlQBO6/lBe2TE6rFi7Aj5cgrWDQXUk8GFM4hE1Rp4gdnteTmgjgeBiHCfBhwJn0UmZaBpqRTO/SjLzbrp4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=lBsJoyn8; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="lBsJoyn8" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250519093010epoutp0125c9aa944f9f63cef6a9473c4d90ec1b~A47JFL9sw2770027700epoutp011 for ; Mon, 19 May 2025 09:30:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250519093010epoutp0125c9aa944f9f63cef6a9473c4d90ec1b~A47JFL9sw2770027700epoutp011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747647010; bh=7IiVDKeuT6ksxMCu0KcGg4lZAvWupjIAe2fDKqXfIqc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lBsJoyn84vC1WWLidbGzombtrLDGYiAQ9ePtySe+o/LVpsDT1+wv9gad3FfALgIxM uyClLmVvJ3hKkirAKG35T9fCggEkQPjFbTG/SgVEvbj4FIcz4qVjCe0mD8ae65Dgh+ 2wgr6rW/vYeOQI1LZ2bXUPHzZWBwu679xZWjGy5Y= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPS id 20250519093009epcas5p4a11a3b2bf57a994aa57192c95cb235da~A47IckQK50267802678epcas5p4W; Mon, 19 May 2025 09:30:09 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.180]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4b1C8J2FDvz6B9mC; Mon, 19 May 2025 09:30:08 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250518193300epcas5p17e954bb18de9169d65e00501b1dcd046~AtgM2q0TF2916729167epcas5p1E; Sun, 18 May 2025 19:33:00 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193300epsmtrp12c671528e52872ad9869e0ea34bbcc3c~AtgM1qoa-2903229032epsmtrp1B; Sun, 18 May 2025 19:33:00 +0000 (GMT) X-AuditID: b6c32a28-46cef70000001e8a-fa-682a35eb53ae Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id C1.6A.07818.BE53A286; Mon, 19 May 2025 04:33:00 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193257epsmtip16ee2ea24b3efe12f48092e9e99ba7067~AtgJ8nW1U1176111761epsmtip1L; Sun, 18 May 2025 19:32:57 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC Date: Mon, 19 May 2025 01:01:51 +0530 Message-ID: <20250518193152.63476-10-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsWy7bCSnO4bU60Mg/k7mC0ezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugSvj3sNDTAVfEir2nPrF1MB4yr+LkYNDQsBEYk2zTRcjJ4eQwG5GiUc/OEBsCQFJic8X 1zFB2MISK/89Z+9i5AKq+cQosX/ySjaQBJuAlkTj1y5mEFtE4ASjRN8tS5AiZoH3TBIzF/wC 6xYWcJS4tmAOC4jNIqAqsfVVHzPIYl4Ba4n+ByUQN8hL9HdIgFRwAkW3rZ/KBHGPlcTCJzsZ QWxeAUGJkzOfgE1hBipv3jqbeQKjwCwkqVlIUgsYmVYxSqYWFOem5yYbFhjmpZbrFSfmFpfm pesl5+duYgTHoZbGDsZ335r0DzEycTAeYpTgYFYS4V21WSNDiDclsbIqtSg/vqg0J7X4EKM0 B4uSOO9Kw4h0IYH0xJLU7NTUgtQimCwTB6dUA5McQ7nN0zv+CvNbbFtvmGXtZ7tw0UdfY9bT Q8cZgrnrLT+eOvMiKrbyWOUU6TJX5i0xG/Tnepq+eeEpL/278PWrrXtWpDXn+n9eOL3/nTdD vHzkn5M2vz8dWc82L/bH5re7FV4eS35h/93FYlpcF0/53McbD/THqfWWdj1LFas0LKrlTkvj dfgRcav99O1kkzmTG7LfXH4leb3r0/qaJnF3+d6FLN8OxDntteXaK76WsfzmXMeQHAHeD2/K WWIu1b56wigsXsas/Nna74G0YBN/wc3NB+/Ou76z7OGNA0eurtFTe6T0eJHXt49/vr3RfRMw U4JFPPX5pj1fVj30ktG+lN+ttFj44dJlsx3upsxWYinOSDTUYi4qTgQAF91GEDIDAAA= X-CMS-MailID: 20250518193300epcas5p17e954bb18de9169d65e00501b1dcd046 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193300epcas5p17e954bb18de9169d65e00501b1dcd046 References: <20250518193152.63476-1-shradha.t@samsung.com> Add host and endpoint controller driver support for FSD SoC. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 330 +++++++++++++++++++++++- 1 file changed, 322 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index b122a2ae8681..97953cc73aa2 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include =20 #include "pcie-designware.h" =20 @@ -49,17 +51,46 @@ #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 +#define FSD_IRQ2_STS 0x008 +#define FSD_IRQ_MSI_ENABLE BIT(17) +#define FSD_IRQ2_EN 0x018 +#define FSD_PCIE_APP_LTSSM_ENABLE 0x054 +#define FSD_PCIE_LTSSM_ENABLE 0x1 +#define FSD_PCIE_DEVICE_TYPE 0x080 +#define FSD_DEVICE_TYPE_RC 0x4 +#define FSD_DEVICE_TYPE_EP 0x0 +#define FSD_PCIE_CXPL_DEBUG_00_31 0x2C8 + +/* to store different SoC variants of Samsung */ +enum samsung_pcie_variants { + FSD, + EXYNOS_5433, +}; + +/* Values to be written to SYSREG to view DBI space as CDM/DBI2/IATU/DMA */ +enum fsd_pcie_addr_type { + ADDR_TYPE_DBI =3D 0x0, + ADDR_TYPE_DBI2 =3D 0x12, + ADDR_TYPE_ATU =3D 0x36, + ADDR_TYPE_DMA =3D 0x3f, +}; + struct samsung_pcie_pdata { struct pci_ops *pci_ops; const struct dw_pcie_ops *dwc_ops; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; const struct samsung_res_ops *res_ops; + unsigned int soc_variant; + enum dw_pcie_device_mode device_mode; }; =20 struct exynos_pcie { struct dw_pcie pci; void __iomem *elbi_base; const struct samsung_pcie_pdata *pdata; + struct regmap *sysreg; + unsigned int sysreg_offset; struct clk_bulk_data *clks; struct phy *phy; struct regulator_bulk_data *supplies; @@ -69,6 +100,7 @@ struct exynos_pcie { struct samsung_res_ops { int (*init_regulator)(struct exynos_pcie *ep); irqreturn_t (*pcie_irq_handler)(int irq, void *arg); + void (*set_device_mode)(struct exynos_pcie *ep); }; =20 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -328,11 +360,202 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops = =3D { .start_link =3D exynos_pcie_start_link, }; =20 +static void fsd_pcie_stop_link(struct dw_pcie *pci) +{ + u32 val; + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + val =3D readl(ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); + val &=3D ~FSD_PCIE_LTSSM_ENABLE; + writel(val, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); +} + +static int fsd_pcie_start_link(struct dw_pcie *pci) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + struct dw_pcie_ep *dw_ep =3D &pci->ep; + + if (dw_pcie_link_up(pci)) + return 0; + + writel(FSD_PCIE_LTSSM_ENABLE, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); + + /* no need to wait for link in case of host as core files take care */ + if (ep->pdata->device_mode =3D=3D DW_PCIE_RC_TYPE) + return 0; + + /* check if the link is up or not in case of EP */ + if (!dw_pcie_wait_for_link(pci)) { + dw_pcie_ep_linkup(dw_ep); + return 0; + } + + return -ETIMEDOUT; +} + +static irqreturn_t fsd_pcie_irq_handler(int irq, void *arg) +{ + u32 val; + struct exynos_pcie *ep =3D arg; + struct dw_pcie *pci =3D &ep->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + + val =3D readl(ep->elbi_base + FSD_IRQ2_STS); + if ((val & FSD_IRQ_MSI_ENABLE) =3D=3D FSD_IRQ_MSI_ENABLE) { + val &=3D FSD_IRQ_MSI_ENABLE; + writel(val, ep->elbi_base + FSD_IRQ2_STS); + dw_handle_msi_irq(pp); + } + + return IRQ_HANDLED; +} + +static void fsd_pcie_msi_init(struct exynos_pcie *ep) +{ + int val; + + val =3D readl(ep->elbi_base + FSD_IRQ2_EN); + val |=3D FSD_IRQ_MSI_ENABLE; + writel(val, ep->elbi_base + FSD_IRQ2_EN); +} + +static void __iomem *fsd_atu_setting(struct dw_pcie *pci, void __iomem *ba= se) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + if (base >=3D pci->atu_base) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_ATU); + return (base - DEFAULT_DBI_ATU_OFFSET); + } else if (base =3D=3D pci->dbi_base) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI); + } else if (base =3D=3D pci->dbi_base2) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI2); + } + + return base; +} + +static u32 fsd_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + void __iomem *addr; + u32 val; + + addr =3D fsd_atu_setting(pci, base); + + dw_pcie_read(addr + reg, size, &val); + + return val; +} + +static void fsd_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + void __iomem *addr; + + addr =3D fsd_atu_setting(pci, base); + + dw_pcie_write(addr + reg, size, val); +} + +static void fsd_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + fsd_atu_setting(pci, base); + dw_pcie_write(pci->dbi_base + reg, size, val); + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI); +} + +static int fsd_pcie_link_up(struct dw_pcie *pci) +{ + u32 val; + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + val =3D readl(ep->elbi_base + FSD_PCIE_CXPL_DEBUG_00_31); + val &=3D PORT_LOGIC_LTSSM_STATE_MASK; + + return (val =3D=3D PORT_LOGIC_LTSSM_STATE_L0); +} + +static int fsd_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + phy_init(ep->phy); + fsd_pcie_msi_init(ep); + + return 0; +} + +static const struct dw_pcie_host_ops fsd_pcie_host_ops =3D { + .init =3D fsd_pcie_host_init, +}; + +static int fsd_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + case PCI_IRQ_MSIX: + dev_err(pci->dev, "EP does not support legacy IRQs\n"); + return -EINVAL; + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static const struct pci_epc_features fsd_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, +}; + +static const struct pci_epc_features *fsd_pcie_get_features(struct dw_pcie= _ep *ep) +{ + return &fsd_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops fsd_ep_ops =3D { + .raise_irq =3D fsd_pcie_raise_irq, + .get_features =3D fsd_pcie_get_features, +}; + +static void fsd_set_device_mode(struct exynos_pcie *ep) +{ + if (ep->pdata->device_mode =3D=3D DW_PCIE_RC_TYPE) + writel(FSD_DEVICE_TYPE_RC, ep->elbi_base + FSD_PCIE_DEVICE_TYPE); + else + writel(FSD_DEVICE_TYPE_EP, ep->elbi_base + FSD_PCIE_DEVICE_TYPE); +} + +static const struct dw_pcie_ops fsd_dw_pcie_ops =3D { + .read_dbi =3D fsd_pcie_read_dbi, + .write_dbi =3D fsd_pcie_write_dbi, + .write_dbi2 =3D fsd_pcie_write_dbi2, + .start_link =3D fsd_pcie_start_link, + .stop_link =3D fsd_pcie_stop_link, + .link_up =3D fsd_pcie_link_up, +}; + static const struct samsung_res_ops exynos_res_ops_data =3D { .init_regulator =3D exynos_init_regulator, .pcie_irq_handler =3D exynos_pcie_irq_handler, }; =20 +static const struct samsung_res_ops fsd_res_ops_data =3D { + .pcie_irq_handler =3D fsd_pcie_irq_handler, + .set_device_mode =3D fsd_set_device_mode, +}; + static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -355,6 +578,26 @@ static int exynos_pcie_probe(struct platform_device *p= dev) if (IS_ERR(ep->phy)) return PTR_ERR(ep->phy); =20 + if (ep->pdata->soc_variant =3D=3D FSD) { + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); + if (ret) + return ret; + + ep->sysreg =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,syscon-pcie"); + if (IS_ERR(ep->sysreg)) { + dev_err(dev, "sysreg regmap lookup failed.\n"); + return PTR_ERR(ep->sysreg); + } + + ret =3D of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", = 1, + &ep->sysreg_offset); + if (ret) { + dev_err(dev, "couldn't get the register offset for syscon!\n"); + return ret; + } + } + /* External Local Bus interface (ELBI) registers */ ep->elbi_base =3D devm_platform_ioremap_resource_byname(pdev, "elbi"); if (IS_ERR(ep->elbi_base)) @@ -375,13 +618,43 @@ static int exynos_pcie_probe(struct platform_device *= pdev) return ret; =20 platform_set_drvdata(pdev, ep); - ret =3D samsung_irq_init(ep, pdev); - if (ret) - goto fail_regulator; - ep->pci.pp.ops =3D pdata->host_ops; - ret =3D dw_pcie_host_init(&ep->pci.pp); - if (ret < 0) + + if (pdata->res_ops->set_device_mode) + pdata->res_ops->set_device_mode(ep); + + switch (ep->pdata->device_mode) { + case DW_PCIE_RC_TYPE: + ret =3D samsung_irq_init(ep, pdev); + if (ret) + goto fail_regulator; + + ep->pci.pp.ops =3D pdata->host_ops; + + ret =3D dw_pcie_host_init(&ep->pci.pp); + if (ret < 0) + goto fail_phy_init; + + break; + case DW_PCIE_EP_TYPE: + phy_init(ep->phy); + + ep->pci.ep.ops =3D pdata->ep_ops; + + ret =3D dw_pcie_ep_init(&ep->pci.ep); + if (ret < 0) + goto fail_phy_init; + + ret =3D dw_pcie_ep_init_registers(&ep->pci.ep); + if (ret) + goto fail_phy_init; + + pci_epc_init_notify(ep->pci.ep.epc); + + break; + default: + dev_err(dev, "invalid device type\n"); goto fail_phy_init; + } =20 return 0; =20 @@ -397,8 +670,11 @@ static void exynos_pcie_remove(struct platform_device = *pdev) { struct exynos_pcie *ep =3D platform_get_drvdata(pdev); =20 + if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) + return; dw_pcie_host_deinit(&ep->pci.pp); - exynos_pcie_assert_core_reset(ep); + if (ep->pdata->soc_variant =3D=3D EXYNOS_5433) + exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); samsung_regulator_disable(ep); @@ -407,8 +683,16 @@ static void exynos_pcie_remove(struct platform_device = *pdev) static int exynos_pcie_suspend_noirq(struct device *dev) { struct exynos_pcie *ep =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &ep->pci; =20 - exynos_pcie_assert_core_reset(ep); + if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) + return 0; + + if (ep->pdata->dwc_ops->stop_link) + ep->pdata->dwc_ops->stop_link(pci); + + if (ep->pdata->soc_variant =3D=3D EXYNOS_5433) + exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); samsung_regulator_disable(ep); @@ -423,6 +707,9 @@ static int exynos_pcie_resume_noirq(struct device *dev) struct dw_pcie_rp *pp =3D &pci->pp; int ret; =20 + if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) + return 0; + ret =3D samsung_regulator_enable(ep); if (ret) return ret; @@ -439,11 +726,30 @@ static const struct dev_pm_ops exynos_pcie_pm_ops =3D= { exynos_pcie_resume_noirq) }; =20 + +static const struct samsung_pcie_pdata fsd_hw3_pcie_rc_pdata =3D { + .dwc_ops =3D &fsd_dw_pcie_ops, + .host_ops =3D &fsd_pcie_host_ops, + .res_ops =3D &fsd_res_ops_data, + .soc_variant =3D FSD, + .device_mode =3D DW_PCIE_RC_TYPE, +}; + +static const struct samsung_pcie_pdata fsd_hw3_pcie_ep_pdata =3D { + .dwc_ops =3D &fsd_dw_pcie_ops, + .ep_ops =3D &fsd_ep_ops, + .res_ops =3D &fsd_res_ops_data, + .soc_variant =3D FSD, + .device_mode =3D DW_PCIE_EP_TYPE, +}; + static const struct samsung_pcie_pdata exynos_5433_pcie_rc_pdata =3D { .dwc_ops =3D &exynos_dw_pcie_ops, .pci_ops =3D &exynos_pci_ops, .host_ops =3D &exynos_pcie_host_ops, .res_ops =3D &exynos_res_ops_data, + .soc_variant =3D EXYNOS_5433, + .device_mode =3D DW_PCIE_RC_TYPE, }; =20 static const struct of_device_id exynos_pcie_of_match[] =3D { @@ -451,6 +757,14 @@ static const struct of_device_id exynos_pcie_of_match[= ] =3D { .compatible =3D "samsung,exynos5433-pcie", .data =3D (void *) &exynos_5433_pcie_rc_pdata, }, + { + .compatible =3D "tesla,fsd-pcie", + .data =3D (void *) &fsd_hw3_pcie_rc_pdata, + }, + { + .compatible =3D "tesla,fsd-pcie-ep", + .data =3D (void *) &fsd_hw3_pcie_ep_pdata, + }, { }, }; =20 --=20 2.49.0 From nobody Fri Dec 19 17:23:31 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E12FB274FD0 for ; Mon, 19 May 2025 09:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647018; cv=none; b=GTe4Wp1nW21Ni5WIUpmyUDOgp2hIWz6zvsxXiVCmNWgMZ4F6x7heL/sC9R5bd6G7FrlHc9vvFpSqzvIiNr8cjzgTGRT9v6HQRSpEGAB9dnM7Ag0F6Ws6DoEehQj9pU47/oX1truKHgmwaowNNrlXLImvH9DNUdYlwQsq8pdBElE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747647018; c=relaxed/simple; bh=ej4v934Mw6xmD65+BX8cBOhGE4lCaEYcsDyq0osmCIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=XU0KSwuz9DLeq2LHFjbKVas+AB7zFGzPw5eAJv5P3BMEJcgKXVzb8j9P7XLONRxUSBsJb5cFUDZqv+g9wtNQFxhD/AMPW8rFhTk5FZ6RQLaKazBPh9sQJuazivDqTNY6TrLTMTusAXHhEtjYTW/pgT0Y6o0GNflbHvPpJJVERSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=mWrJuSD1; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="mWrJuSD1" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250519093015epoutp04f4ddd7433179efdf9b699183dd0cb915~A47NnwoJ61577715777epoutp04z for ; Mon, 19 May 2025 09:30:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250519093015epoutp04f4ddd7433179efdf9b699183dd0cb915~A47NnwoJ61577715777epoutp04z DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1747647015; bh=3JXJPK8Pxeu+1hTQ6X+A9fh/NPx5Fi27JyhWAictUa0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mWrJuSD1Bu1XE6n79VK8PSLESyAOwgwXCTZkqyuntj1p2LE+Bl8EeACGopzO2DfL5 U87wbJNIy+0Xx+jvEkYgftCnk/KsGbuXrIVfHhfsvp2QxZ44dbr63YUUkDxVxaGtp9 UlAhs9j8nF2JtL+3LW9NDKsysZfF+ZFQGNkysMRk= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPS id 20250519093014epcas5p499efbb243762f4c0d7b482ab6d6e64dd~A47NDNaaO0739507395epcas5p47; Mon, 19 May 2025 09:30:14 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.177]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4b1C8N23NWz6B9mW; Mon, 19 May 2025 09:30:12 +0000 (GMT) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250518193305epcas5p263b59196e93ef504eab8537f82c37342~AtgRoIaZN2822528225epcas5p2x; Sun, 18 May 2025 19:33:05 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250518193305epsmtrp158ea8f08c187125ab00047b623695cfc~AtgRmSg2r2903229032epsmtrp1D; Sun, 18 May 2025 19:33:05 +0000 (GMT) X-AuditID: b6c32a28-46cef70000001e8a-02-682a35f1b01d Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 63.6A.07818.1F53A286; Mon, 19 May 2025 04:33:05 +0900 (KST) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250518193302epsmtip183267af4e412e5df727520c6d803b916~AtgO3rs881176111761epsmtip1O; Sun, 18 May 2025 19:33:02 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, Shradha Todi Subject: [PATCH 10/10] misc: pci_endpoint_test: Add driver data for FSD PCIe controllers Date: Mon, 19 May 2025 01:01:52 +0530 Message-ID: <20250518193152.63476-11-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250518193152.63476-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWy7bCSnO5HU60Mg+kHhC0ezNvGZvF30jF2 iyVNGRZr9p5jsph/5ByrxY1fbawWK77MZLc42vqf2eLlrHtsFg09v1ktNj2+xmpxedccNouz 846zWUxY9Y3F4uz3BUwWLX9aWCzWHrnLbnG3pZPV4v+eHewWvYdrLXbeOcHsIOrx+9ckRo+d s+6yeyzYVOqxaVUnm8eda3vYPJ5cmc7ksXlJvUffllWMHke+Tmfx+LxJLoArissmJTUnsyy1 SN8ugStjyYJ9LAV3uSoOrd/F3sDYy9nFyMEhIWAiMX02YxcjJ4eQwG5GicY3+iC2hICkxOeL 65ggbGGJlf+es3cxcgHVfGKU+Ny2iA0kwSagJdH4tYsZxBYROMEo0XfLEqSIWeA9k8TMBb/A uoUFIiQuXNsG1sAioCrxeOtHdhCbV8Ba4sydLewQR8hL9HdIgIQ5gcLb1k9lgjjISmLhk52M EOWCEidnPmEBsZmBypu3zmaewCgwC0lqFpLUAkamVYySqQXFuem5yYYFhnmp5XrFibnFpXnp esn5uZsYwZGopbGD8d23Jv1DjEwcjIcYJTiYlUR4V23WyBDiTUmsrEotyo8vKs1JLT7EKM3B oiTOu9IwIl1IID2xJDU7NbUgtQgmy8TBKdXAFN7Ve33a3sO3D+05uOWgFm//iZDJhpbn2HJn Bwd9bWFqfTnrgfqXdTPuPMx+UzDlT46Y14SjMr4VBSs/7VgT+b8xTPTSKj7uE+pn90Yoteqt nfuOzeJbmaFz01FbwcthpWziLN+nTvz7dbX+VAPRqA9mN1/9sYtQmcKx4Cz/0We3Zjl7hey+ nGrdn9T4PLq674le9MkXa8RL9s/SaxXcY73NcG1nb8TSW6nJBUqCu0WPFx/2nCHZVmrZyPz2 k/UMMcX6HBXhNMm+C9bd7nuvsxoc/LKeOdDE/esO3h5VrZ7p3Qf+rPn1ycK7+vv81iq31NS1 V1i37Te5pbtBZfu+d1KGrZM6V3RKqwh2LFp8QomlOCPRUIu5qDgRAORarhIzAwAA X-CMS-MailID: 20250518193305epcas5p263b59196e93ef504eab8537f82c37342 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193305epcas5p263b59196e93ef504eab8537f82c37342 References: <20250518193152.63476-1-shradha.t@samsung.com> dma_map_single() might not return a 4KB aligned address, so add the default_data as driver data for FSD PCIe controllers to make it 4KB aligned. Signed-off-by: Shradha Todi --- drivers/misc/pci_endpoint_test.c | 3 +++ include/linux/pci_ids.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_t= est.c index c4e5e2c977be..d94a94231ee5 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -1110,6 +1110,9 @@ static const struct pci_device_id pci_endpoint_test_t= bl[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A), .driver_data =3D (kernel_ulong_t)&default_data, }, + { PCI_DEVICE(PCI_VENDOR_ID_TESLA, 0x7777), + .driver_data =3D (kernel_ulong_t)&default_data, + }, { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), .driver_data =3D (kernel_ulong_t)&am654_data diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 2e28182c3af0..e0afc5aa1c0e 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -167,6 +167,8 @@ =20 #define PCI_VENDOR_ID_SOLIDIGM 0x025e =20 +#define PCI_VENDOR_ID_TESLA 0x014a + #define PCI_VENDOR_ID_TTTECH 0x0357 #define PCI_DEVICE_ID_TTTECH_MC322 0x000a =20 --=20 2.49.0