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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 05:48:09.1767 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3d70ee3-536a-4528-c34e-08dd95cf91ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4399 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Fixes a security bug due to mismatched attributes between S1 and S2 mapping. Currently, it is possible for a region to be cacheable in S1, but mapped non cached in S2. This creates a potential issue where the VMM may sanitize cacheable memory across VMs using cacheable stores, ensuring it is zeroed. However, if KVM subsequently assigns this memory to a VM as uncached, the VM could end up accessing stale, non-zeroed data from a previous VM, leading to unintended data exposure. This is a security risk. Block such mismatch attributes case by returning EINVAL when userspace try to map PFNMAP cacheable. CC: Oliver Upton CC: Sean Christopherson Suggested-by: Jason Gunthorpe Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 2feb6c6b63af..eaac4db61828 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1466,6 +1466,15 @@ static bool kvm_vma_mte_allowed(struct vm_area_struc= t *vma) return vma->vm_flags & VM_MTE_ALLOWED; } =20 +/* + * Determine the memory region cacheability from VMA's pgprot. This + * is used to set the stage 2 PTEs. + */ +static unsigned long mapping_type(pgprot_t page_prot) +{ + return FIELD_GET(PTE_ATTRINDX_MASK, pgprot_val(page_prot)); +} + static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_s2_trans *nested, struct kvm_memory_slot *memslot, unsigned long hva, @@ -1612,6 +1621,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, =20 vfio_allow_any_uc =3D vma->vm_flags & VM_ALLOW_ANY_UNCACHED; =20 + if ((vma->vm_flags & VM_PFNMAP) && + mapping_type(vma->vm_page_prot) =3D=3D MT_NORMAL) + return -EINVAL; + /* Don't use the VMA after the unlock -- it may have vanished */ vma =3D NULL; =20 @@ -2207,6 +2220,12 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, ret =3D -EINVAL; break; } + + /* Cacheable PFNMAP is not allowed */ + if (mapping_type(vma->vm_page_prot) =3D=3D MT_NORMAL) { + ret =3D -EINVAL; + break; + } } hva =3D min(reg_end, vma->vm_end); } while (hva < reg_end); --=20 2.34.1 From nobody Fri Dec 19 17:20:13 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2071.outbound.protection.outlook.com [40.107.92.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BB83142E83 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 05:48:06.8862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c48f7870-68cb-4244-c805-08dd95cf905f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Change the scope of stage2_has_fwb as it will be used in broader KVM code to determine whether the FWB feature is supported by the hardware. Signed-off-by: Ankit Agrawal --- arch/arm64/include/asm/kvm_pgtable.h | 8 ++++++++ arch/arm64/kvm/hyp/pgtable.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 6b9d274052c7..f21e2fae2bfe 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -507,6 +507,14 @@ u64 kvm_pgtable_hyp_unmap(struct kvm_pgtable *pgt, u64= addr, u64 size); */ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift); =20 +/** + * stage2_has_fwb() - Determine whether FWB is supported + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*() + * + * Return: True if FWB is supported. + */ +bool stage2_has_fwb(struct kvm_pgtable *pgt); + /** * kvm_pgtable_stage2_pgd_size() - Helper to compute size of a stage-2 PGD * @vtcr: Content of the VTCR register. diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index df5cc74a7dd0..ee6b98fefd61 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -637,7 +637,7 @@ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift) return vtcr; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 05:48:08.3008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3369aa85-7d0e-48e4-a5ed-08dd95cf9140 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4361 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Introduce a new memslot flag KVM_MEM_ENABLE_CACHEABLE_PFNMAP as a tool for userspace to indicate that it expects a particular PFN range to be mapped cacheable. This will serve as a guide for the KVM to activate the code that allows cacheable PFNMAP. CC: Oliver Upton CC: Catalin Marinas CC: Jason Gunthorpe Suggested-by: Marc Zyngier Signed-off-by: Ankit Agrawal --- include/uapi/linux/kvm.h | 1 + virt/kvm/kvm_main.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index b6ae8ad8934b..9defefe7bdf0 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -51,6 +51,7 @@ struct kvm_userspace_memory_region2 { #define KVM_MEM_LOG_DIRTY_PAGES (1UL << 0) #define KVM_MEM_READONLY (1UL << 1) #define KVM_MEM_GUEST_MEMFD (1UL << 2) +#define KVM_MEM_ENABLE_CACHEABLE_PFNMAP (1UL << 3) =20 /* for KVM_IRQ_LINE */ struct kvm_irq_level { diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index e85b33a92624..a3e77fe57cc4 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -1524,12 +1524,14 @@ static void kvm_replace_memslot(struct kvm *kvm, * only allows these. */ #define KVM_SET_USER_MEMORY_REGION_V1_FLAGS \ - (KVM_MEM_LOG_DIRTY_PAGES | KVM_MEM_READONLY) + (KVM_MEM_LOG_DIRTY_PAGES | KVM_MEM_READONLY | \ + KVM_MEM_ENABLE_CACHEABLE_PFNMAP) =20 static int check_memory_region_flags(struct kvm *kvm, const struct kvm_userspace_memory_region2 *mem) { - u32 valid_flags =3D KVM_MEM_LOG_DIRTY_PAGES; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 05:48:11.9040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed51a05a-ae2f-47b5-6a48-08dd95cf935d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6689 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Today KVM forces the memory to either NORMAL or DEVICE_nGnRE based on pfn_is_map_memory (which tracks whether the device memory is added to the kernel) and ignores the per-VMA flags that indicates the memory attributes. The KVM code is thus restrictive and allows only for the memory that is added to the kernel to be marked as cacheable. The device memory such as on the Grace Hopper/Blackwell systems is interchangeable with DDR memory and retains properties such as cacheability, unaligned accesses, atomics and handling of executable faults. This requires the device memory to be mapped as NORMAL in stage-2. Given that the GPU device memory is not added to the kernel (but is rather VMA mapped through remap_pfn_range() in nvgrace-gpu module which sets VM_PFNMAP), pfn_is_map_memory() is false and thus KVM prevents such memory to be mapped Normal cacheable. The patch aims to solve this use case. A cachebility check is made if the VM_PFNMAP is set in VMA flags by consulting the VMA pgprot value. If the pgprot mapping type is MT_NORMAL, it is safe to be mapped cacheable as the KVM S2 will have the same Normal memory type as the VMA has in the S1 and KVM has no additional responsibility for safety. Checking pgprot as NORMAL is thus a KVM sanity check. Introduce a new variable cacheable_devmem to indicate a safely cacheable mapping. Do not set the device variable when cacheable_devmem is true. This essentially have the effect of setting stage-2 mapping as NORMAL through kvm_pgtable_stage2_map. Add check for COW VM_PFNMAP and refuse such mapping. No additional checks for MTE are needed as kvm_arch_prepare_memory_region() already tests it at an early stage during memslot creation. There would not even be a fault if the memslot is not created. Note when FWB is not enabled, the kernel expects to trivially do cache management by flushing the memory by linearly converting a kvm_pte to phys_addr to a KVA, see kvm_flush_dcache_to_poc(). The cache management thus relies on memory being mapped. So do not allow !FWB. Lastly ARM64_HAS_CACHE_DIC CPU cap allows KVM to avoid flushing the icache and turns icache_inval_pou() into a NOP. This is also thus a requirement of the cacheable PFNMAP feature. Disallow cacheable PFNMAP on hardware with no ARM64_HAS_CACHE_DIC. CC: Oliver Upton Suggested-by: Jason Gunthorpe Suggested-by: Catalin Marinas Suggested-by: David Hildenbrand Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 43 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index eaac4db61828..3ee2691466fa 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1484,6 +1484,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, bool write_fault, writable, force_pte =3D false; bool exec_fault, mte_allowed; bool device =3D false, vfio_allow_any_uc =3D false; + bool cacheable_devmem =3D false; unsigned long mmu_seq; phys_addr_t ipa =3D fault_ipa; struct kvm *kvm =3D vcpu->kvm; @@ -1621,9 +1622,19 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, =20 vfio_allow_any_uc =3D vma->vm_flags & VM_ALLOW_ANY_UNCACHED; =20 - if ((vma->vm_flags & VM_PFNMAP) && - mapping_type(vma->vm_page_prot) =3D=3D MT_NORMAL) - return -EINVAL; + if (vma->vm_flags & VM_PFNMAP) { + /* Reject COW VM_PFNMAP */ + if (is_cow_mapping(vma->vm_flags)) + return -EINVAL; + + /* + * If the VM_PFNMAP is set in VMA flags, do a KVM sanity + * check to see if pgprot mapping type is MT_NORMAL and a + * safely cacheable device memory. + */ + if (mapping_type(vma->vm_page_prot) =3D=3D MT_NORMAL) + cacheable_devmem =3D true; + } =20 /* Don't use the VMA after the unlock -- it may have vanished */ vma =3D NULL; @@ -1656,10 +1667,13 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, ph= ys_addr_t fault_ipa, * via __kvm_faultin_pfn(), vma_pagesize is set to PAGE_SIZE * and must not be upgraded. * - * In both cases, we don't let transparent_hugepage_adjust() + * Do not set device as the device memory is cacheable. Note + * that such mapping is safe as the KVM S2 will have the same + * Normal memory type as the VMA has in the S1. * change things at the last minute. */ - device =3D true; + if (!cacheable_devmem) + device =3D true; } else if (logging_active && !write_fault) { /* * Only actually map the page as writable if this was a write @@ -1741,6 +1755,20 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, prot |=3D KVM_PGTABLE_PROT_X; } =20 + /* + * When FWB is unsupported KVM needs to do cache flushes + * (via dcache_clean_inval_poc()) of the underlying memory. This is + * only possible if the memory is already mapped into the kernel map. + * + * Outright reject as the cacheable device memory is not present in + * the kernel map and not suitable for cache management. + */ + if (cacheable_devmem && (!cpus_have_final_cap(ARM64_HAS_CACHE_DIC) || + !stage2_has_fwb(pgt))) { + ret =3D -EINVAL; + goto out_unlock; + } + /* * Under the premise of getting a FSC_PERM fault, we just need to relax * permissions only if vma_pagesize equals fault_granule. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 05:48:13.9505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f184e58-7a3b-493f-6324-08dd95cf949c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9388 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Introduce a new KVM capability to expose to the userspace whether cacheable mapping of PFNMAP is supported. The ability to safely do the cacheable mapping of PFNMAP is contingent on S2FWB and ARM64_HAS_CACHE_DIC. S2FWB allows KVM to avoid flushing the D cache, ARM64_HAS_CACHE_DIC allows KVM to avoid flushing the icache and turns icache_inval_pou() into a NOP. The cap would be false if those requirements are missing. This capability would allow userspace to discover the support. This would be used in conjunction with the KVM_MEM_ENABLE_CACHEABLE_PFNMAP memslot flag. Userspace is required to query this capability before it can set the memslot flag. This cap could also be used by userspace to prevent live-migration across FWB and non-FWB hosts. CC: Catalin Marinas CC: Jason Gunthorpe CC: Oliver Upton Suggested-by: Marc Zyngier Signed-off-by: Ankit Agrawal --- Documentation/virt/kvm/api.rst | 17 ++++++++++++++++- arch/arm64/kvm/arm.c | 8 ++++++++ include/uapi/linux/kvm.h | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 47c7c3f92314..ad4c5e131977 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -8478,7 +8478,7 @@ ENOSYS for the others. When enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request. =20 -7.37 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS +7.42 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS ------------------------------------- =20 :Architectures: arm64 @@ -8496,6 +8496,21 @@ aforementioned registers before the first KVM_RUN. T= hese registers are VM scoped, meaning that the same set of values are presented on all vCPUs in a given VM. =20 +7.43 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED +------------------------------------------- + +:Architectures: arm64 +:Target: VM +:Parameters: None + +This capability indicate to the userspace whether a PFNMAP memory region +can be safely mapped as cacheable. This relies on the presence of +force write back (FWB) feature support on the hardware. + +The usermode could query this capability and subsequently set the +KVM_MEM_ENABLE_CACHEABLE_PFNMAP memslot flag forming a handshake to +activate the code. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 68fec8c95fee..7855f579fb82 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -402,6 +402,14 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long= ext) case KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES: r =3D BIT(0); break; + case KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED: + if (!kvm) + r =3D -EINVAL; + else + r =3D stage2_has_fwb(kvm->arch.mmu.pgt) && + cpus_have_final_cap(ARM64_HAS_CACHE_DIC); + break; + default: r =3D 0; } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 9defefe7bdf0..fb868586d73d 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -931,6 +931,7 @@ struct kvm_enable_cap { #define KVM_CAP_X86_APIC_BUS_CYCLES_NS 237 #define KVM_CAP_X86_GUEST_MODE 238 #define KVM_CAP_ARM_WRITABLE_IMP_ID_REGS 239 +#define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 240 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; --=20 2.34.1